52483839 Microprocessor 8085 Notes

8/13/2019 52483839 Microprocessor 8085 Notes

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Mahendra Engineering College

Mahendhirapuri

Department of ECE

AIM

To learn the architecture, programming and interfacing of microprocessors and microcontrollers.

OBJECTIVES

To introduce the architecture and programming of 8085 microprocessor.

To introduce the interfacing of peripheral devices with 8085 microprocessor.

To introduce the architecture and programming of 8086 microprocessor.

To introduce the architecture, programming and interfacing of 8051 micro controller.

UNIT I 8085 CPU 9

8085 Architecture Instruction set Addressing modes Timing diagrams Asseml! language

programming "ounters Time #ela!s Interrupts $emor! interfacing Interfacing, I%& devices.

UNIT II PERIPHERALS INTERFACING 9

Interfacing 'erial I%& (8)51*+ parallel I%& (8)55* e!oard and #ispla! controller (8)-* A#"%#A"

interfacing Inter Integrated "ircuits interfacing (I)" 'tandard*+ /us ')2)"+'385+4I/

UNIT III 8086 CPU 9

Intel 8086 Internal Architecture 8086 Addressing modes+ Instruction set+ 8086 Asseml! language

rogrammingInterrupts.

UNIT IV 8051 MICROCONTROLLER 9

8051 $icro controller hardware+ I%& pins, ports and circuits+ 7ternal memor! "ounters and Timers+'erial

#ata I%&+ Interrupts+Interfacing to e7ternal memor! and 8)55.

UNIT V 8051 PROGRAMMING AND APPLICATIONS 9

8051 instruction set Addressing modes Asseml! language programming I%& port programming +Timer

and counter programming 'erial "ommunication Interrupt programming 8051 Interfacing "#, A#",

'ensors, 'tepper $otors, e!oard and #A".

TOTAL : 45TEXT BOOKS

1. amesh ' 4aon9ar, $icroprocessor Architecture, rogramming and application with 8085, 3thdition,

enram International ulishing, :ew #elhi, )000. (;nit I, II*

). idi and idi, The 8051 $icrocontroller and medded '!stems,

earson ducation Asia, :ew #elhi, )002. (;nit I?, ?*

EC10 ! M"#$%&$%#'((%$ )*+ ",( )&&-"#),"%*(


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UNIT I INTEL 8085

1.1 INTRODUCTION TO MICROPROCESSOR BASED S/STEM

The microprocessor is a semiconductor device (Integrated "ircuit* manufactured ! the ?'I (?er!

arge 'cale Integration* techni@ue. It includes the A;, register arra!s and control circuit on a

single chip. To perform a function or useful tas9 we have to form a s!stem ! using microprocessor

as a "; and interfacing memor!, input and output devices to it. A s!stem designed using amicroprocessor as its "; is called a microcomputer.

The $icroprocessor ased s!stem (single oard microcomputer* consists of microprocessor as

";, semiconductor memories li9e &$ and A$, input device, output device and interfacing

devices. The memories, input device, output device and interfacing devices are called peripherals.

The popular input devices are 9e!oard and flopp! dis9 and the output devices are printer,

#%"# displa!s, "T monitor, etc.

The aove loc9 diagram shows the organi>ation of a microprocessor ased s!stem. In this s!stem,

the microprocessor is the master and all other peripherals are slaves. The master controls all the

peripherals and initiates all operations.

The wor9 done ! the processor can e classified into the following three groups.

1. or9 done internal to the processor

). or9 done e7ternal to the processor

2. &perations initiated ! the slaves or peripherals.

The wor9 done internal to the processors are addition, sutraction, logical operations, data transfer

operations, etc. The wor9 done e7ternal to the processor are reading%writing the memor! and

reading%writing the


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The microprocessor is the master, which controls all the activities of the s!stem. To perform a

specific Bo or tas9, the microprocessor has to e7ecute a program stored in memor!. The programconsists of a set of instructions. It issues address and control signals and fetches the instruction and

data from memor!. The instruction is e7ecuted one ! one internal to the processor and ased on

the result it ta9es appropriate action.

/;''The uses are group of lines that carries data, address or control signals.

The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals.

The "; interface is provided to demultiple7 the multiple7ed lines, to generate chip selectsignals and additional control signals.

The system bus has separate lines for each signal.

All the slaves in the s!stem are connected to the same s!stem us. At an! time instant

communication ta9es place etween the master and one of the slaves. All the slaves have tri+

state logic and hence normall! remain in high impedance state. &nl! when the slave isselected it comes to the normal logic.

ICA #?I"'

The &$ memor! is used to store permanent programs and data.

The A$ memor! is used to store temporar! programs and data.

The input device is used to enter the program, data and to operate the s!stem.

The output device is used for e7amining the results.

'ince the speed of I%& devices does not match with the speed of microprocessor, an interface

device is provided etween s!stem us and I%& devices. Generally I/ de!ices are slo"

de!ices.

A+)*,)'( %2 M"#$%&$%#'((%$ 3)('+ ((,'

1. "omputational%processing speed is high.

). Intelligence has een rought to s!stems.

2. Automation of industrial processes and office administration.3. 'ince the devices are programmale, there is fle7iilit! to alter the s!stem ! changing the software

alone.5. ess numer of components, compact in si>e and cost less. Also it is more reliale.

6. &peration and maintenance are easier.

D"()+)*,)'( %2 M"#$%&$%#'((%$ 3)('+ S(,'

1. It has limitations on the si>e of data.). The applications are limited ! the ph!sical address space.

2. The analog signals cannot e processed directl! and digiti>ing the analog signals introduces errors.

3. The speed of e7ecution is slow and so real time applications are not possile.5. $ost of the microprocessors does not support floating point operations.


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INTEL 8085 ! P"* D")$) D'(#$"&,"%*

The I:T 8085 is a 8+it microprocessor.

It operates on 8+it data and uses 16+it address to access the memor!.

ith the help of 16+it address, 8085 can access )16D 65526 D 63 memor! locations.

It is a 30+pin #I chip designed using :$&'.

It operates with a power suppl! of E5 volts and 4:#.

8085 generates the cloc9 signal internall! ! dividing the e7ternal supplied cloc9 signal !

two.


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INTEL 8085 ARCHITECTURE

The architecture of.8085 is shown in figure given elow. The internal architecture of 8085 includes

the A;, timing and control unit, instruction register and decoder, register arra!, interrupt control

and serial I%& control.

&ATI&:' =&$# /F 8085

The A; performs the arithmetic and logical operations.

The operations performed ! A; of 8085 are )++","%*7 (3,$)#,"%*7 "*#$''*,7 +'#$''*,7

-%"#)- AND7 OR7 EXCL U8IVE OR7 #%&)$'7 #%&-''*, and -'2, $";, (;"2,. The

accumulator and temporar! register are used to hold the data during an arithmetic % logical

operation. After an operation the result is stored in the accumulator and the flags are set or reset

according to the result of the operation.

=A4 4I'T

There are five flags in 8085, which are ("* 2-) '$% 2-)


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After an A; operation, if the most significant it of the result is 1, then sign flag is set. The >ero

flag is set, if the A; operation results in >ero and it is reset if the result is non+>ero. In an

arithmetic operation, when a carr! is generated ! the lower nile, the au7iliar! carr! flag is set.After an arithmetic or logical operation, if the result has an even numer of 1 Gs the parit! flag is set,

other wise it is reset.

If an arithmetic operation results in a carr!, the carr! flag is set other wise it is reset. Among thefive flags, the A" flag is used internall! for /"# arithmetic and other four flags can e used ! the

programmer to chec9 the conditions of the result of an operation.

TI$I:4 H "&:T& ;:IT

The timing and control unit s!nchroni>es all the microprocessor operations with the cloc9 andgenerates the control signals necessar! for communication etween the microprocessor and

peripherals.

I:'T;"TI&: 4I'T H #"

hen an instruction is fetched from memor! it is placed in instruction register. Then it is decodedand encoded into various machine c!cles.

4I'T AAF

Apart from Accumulator (A+register*, there are si7 general+purpose programmale registers/, ", #, , C and .

The! can e used as 8+it registers or paired to store l6+it data. The allowed pairs are /+",#+ and C+.

The temporar! registers and are intended for internal use of the processor and it cannot

e used ! the programmer.

'TA" &I:T ('*

The stac9 pointer ', holds the address of the stac9 top. The stac9 is a se@uence of A$memor! locations defined ! the programmer. The stac9 is used to save the content of

registers during the e7ecution of a program.

&4A$ "&;:T ("*The program counter ("* 9eeps trac9 of program e7ecution. To e7ecute a program the

starting address of the program is loaded in program counter. The " sends out an address to

fetch a !te of instruction from memor! and increment its content automaticall!. Cence,when a !te of instruction is fetched, the " holds the address of the ne7t !te of the

instruction or ne7t instruction.


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INSTRUCTION EXECUTION AND DATA FLO "* 8085

The program instructions are stored in memor!, which is an e7ternal device. To e7ecute a program

in 8085, the starting address of the program should e loaded in program counter. The 8085 output

the content of program counter in address us and asserts read control signal low. Also, the program

counter is incremented.

The address and the read control signal enale the memor! to output the content of memor!

location on the data us. :ow the content of data us is the opcode of an instruction. The readcontrol signal is made high ! timing and control unit after a specified time. At the rising edge of

read control signals, the opcode is latched into microprocessor internal us and placed in instruction

register.

The instruction+decoding unit, decodes the instructions and provides information to timing and

control unit to ta9e further actions.

INSTRUCTION FORMAT OF 8085

The 8085 have -3 asic instructions and )36 total instructions. The instruction set of 8085 is

defined ! the manufacturer Intel "orporation. ach instruction of 8085 has 1 !te opcode. ith 8

it inar! code, we can generate )56 different inar! codes. In this, )36 codes have een used foropcodes.

The si>e of 8085 instructions can e 1 !te, ) !tes or 2 !tes.

The 1+!te instruction has an opcode alone.

The ) !tes instruction has an opcode followed ! an eight+it address or data.

The 2 !tes instruction has an opcode followed ! 16 it address or data. hile storing the 2

!tes instruction in memor!, the se@uence of storage is, opcode first followed ! low !te ofaddress or data and then high !te of address or data.


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ADDRESSING MODES

ver! instruction of a program has to operate on a data. The method of specif!ing the data to e

operated ! the instruction is called#ddressing. The 8085 has the following 5 different t!pes of

addressing.

1. Immediate Addressing

). #irect Addressing2. egister Addressing

3. egister Indirect Addressing

5. Implied Addressing

I'+"),' A++$'(("*

In immediate addressing mode, the data is specified in the instruction itself. The data will e apart

of the program instruction. All instructions that have JIK in their mnemonics are of Immediateaddressing t!pe.

$g. $?I /, 2C + $ove the data 2Cgiven in the instruction to / register.

D"$'#, A++$'(("*

In direct addressing mode, the address of the data is specified in the instruction. The data will e inmemor!. In this addressing mode, the program instructions and data can e stored in different

memor! loc9s. This t!pe of addressing can e identified ! 16+it address present in the

instruction.

$g. #A 1050C + oad the data availale in memor! location 1050Cin accumulator.

R'"(,'$ A++$'(("*

In register addressing mode, the instruction specifies the name of the register in which the data isavailale. This t!pe of addressing can e identified ! register names (such as JAK, J/K, L * in theinstruction.

$g. $&? A, / +$ove the content of / register to A register.

R'"(,'$ I*+"$'#, A++$'(("*

In register indirect addressing mode, the instruction specifies the name of the register in which theaddress of the data is availale. Cere the data will e in memor! and the address will e in the

register pair. This t!pe of addressing can e identified ! letter J$K present in the instruction.

$g. $&? A, $ + The memor! data addressed ! C pair is moved to A register.

I&-"'+ A++$'(("*

In implied addressing mode, the instruction itself specifies the t!pe of operation and location of data

to e operated. This t!pe of instruction does not have an! address, register name, immediate data

specified along with it.

$g. "$A + "omplement the content of accumulator.


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INSTRUCTION SET

The 8085 instruction set can e classified into the following five functional headings.

G$%& I DATA TRANSFER INSTRUCTIONS:

Includes the instructions that moves ( copies* data etween registers or etween memor! locations

and registers. In all data transfer operations the content of source register is not altered. Cence the

data transfer is cop!ing operation.

7 i* $&? A,/ ii* #A 3600 iii* C# 3)00

G$%& II ARITHMETIC INSTRUCTIONS:

Includes the instructions which performs the addition, sutraction, increment or decrement

operations. The flag conditions are altered after e7ecution of an instruction in this group.

7 i* A## / ii* ';/ " iii* I: # iv* I:M C

G$%& III LOGICAL INSTRUCTIONS:The instructions which performs the logical operations li9e A:#, &, 7clusive+&, complement,

compare and rotate instructions are grouped under this heading. The flag conditions are altered aftere7ecution of an instruction in this group.

7 i* &A / ii* MA A iii* A

G$%& IV BRANCHING INSTRUCTIONS:

The instructions that are used to transfer the program control from one memor! location to anothermemor! location are grouped under this heading.

7 i* e,

machine c!cles, numer of T +state and the total numer of instructions in each t!pe are also shown

in tale in ne7t page. The instructions affecting the status flag are listed in tale followed.


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INTERRUPTS

NEED FOR INTERRUPTS

Interrupt is a signal send by an external de!ice to the processor, to the processor to perform a

particular tas% or "or%. &ainly in the microprocessor based system the interrupts are used for datatransfer bet"een the peripheral and the microprocessor.

hen a peripheral is read! for data transfer, it interrupts the processor ! sending an appropriatesignal to the interrupt pin of the processor. If the processor accepts the interrupt then the processor

suspends its current activit! and e7ecutes an interrupt service suroutine to complete the data

transfer etween the peripheral and processor. After e7ecuting the interrupt service routine theprocessor resumes its current activit!. This t!pe of data transfer scheme is called interrupt driven

data transfer scheme.

T/PES OF INTERRUPTS

The interrupts are classified into software interrupts and hardware interrupts.

The soft"are interrupts are program instructions.These instructions are inserted at desired

locations in a program. hile running a program, lf a software interrupt instruction isencountered, then the processor e7ecutes an interrupt service routine (I'*.

The hard"are interrupts are initiated by an external de!ice by placing an appropriatesignal at the interrupt pin of the processor.If the interrupt is accepted, then the processor

e7ecutes an interrupt service routine (I'*.

SOFTARE INTERRUPTS OF 8085

The software interrupts are program instructions. hen the instruction is e7ecuted, the processore7ecutes an interrupt service routine stored in the vector address of the software interrupt

instruction. The software interrupts of 8085 are 'T 0, 'T 1, 'T ), 'T 2, 'T 3, 'T 5, 'T

6 and 'T -.

The vector addresses of

software interrupts are

given in tale elow.


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The software interrupt instructions are included at the appropriate (or re@uired* place in the main

program. hen the processor encounters the software instruction, it pushes the content of "

(rogram "ounter* to stac9. Then loads the ?ector address in " and starts e7ecuting the Interrupt

'ervice outine (I'* stored in this vector address. At the end of I', a return instruction + T

will e placed. hen the T instruction is e7ecuted, the processor & the content of stac9 to ".

Cence the processor control returns to the main program after servicing the interrupt. $xecution of

I'( is referred to as ser!icing of interrupt.

All software interrupts of 8085 are vectored interrupts. The software interrupts cannot e mas9ed

and the! cannot e disaled.

T;' (%2,)$' "*,'$$&,( )$' RST07 RST17 RST


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The TA, 'T -.5, 'T 6.5 and 'T 5.5 are vectored interrupts.

The I:T is a non+vectored interrupt. Cence when a device interrupts through I:T, it has tosuppl! the address of I' after receiving interrupt ac9nowledge signal.

The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085 are

defined by INTEL.

The TA interrupt is edge and level sensitive. Cence, to initiate TA, the interrupt signal has toma9e a low to high transition and then it has to remain high until the interrupt is recogni>ed.

The 'T -.5 interrupt is edge sensitive (positive edge*. To initiate the 'T -.5, the interrupt signal

has to ma9e a low to high transition an it need not remain high until it is recogni>ed.

The 'T 6.5, 'T 5.5 and I:T are level sensitive interrupts. Cence for these interrupts the

interrupting signal should remain high, until it is recogni>ed.

$A'A/ H :&:+$A'A/ I:T;T'

The hardware vectored interrupts are classified into masable and non!masable interrupts.

TA is non+mas9ale interrupt

'T -.5, 'T 6.5 and 'T 5.5 are mas9ale interrupt.

$as9ing is preventing the interrupt from disturing the main program. hen an interrupt is mas9ed

the processor will not accept the interrupt signal. The interrupts can e mas9ed ! moving an

appropriate data (or code* to accumulator and then e7ecuting 'I$ instruction. ('I$ + 'et Interrupt$as9*. The status of mas9ale interrupts can e read into accumulator ! e7ecuting I$ instruction

(I$ + ead Interrupt $as9*.

All the hardware interrupts, e7cept TA are disaled, when the processor is resetted. The! can

also e disaled ! e7ecuting #l instruction. (#l+#isale Interrupt*.

hen an interrupt is disaled, it will not e accepted ! the processor. (i.e., I:T, 'T 5.5,

'T 6.5 and 'T -.5 are disaled ! #I instruction and upon hardware reset*.

To enale (to allow* the disaled interrupt, the processor has to e7ecute l instruction (l+

nale Interrupt*.


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INTERRUPT DRIVEN DATA TRANSFER SCHEME

The interrupt driven data transfer scheme is the est method of data transfer for effectivel! utili>ing

the processor time. In this scheme, the processor first initiates the I%& device for data transfer. After

initiating the device, the processor will continue the e7ecution of instructions in the program. Alsoat the end of an instruction the processor will chec9 for a valid interrupt signal. If there is no

interrupt then the processor will continue the e7ecution.

hen the I%& device is read!, it will interrupt the processor. &n receiving an interrupt signal, the

processor will complete the current instruction e7ecution and saves the processor status in stac9.

Then the processor calls an interrupt service routine (I'* to service the interrupted device. At the

end of I' the processor status is retrieved from stac9 and the processor starts e7ecuting its main

program. The se@uence of operations for an interrupt driven data transfer scheme is shown in figure

elow.


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TIMING DIAGRAM for various machine cycles

The machine c!cles are the asic operations performed ! the processor, while instructionsare e7ecuted. The time ta9en for performing each machine c!cle is e7pressed in terms of T+

states.

&ne T+state is the time period of one cloc9 c!cle of the microprocessor.

The various machine c!cles are

1. &pcode fetch LLLLL.. + 3 % 6 T

). $emor! ead LLLLL. + 2 T

2. $emor! rite LLLLL. + 2 T3. I%& ead LLLLLLL.. + 2 T

5. I%& rite LLLLLLL. + 2 T

6. Interrupt Ac9nowledge LL + 6 % 1) T-. /us Idle LLLLLLLL + ) % 2 T


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DELA/ ROUTINE

#ela! routines are suroutines used for maintaining the timings of various operations in

microprocessor.

In control applications, certain e@uipment needs to e )/** after a specified time dela!. In some

applications, a certain operation has to e repeated after a specified time interval. In such cases,

simple time dela! routines can e used to maintain the timings of the operations.

#AF &;TI: &"''

# delay routine is generally "ritten as a subroutine +It need not be a subroutine al"ays. It can be

e!en a part of main program. In delay routine a count +number is loaded in a register of

microprocessor. Then it is decremented by one and the -ero flag is chec%ed to !erify "hether the

content of register is -ero or not. This process is continued until the content of register is -ero.hen it is -ero, the time delay is o!er and the control is transferred to main program to carry out

the desired operation.

The dela! time is given ! the total time ta9en to e7ecute the dela! routine. It can e computed !multipl!ing the total numer of T+states re@uired to e7ecute suroutine and the time for one T+state

of the processor. The total numer of T+states can e computed from the 9nowledge of T+statesre@uired for each instruction. The time for one T+state of the processor is given ! the inverse of the

internal cloc9 fre@uenc! of the processor.

=or e7ample, if the 8085 microprocessor has 5 $C> @uart> cr!stal then,

The internal cloc9 fre@uenc! D 5 % ) D ).5 $C>

Time for one T+stateD 1 % ).5 7 106D 0.3Nsec

=or small time dela!s (O 0.5 msec* an 8+ it register can e used.

=or large time dela!s (O 0.5 'ec* l6+it register should e used.

=or ver! large time dela!s (P 0.5 sec*, a dela! routine can e repeatedl! called in the main

program.

The disadvantage in dela! routines is that the processor time is wasted. An alternate solution is touse dedicated timer li9e 8)52%8)53 to produce time dela!s or to maintain timings of various

operations.

Two e7ample dela! routines are presented in this section with details of timing calculations.


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EXAMPLE DELA/ ROUTINE +1

rite a dela! routine to produce a time dela! of 0.5 msec in 8085 processor+ased s!stem whosecloc9 source is 6 $C> @uart> cr!stal.

S%-,"%*

The dela! re@uired is 0.5 msec, hence an 8+it register of8085 can e used to store a "ount value

and then decrement to >ero. The dela! routine is written as a suroutine as shown elow.

D'-) $%,"*'

$?I #,) Q oad the count value,)in #+register.

oop0 #" # Q #ecrement the count.ero go to

T Q eturn to main program.

The following tale shows the T+state re@uired for e7ecution of the instructions in the suroutine.

Instruction

T1'tate re2uired for

execution of an

instruction

)umber of times the

instruction is executedTotal T1'tates

"A addr16$?I #, :

#" #


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PROGRAMMING EXAMPLES:

1. $",' )* ALP ("* 8085 ,% -,"&- ,% 83", *3'$( 3 $'&'),'+ )++","%*.

$?I A, && Q#ccumulator contents are cleared

$?I ", && Q C (egister contents are cleared

$?I /, data34 QI perand is loaded into B (egister$?I #, data35 QII perand is loaded into 6 (egister

oop A## / S


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3. $",' )* ALP ("* 8085 ,% ')-),' ,;' '@&$'(("%* CAB

et JAK e #ataU1 and J/K e #ataU)

$?I /, #ataU1 Q #ata 34 is stored in register B

$&? ", / Q Copy of 6ata 34 is made in register C

$?I #, #ataU) Q #ata 35 is stored in register 6$&? ,# Q Copy of 6ata 35 is made in register $

MA A Q #ccumulator content is cleared

Again A## / V#" " #5is calculated by repeated #ddition


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INTERFACING EXAMPLES:

D$) ,;' #"$#", +")$) %2 )* 8085 ((,'7 ;)"* ) 4 KB EPROM )*+ ,% 8 KB RAM IC(.

T;' (,)$,"* )++$'(( %2 ,;' EPROM "( 0000H )*+ ,;), %2 RAM "( 8000H. T;' )++$'(( %2 ,;'

+'#%+'$ #"$#",( (;%-+ 3' #-')$- (;%*.

'nswer (&$ + 3 / (Address lines re@uired is 1) A0to A11*

A$+I + 8 / (Address lines re@uired is 12 A0to A1) *

A$+II + 8 / (Address lines re@uired is 12 A0to A1)*

$apping of Addresses to $emor! Ics

ICsBinary #ddress 8ex

#ddres

sA15 A13 A12 A1) A11 A10 A A8 A- A6 A5 A3 A2 A) A1 A0

&$

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P)$, A:

1. S,),' ,;' 2*#,"%* %2 HOLD )*+ HLDA &"*( "* 8085.

The C and C#A pins in 8085 are used in interfacing the 8)5-+#$A controller I"

with the processor.

A signal is sent ! 8)5- to C pin in , to re@uest the to stop its current process

and allocate the uses for #$A data transfer. ac9nowledges the re@uest for #$A data transfer ! 8)5-, ! sending a signal in C#Ato 8)5-.

. D"(,"*"(; IO )&&'+ IO )*+ '%$ )&&'+ IO.

$apping is the process ! which the addresses are allocated to the I%& devices.

The two 9inds of mapping are

a* $emor! mapped I%&

* I%& mapped I%&

S.N% &emory mapped I/ IO )&&'+ IO

14; bitaddress is given to each I%&

device

< bitaddress is given to each I%&

device

)

achI/ de!ice is treated li%e a

memory locationand the! areaccessed using instructions related to

memor! operations.

All I%& devices are accessed using

only t"o instructionsvi>., I: and&;T.

2#ata can e transferred bet"een I/

de!ices and all registersin .

#ata can e transferred only bet"een

I/ de!ices and accumulatorin .

3 This scheme is used in s!stem, wherememory re2uirement is small.

This scheme is used in s!stem, wherecomplete memory capacity is

re2uired.

5

&nl!&emory (ead = rite machine

cycles are in!ol!edduring data

transfer with I%& devices.

&nl!I/ (ead = rite machine

cycles are in!ol!edduring data

transfer with I%& devices.

6arge numer of I%& devices can econnected in this scheme.

&nl! ma7imum of )56(D)8* I%&

devices can e connected in thisscheme.

. E@&-)"* ,;' '@'#,"%* %2 ,;' "*(,$#,"%* CMA "*(,$#,"%* "* 8085.

"$A instruction is used to perform 1Ks complement of the contents of Accumulator in 8085.


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4. ;), "( ,;' 2*#,"%* &'$2%$'+ 3 SIM )*+ RIM "*(,$#,"%*.

'I& Instruction0

The 'I$ instruction is used to mas9 the hardware interrupts 'T-.5, 'T6.5 and 'T5.5. Itis also used to send data through ' line.

(I& Instruction0

The I$ instruction is used to chec9 whether an interrupt ('T-.5, 'T6.5 and 'T5.5* ismas9ed or not. It is also used to read data from 'I# line.

5. ;), "-- 3' ,;' %,#%'7 "* '@'#,"%* %2 "*(,$#,"%*( LXI H74600H )*+ LHLD 4600H

hen MI C,3600 is e7ecuted, the numer 3600 will e loaded to C register pair.

hen C# 3600 is e7ecuted, the contents of memor! location 3600Cwill e transferred to

C register pair.

6. E@&-)"* ,;' #%*#'&, %2 +'-,"&-'@"* AD0-"*'( "* 8085

#emultiple7ing is the process of separating the low !te address A0+- and 8+it data #0+-from A#0+-lines of 8085, using a latch and Address latch enale (A* signal.

#0+-

A0+-

hen low !te address (A0+-* comes out of A#0+- lines, the processor asserts CI4C in the

A pin, enaling the latch to separate the low !te address.

P AD0-78085

ALE

74LS373

Latch


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. C%&)$' S(,' 3( )*+ CPU 3(.

/us is a set of conducting wires in a microprocessor ased s!stem, which helps to carr!various information li9e #ATA, A##'' and other "&:T&

/us

Internal 7ternal

"; us '!stem /us

'!stem /us "; /us

It will note

directl! connected

to ";

It will e directl!

connected to ";

There will e

separatedata,address H control

uses

The data and

address ma! emultiplexed

8. S,),' ,;' ("*"2"#)*#' %2 X1 )*+ X&"*( %2 8085.

The cloc9 signal is supplied to the microprocessor 8085 ! connecting @uart> cr!stalthrough the pins M1 and M).

Wuart>

"r!stal

9. ;), "( P$%#'((%$


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10. L"(, ,;' )$"%( )++$'(("* %+'( "* 8085 ",; ,% '@)&-'( "* ')#;.

Addressing is the method of specif!ing the location of data in an instruction.

The different t!pes of addressing modes in 8085 are

a 6irect0

The data is stored in memor! and 16 it address of data in memor! location is specifiedin the instruction.

g. #A 3500, C# 3)00

b Immediate0

The re@uired data for processing is given ne7t to the &pcode, in the instruction itself.

g. $?I A, 55 "I 63, A#I 0A

c (egister0

The data is placed in a register and the register name is given in the instruction to access

the data.

g. $&? A,/ A## /, ';/ "

d (egister Indirect0

The data is stored in memor! and the 16+it address of the data location in memor! isplaced in a register pair. This register pair holding the 16+it address is given in the

instruction to access the data.

g. MI, C 3)50 $&? A, $

e Implied0

The data location H the operation to e performed is given in the instruction itself.g. "$A, A, M"C4

11. D'2"*' (,)# )*+ (,)# &%"*,'$.

'tac%0A small portion of the A$ memor! is declared as stac9 and it is used for temporar!

storage of the register contents, using instructions li9e ;'C and &.

The contents are stored and retrieved in I=& (ast In =irst &ut* form.

'tac% Pointer0It is a 16+it memor! pointing register, having the last address of the stac9 in A$.


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1. C%&)$' CALL )*+ JMP "*(,$#,"%*(.

C# Instruction0

7ecution of a "A instruction will transfer the program control from e7isting program toanother program. ie., 'u program specified ! the 16+it address in "A instruction will

e e7ecuted. The called program should have T return instruction as its last instruction.

Time ta9en for its e7ecution is % 18 T

$ain XXXXXXXXX addr16 XXXXXXXXX XXXXXXXXX XXXXXXXXX

XXXXXXXXX XXXXXXXXX

XXXXXXXXX

"A addr16 XXXXXXXXX XXXXXXXXX XXXXXXXXX

XXXXXXXXX T

XXXXXXXXX

)*+ Instruction

7ecution of a


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14. E@&-)"* ,;' 2*#,"%* %2 IN )*+ OUT "*(,$#,"%*(.

7ecution of an I: instruction will transfer one byte of data from an Input de!ice to#ccumulatorof microprocessor.

7ecution of an &;T instruction will transfer one byte of data from #ccumulator ofmicroprocessor to an utput de!ice.

15. $",' )* ALP 2%$ ,"' +'-) ("* ) $'"(,'$ &)"$ ))"-)3-' "* 8085.

$ain XXXXXXXXX 6elay MI #, data16

XXXXXXXXX loop :&

XXXXXXXXX :&:&

"A6elay #"M #

XXXXXXXXX 5?T x data4;(stored in # register pair*

16.$",' )* )(('3- -)*)' &$%$) ,% (,%$' ,;' #%*,'*,( %2 ,;' 2-) $'"(,'$ "*

'%$ -%#),"%* 000H.

;'C ' + 'tores the contents of #ccumulator = *lag register in 'tac%& # + (estores the stored contents of stac% to 6$ register pair

$&? A, + &o!e the contents of $ register to #ccumulator

'TA )000C + Contents of #ccumulator is no" stored to memory location 57778

1. E@&-)"* ,;' I*(,$#,"%* 2%$), %2 8085.

The 8085 have -3 asic instructions. The

si>e of 8085 instructions can e 1 !te, )

!tes or 2!tes.

1 /!te instruction has &pcode alone.) /!tes instructions have 1 !te

&pcode followed ! 8 it data.

2 /!tes instruction have 1 !te &pcode followed ! 16 it data.


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18. D$) )*+ -)3'- ,;' 2-)( "* 2-) $'"(,'$ %2 8085.

52483839 Microprocessor 8085 Notes

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