1 Tx 0/10/1MR3:0TCEMR2MAT1.3 Tx 0 IR TxTC TxIR 0 MR0 0 4 CR0 0 1 MR1 0 5 CR1 1 2 MR2 0 6 CR2 2 3 MR3 0 7 CR3 0 TxPC TxTC TxPR TxTCR TxIR Fpclk —— MCR 0 PR=2, MRx=6, PCLK PCLK/3 VIC TCR ——0 —— PWM PWMIR PWMIR 0 PWMMR0 0 4:7 PWMLER PWMLER PWMTC PWM PWMPCR PWMMCR PWMMRx PWM PWM —— PWMLER 0 PWM0 A/DV3AVSSA 1: 0: A/D PCLK / ( CLKDIV + 1) BURSTSEL1 A/D ADCR —— 27 26:24 23:22 21 19:17 16 15:8 7:0 EDGE START TEST1:0 PDN CLKS BURST CLKDIV SEL A/D ADCR —— 27 26:24 23:22 21 19:17 16 15:8 7:0 EDGE START TEST1:0 PDN CLKS BURST CLKDIV SEL A/D ADCR —— 27 26:24 23:22 21 19:17 16 15:8 7:0 EDGE START TEST1:0 PDN CLKS BURST CLKDIV SEL Vin = ×(VSSA / 0x3FF) A/D —— ADDR 31 30 29:27 26:24 23:16 15:6 5:0 DONE OVERUN 0 CHN 0 V/VddA 0 A/D —— ADDR 31 30 29:27 26:24 23:16 15:6 5:0 DONE OVERUN 0 CHN 0 V/VddA 0 #define ADBIT 10 // BURST #define ADBIT2 (10 - ADBIT) RTC —— PREINT 13 1 CTCRST 3 : 2 SEC 6 DOW 3 MONTH 4 DOW 3 MONTH 4 —— ILR CIIR AMR —— ILR CIIR AMR —— ILR CIIR AMR CIIR 0 IMSEC RTC RTC RTC RTC WDTWDTWDT WDFEED WDTC WDTV 32bit —— WDMOD tpclk×0xFF×4 tpclk×0xFFFFFFFF×4