5. Delta-Sigma Modulators for ADCpserra/uab/ihsd/ihsd-5-dsm.pdf · Delta-Sigma Modulators for ADC Integrated Heterogeneous Systems Design F. Serra Graells Basics Architectures SC

5. Delta-Sigma Modulators for ADC

Integrated Heterogeneous Systems Design F. Serra Graells

Basics Architectures SC Modeling Assisted Low-Power 1/46

5. Delta-Sigma Modulatorsfor ADC

Francesc Serra Graells

[email protected] de Microelectrònica i Sistemes Electrònics

Universitat Autònoma de Barcelona

[email protected] Circuits and Systems

IMB-CNM(CSIC)




Oversampling and Noise Shaping Principles1

Architecture Selection Based on Quantization Error2

Switched-Capacitor CMOS Implementations3

Modeling Circuit Second Order Effects4

Digitally Assisted Techniques5

Low-Power Circuit Topologies6













Oversampling

Constant (white)error spectrum profile signal

amplitude

erroramplitude

e.g. 5-level quantization

2-times sampling rate

erroramplitude

signalamplitude




Oversampling

Constant (white)error spectrum profile

Power spectral density (PSD)

Spread acrossspectrum (fs/2)

Oversampling ratio

Lower in-band noise

Higher clock frequenciesDynamicRange Power

dependent fromsampling frequency

Same power(total area) Nyquist

rate

Oversamplingrate




Basic single-loop Delta-Sigma modulator (DSM) for discrete time (DT) ADCs:

S/H

shaping filter(e.g. integrator)

quantizer(e.g. 1-bit) all-pass

high-passshaping

log(frequency)

log(power)

signal

out-bandnoise shaping

20dB/dec

Quantization Noise Shaping

signal

quantizationnoise

output

Equivalent linear model:




N-order B-bit single loop architecture:

S/H

directimprovement

log(frequency)

log(power)

signal

20N dB/dec6N dB/oct

multi-bit (B)quantization

Ideal dynamic range:

(N+0.5)-bit/oct(OSR)

Multi-bit quantization:

Internal full-scale reduction

Resolution added to overall DR

Feedback DAC not intrinsically linear

High-order filtering:

Stability issues

Sharper noise shaping

oversamplingonly

shapingorder

Quantization Noise Shaping













High-order feedback or feedforward DSM architectures:

S/H

Unstability issues

Single-Loop vs MASH

DAC

S/H

DAC

DAC

Mismatchingsensitivity

Canc

ellat

ion

Filte

r




High-order feedback or feedforward DSM architectures:

S/H

Unstability issues

Single-Loop vs MASH

DAC

S/H

DAC

Mismatchingsensitivity

Canc

ellat

ion

Filte

r

More suitablefor DSM DACs!

DAC




Simplest DSM architecture: first-order

S/H Large OSR needed

Tonal spectrum caused bysignal to quantizationnoise correlation!

log(frequency)

log(power)

signalin-band

harmonics

Order Selection

Intrinsically stable

DAC




Next architecture step: second-order

S/H

Order Selection

Intrinsically stablefor limited input range

DAC Moderate OSRrequirements

log(frequency)

log(power)

signal

40 dB/dec12 dB/octsecond-order

high-pass

Signal to quantizationnoise uncorrelation(continuous spectrum)




Higher-order general architecture:

Sharper noise shaping

Possibility of loopinstability for N>2

S/H

gaincoefficients

Coefficientsoptimizationagainstmismatching

Delta-Sigma Noise Shaping

DAC

SNDRmaps

saferegion




Feedfoward cancellation: Internal full scalelow occupancyAdditional adder stagein front of quantizer

S/H

Commonly Used Architectures

Resonator attenuation:

Extra noise shapingat band edgeZero sensitivity tocoefficient matching

S/H

log(frequency)

log(power)

DAC

DAC

zero













Shaping filter basic building block:

SC Integrator

clock S I

integrationfunction

gainfunction

SC-OpAmp compact implementation:

non-overlappingphases

for initializationpurposes

single-endedcircuit version

Analog circuit realization (ADC)

Digital circuit realization (DAC)




SC Integrator

clock S I





SC Integrator

clock S I





SC Integrator





SC Noise Shaper

S/H

differentialsignal domain

Fully-differential 2nd-ordersingle-bit DSM example:

feedforwardsignal cancellation





SC Noise Shaper

input samplerreused for DAC

feedback

commonmode

S/H





SC Noise Shaper

integratorinitialization

S/H





SC Noise Shaper

passiveadder

S/H

-6dB attenuation negligiblethanks to 1-bit quantization













Switch Thermal Noise

switchon-resistanceoversampling

extension

Added to signal at input sampler:




Switch Thermal Noise Dynamicrange

Power& area

Large capacitor area and low input impedance values!

switchon-resistance

Fully differentialcontributions:

oversamplingextension

Added to signal at input sampler:




Clock Jitter

Critical at input sampler due to itscontinuous (CT) to discrete time (DT) conversion:

jitterprobability estimated power

under harmonic stimulus:

jittererror

S Halreadyin DT!

Dynamicrange

Externalreferences




OpAmp Finite Gain

SC integrator transfer function whenOpAmp open loop gain is limited:

equivalent single endedhalf circuit

more relevant infirst stages




OpAmp Finite Gain


integration leakage gain mismatch




OpAmp Finite Gain


Signal dependent gaingenerates output distortion

integration leakage gain mismatch




OpAmp Slew-Rate and GBW

Qualitative case studies:

OpAmp worksas a charge pump

during integration phase

currentlimitation!






frequencytransferfunction!






mixedlimitation!

Non-linear errors = signal distortion




Feedback DAC Non-Linearity

Only for multi-bit DSM architectures:

INL/DNLdirectly added

to signal input!

quantizernon-linearity

shaped as error

How to get rid of feedback flash DAC non-linearity effects?













Feedback DAC Mismatching

single-endedversion

Single-stage multi-bit SC flash architecture example: reset





Single-stage multi-bit SC flash architecture example:

hardwiredbinary

weighted

Simple digital control






Pelgrom's Law

technologymismatching

hardwiredbinary

weighted

Simple digital control

Distortion caused by static mismatching

in-bandharmonics






Pelgrom's Law

technologymismatching

thermometricdynamicselection

Low in-band noise by thermometric scrambling

Complex digital control

in-bandwhite noise

binto

therm

randomizer





Single-stage multi-bit SC flash architecture example:technology

mismatchingdynamicelement

matching (DEM)

Mismatch shaping by equalizing long-term element selection

Complex digital control

binto

thermDWA

data-wieghtedaveraging

20dB/decfirst-ordershaping

barrelshifting

07

3425

16



41/46Basics Architectures SC Modeling Assisted Low-Power










Switched OpAmp (SOA)

Distortion caused by signal-dependent switch on-resistance:

INL/DNLdirectly added

to signal input!

quantizernon-linearity

shaped as error

How to make on-resistance independent from signal for these particular switches?





Moving output switches into OpAmp blocks:

Each integrator stage operatesin alternative phases

clock S I

single-endedcircuit version

Constant on-resistancefor all switchesPower savings due to50% OpAmp duty cycle





Moving output switches into OpAmp blocks:

Each integrator stage operatesin alternative phases

Constant on-resistancefor all switchesPower savings due to50% OpAmp duty cycle

M1

M6

M2

M5

M8

M4 M3

M7

Example: single-ended single-stage folded OpAmp




OpAmp Dynamic Biasing

Discrete time dynamic biasing:

M1

M6

M2

M5

M10M9

M8

M4 M3

M7

time

clock S I




OpAmp Dynamic Biasing

Discrete time dynamic biasing:

M1

M6

M2

M5

M10M9

M8

M4 M3

M7

time

OpAmp fast on/offrecovery time required

Static power savings

Biasing peak value istechnology dependent

Synchronous Class-ABoperation

Ripple induced in thepower rails (digital-like)

5. Delta-Sigma Modulators for ADCpserra/uab/ihsd/ihsd-5-dsm.pdf · Delta-Sigma Modulators for ADC Integrated Heterogeneous Systems Design F. Serra Graells Basics Architectures SC

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