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2716 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012

A Novel Single-Phase Five-Level Inverter WithCoupled Inductors

Zixin Li, Member, IEEE, Ping Wang, Yaohua Li, and Fanqiang Gao, Member, IEEE

Abstract—In this paper, a novel single-phase five-level inverteris proposed using coupled inductors. This inverter can output five-level voltage with only one dc source. No split of the dc voltagecapacitor is needed, totally avoiding the voltage balancing prob-lem in conventional multilevel inverters. The level of the outputvoltage is only half of the dc-link voltage in all conditions, lead-ing to much reduced dv/dt. This inverter is based on the widelyused three-arm power module and the voltage stresses on all thepower switches are the same, making it very easy to construct.Operation mechanism of this inverter is analyzed and the possi-ble switching patterns are investigated. Based on these analyses, anovel optimized modulation scheme is presented. With this mod-ulation method, no dc components exist in the inductor currents,which is very helpful for minimization of the inductors. Simulationand experimental results show the validity of the proposed invertertogether with the optimized modulation scheme.

Index Terms—Multilevel converters, power converters, pulsewidth modulation, single-phase.

I. INTRODUCTION

S INCE their introduction, multilevel inverters have beenreceiving much attention and as a result many different

topologies have been proposed. The academic papers and the-ses focusing on multilevel inverter topologies are almost in-numerable. These topologies can be classified according tomany criteria. This paper will focus on single-phase multilevelinverters.

For single-phase multilevel inverters, the most commontopologies are the cascaded, diode-clamped, and capacitor-clamped types [1]–[3]. There exist many other topologies[4]–[26]. In general, multilevel inverter topologies can be clas-sified into two types: Type I and Type II. Type I uses multipledc voltage sources and Type II uses multiple (split or clamping)dc voltage capacitors. Type I includes the traditional cascadedtopologies [1]–[3], those presented in [4]–[8] and so forth. TypeII includes the conventional diode-clamped, capacitor-clampedinverters, the topologies proposed in [9]–[26]. In terms of single-phase multilevel inverters, the disadvantages of the two typesare apparent. Type I suffers from the availability of the multipledc voltage sources. In practice, bulky transformers either of low

Manuscript received August 9, 2011; revised October 1, 2011; acceptedNovember 13, 2011. Date of current version March 16, 2012. Recommendedfor publication by Associate Editor B. Wu.

The authors are with the Institute of Electrical Engineering, ChineseAcademy of Sciences, 100190 Beijing, China (e-mail: [email protected];[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2011.2176753

Fig. 1. Proposed single-phase five-level inverter.

or medium frequency are usually necessary if a Type I inverteris adopted. This is a great challenge to when it comes to vol-ume, weight, and cost minimization. The problem with TypeII is mainly the balancing of the dc capacitor voltages, thoughsome topologies can achieve self-balancing with certain controlalgorithms.

A multilevel inverter with only one dc source and no split ca-pacitors may be the most desirable topology but unfortunatelythis type of inverter has yet to be discovered. Recently, multilevelinverters with coupled inductors have drawn some researchers’interest and a half-bridge three-level inverter has been proposedusing two power switches, two diodes, and two coupled induc-tors [27]–[30]. Whereas, as for single-phase five-level cases, twosuch half-bridges, i.e., six power devices (four power switches,two diodes) and four (two pairs of) coupled inductors will beneeded [28], [29]. What is more, dc component exists in theinductor current in these of inverters, which is harmful to thefull use of the magnetic cores. More recently, [31] presenteda single-phase inverter called a five-level-active-neutral-point-clamped with coupled inductor (5L-ANPC-CI). The 5L-ANPL-CI inverter uses eight power switches, and split of the dc-linkcapacitor is needed. Thus, the risk of unbalanced capacitor volt-age exists if the inverter is not properly modulated.

This paper presents a novel single-phase five-level inverterusing coupled inductors and the common three-arm power mod-ule (see Fig. 1). With the proposed inverter, only one dc voltagesource is needed and split of the dc voltage capacitor is alsoavoided, which eliminates the problem of dc capacitor volt-age balancing with the conventional topologies. Meanwhile, sixpower switches with the same voltage stress and only one set ofcoupled inductors are adopted. Also, less inductor is needed inthe inverter proposed in this paper compared with the topology

0885-8993/$26.00 © 2011 IEEE

LI et al.: NOVEL SINGLE-PHASE FIVE-LEVEL INVERTER WITH COUPLED INDUCTORS 2717

in [28] and [29]. In addition, an optimized modulation scheme ofthis inverter is also presented. With this modulation method, nodc component exists in the inductor currents under all load con-ditions, which will benefit the full use of the magnetic cores andminimization of the inductors. Theoretical analyses, numericalsimulation, and experimental results are presented to show thevalidity of the proposed inverter with the optimized modulationmethod.

II. PROPOSED SINGLE-PHASE FIVE-LEVEL INVERTER

Fig. 1 shows the circuit of the proposed single-phase five-level inverter. In Fig. 1, 2E is the dc-link voltage and L1 andL2 are the two coupled inductors. The mutual inductance of thetwo inductors is M and the output terminals of this inverter are1 (the same point as the output of arm a) and 2. Obviously, thistopology is very simple and can be constructed simply byadding two coupled inductors to a conventional three-arm in-verter bridge.

A. Role of the Coupled Inductors

It is, in fact, the adoption of the coupled inductors that makesit possible to output five-level voltage with only one dc voltagesource. So the role of the coupled inductors will be analyzed first.Suppose that the two coupled inductors are with the same num-ber of turns or obtained by a center-tapped inductor. The leakageinductances of the two inductors are Lσ1 and Lσ2 , respectively.Assuming that Lσ1 = Lσ2 = Lσ , the voltage equations of thecoupled inductors can be expressed as follows:

(M + Lσ )dib/dt − Mdicdt

= ubn − u2n (1)

(M + Lσ )dic/dt − Mdibdt

= ucn − u2n . (2)

Meanwhile, according to Kirchhoff’s current law, one canobtain

ib + ic + iL = 0. (3)

From (1) to (3), the following equation can be derived:

u2n =(ubn + ucn + LσdiL/dt)

2. (4)

Generally, the leakage inductance can be designed to be verysmall and its influence can be ignored in most cases. Therefore,(4) can be rewritten as

u2n =(ubn + ucn )

2. (5)

This result is interesting and shows that the coupled induc-tors will perform as an adder of the two input voltage at thenon-common-connected terminals with the common-connectedterminal as the output. Actually, without the help of the cou-pled inductors, the proposed inverter will not be able to outputfive-level voltage.

TABLE ISWITCHING STATES AND OUTPUT VOLTAGE OF THE PROPOSED INVERTER

B. Switching States for Five-Level Output Voltage

From Fig. 1 and (5), the output voltage of the proposed in-verter can be expressed as

u12 = u1n − u2n =u1n − (ubn + ucn )

2. (6)

In the following discussion, the power switches in one arm areassumed to switch complementarily. For instance, S2 must beturned OFF if S1 is turned ON and vice versa. So the followingdiscussion will only focus on the switching states of S1 , S3 , andS5 . For convenience of analysis, the number “1” will be usedto denote the ON state of one switch and “0” will be used todenote the OFF state.

In fact, u1n , ubn , and ucn all can generate two-level voltage(+E and −E). According to (6), the voltage levels of u12 canbe summarized in Table I.

Obviously, the proposed inverter can generate five voltagelevels at its output terminals. From Table I, it should be pointedout that the switching state of S1 must be 1 if u12 ≥ 0 and theswitching state of S1 must be 0 if u12 ≤ 0. This means S1 andS2 will switch at the fundamental frequency of the referencesignal. So, the switching losses of S1 and S2 will be very lowin the proposed inverter.

III. PROPOSED MODULATION METHOD

Although the proposed inverter can output five-level voltage,the modulation method must be analyzed in detail for safe op-eration. This section will focus on the pulse-width modulation(PWM) method for this inverter.

From the above analysis, the switching state of S1 is decidedby the sign of u12ref (the reference of u12): S1 is 1 if u12ref ≥0 and S1 is 0 if u12ref ≤ 0, which is very easy to implement.However, the switching states of S3 and S5 cannot be selectedwithout careful study. To decide the switching states of (S3 , S5),the following four cases will be discussed:

Case I (+E < u12ref < + 2E): In this case, the voltage of u12should alternate between +2E and +E. According to Table I,the switching states of (S3 , S5) within every switching periodTs can be (0, 0)↔(0, 1) (defined as SS1 , the note “x↔y” meansalternating between x and y) or (0, 0)↔(1, 0) (defined as SS2).

2718 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012

TABLE IISWITCHING STATES SUITABLE FOR (S3 , S5 )

Case II (0 ≤ u12ref < +E): In this occasion, the voltage ofu12 should alternate between +E and 0. Based on Table I, theswitching states of (S3 , S5) within every Ts can be (0, 1)↔(1,1) (defined as SS3) or (1, 0)↔(1, 1) (defined as SS4).

Case III (−E < u12ref ≤ 0): In this case, the voltage of u12should alternate between +0 and −E. According to Table I, theswitching states of (S3 , S5) within every Ts can be (0, 0)↔(0,1) (which is already defined as SS1 in Case I) or (0, 0)↔(1, 0)(which is already defined as SS2 in Case I).

Case IV (−2E < u12ref <− E): In this occasion, the voltageof u12 should alternate between−E and−2E. Based on Table I,the switching states of (S3 , S5) within every Ts can be (0, 1)↔(1,1) (which is already defined as SS3 in Case II) or (1, 0)↔(1, 1)(which is already defined as SS4 in Case I).

From the above analysis, one can conclude that only fourtypes of switching states within every switching period Ts canbe selected for (S3 , S5), i.e., SS1 , SS2 , SS3 , and SS4 , which arelisted in Table II. Meanwhile, if the reference voltage u12ref isgiven within certain Ts , there are always two possible choices,i.e., SS1 or SS2 for Case I and Case III and SS3 or SS4 for Case IIand Case IV.

For further discussion, the dwelling time for the switch thatswitches within every Ts is defined as

Tdwell =(|u12ref | − K · E) · Ts

E(7)

where the integer K is calculated by

K = floor

(|u12ref |

E

). (8)

The function floor(x) rounds x to the nearest integer less thanx. Obviously, the dwelling time in (7) can be generated usingthe conventional triangle wave which is shown in Fig. 2. Forconvenience of understanding, the green parts in Fig. 3 illus-trate the dwelling time within every Ts . Actually, the proposedinverter can be modulated in such a way that only one of S3 andS5 carries out the dwelling time while the other one is alwaysON or OFF within one Ts . Taking Case I as an example, if SS1is selected, S5 will switch and carry out the dwelling time whileS3 is always OFF within one Ts ; if SS2 is selected, S3 willswitch and carry out the dwelling time while S5 is always OFFwithin one Ts .

As there are always two choices for selecting the switchingstates of (S3 , S5), a great many switching patterns can be found

Fig. 2. Generation of the dwelling time defined in (7).

within one fundamental period. Fig. 3 just shows six of the pos-sible switching patterns for (S3 , S5), i.e., SP1–SP6. All of theseswitching patterns can generate the five-level output voltage u12as shown in Fig. 3. However, as the coupled inductors are con-nected between arms b and c, the voltage ubc may contain dc orfundamental components in case of improper modulation. If dccomponent exists in ubc , the currents in the coupled inductorsmay increase to quite a large value, which is very dangerousto the normal operation of the inverter. In order to operate theinverter safely and minimize the size and weight of the coupledinductors, the following rules for modulation should be satisfied.

1) The voltage ubc should not contain any dc component.Otherwise, the inverter may have the risk of overcurrent.

2) The currents in the coupled inductors should not containany fundamental or loworder harmonic component underno-load condition. Otherwise, the magnetization currentto the core of the inductors together with the inverter losseswill be increased, leading to decreased efficiency of theinverter and increased flux density of the inductor core.

Considering the above rules, not all of the possible switchingpatterns for (S3 , S5) can be selected. Indeed, the two possiblechoices (SS1 or SS2 for Case I and Case III and SS3 or SS4 forCase II and Case IV) for (S3 , S5) within one Ts have the samerole on the output voltage, but the voltage ubc they generatediffers a lot. For example, it is seen from Table II that bothSS1 and SS2 can generate an output voltage alternating between+2E and +E (0 and −E) if the switching state of S1 is 1 (0).Namely, SS1 and SS2 have the same role on the output voltageof this inverter. Whereas, if SS1 is adopted, the voltage on thecoupled inductors ubc will be 0 or −2E while ubc will be 0 or+2E if SS2 is adopted. If SS1 makes the current in the coupledinductors increase, SS2 will make that current decrease and viceversa. This is also true for SS3 and SS4 . Therefore, SS1–SS4cannot be selected in consecutive switching periods withoutchange. Otherwise, fundamental or low-order harmonics willappear in the inductor currents under no load and it will alsoincrease the inductor currents when the inverter is loaded.

Based on these analyses, the proper modulation or switchingstrategy for the proposed inverter can be obtained. As SS1 andSS3 generate 0 and −2E while SS2 and SS4 generate 0 and+2E to ubc , the four switching states must be selected in sucha manner that ubc will change its sign in every Ts . In this way,only ripple component other than dc or fundamental component

LI et al.: NOVEL SINGLE-PHASE FIVE-LEVEL INVERTER WITH COUPLED INDUCTORS 2719

Fig. 3. Dwelling time (green part) within every Ts and the some of the possible switching patterns for S3 and S5 (SP1–SP6).

TABLE IIIRULES FOR SELECTING SWITCHING STATES OF (S3 , S5 )

will appear in the inductor currents under no load, and it willnot introduce extra magnetization currents to the inductor core.

To summarize, the rules for selecting the optimum switch-ing states that can minimize the inductor currents are listed inTable III. For instance, if −E < u12ref ≤ 0 or the Case III inthe (k−1)th Ts and the switching state of (S3 , S5) is SS1 in the(k−1)th Ts , the switching state of (S3 , S5) will be SS2 , SS4 ,SS2 , or SS4 in the kth Ts if it is Case I, Case II, Case III, orCase IV in the kth Ts , respectively. According to the rules listedin Table III, the six switching patterns shown in Fig. 3 are notall suitable. For example, SP1–SP4 do not meet the rules listedin Table III while SP5 and SP6 are suitable.

IV. DESIGN OF THE COUPLED INDUCTORS

In order to design the coupled inductors, the relationshipbetween the currents of the coupled inductors ib , ic and the loadcurrent iL should be analyzed. Using (1) and (2) and neglecting

the leakage inductance, one can obtain

2Mdibdt − 2M

dicdt

= ubc . (9)

Solving (3) and (9), the currents in the coupled inductors canbe expressed as follows:⎧⎪⎨

⎪⎩ib =

12(−iL + iripple)

ic =12(−iL − iripple)

(10)

where

iripple =1

2M

∫ubcdt. (11)

Suppose the ripple current in the coupled inductors is limitedto ΔI , the inductance M can be determined. Considering themost serious condition, i.e., |ubc | is always equal to 2E withinone Ts , the largest ripple current in the coupled inductors canbe calculated as follows:

iripple(max) = ΔI =1

2M

∫ Ts

02Edt =

Ts · EM

. (12)

Hence, the inductance M should satisfy

M >Ts · EΔI

. (13)

Meanwhile, from (10) one can see that the coupled inductors alsocarry half the load current besides the ripple current. Therefore,the load current should also be taken into account in designingthe inductor core. It is clear from (10) that one inductor and thusthe switch S3 /S4 or S5 /S5 carries about half the load current ifthe ripple component is low. Interestingly, the high-switchingfrequency devices S3–S6 take only half the load current whilethe low-switching frequency devices S1–S2 carry the whole load

2720 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012

Fig. 4. Steady-state results when u12ref = 40 cos(100πt) V. (a) u12 and u12ref . (b) ib , ic , and iL .

TABLE IVPARAMETERS OF THE INVERTER FOR SIMULATION AND EXPERIMENT

current. Thereby, the switching and conduction losses of S3–S6will not be very high because they only carry half of the loadcurrent. On the other hand, S1 and S2 switch at the fundamentalfrequency which will lead to very small switching losses. Thischaracteristic of the proposed inverter makes it very suitable forhigh-current applications.

V. SIMULATION RESULTS

In order to verify the validity of the topology with the opti-mized modulation scheme in this paper, the proposed inverteris tested with series-connected RL load. The load resistor is RL

and the load inductor is LL . The parameters of this inverter arelisted in Table IV.

Also, the five-level inverter can also output three-level voltageif the modulation index is low. To verify the validity of thepresented modulation method both in low and high modulation

index cases, the reference voltage u12ref is set as 40 cos(100πt)V(modulation index = 0.4) when t < 0.11 s and u12ref is set as80 cos(100πt)V (modulation index = 0.8) when t ≥ 0.11 s.

Fig. 4(a) and (b) shows the simulation results of the proposedinverter in steady state when the modulation index is 0.4. Onecan see that the output voltage of the inverter has three levels.In meantime, the ripple components in ib and ic are almostcomplementary to each other. Therefore, the ripple componentin the load current is substantially reduced compared with thatin ib or ic . It is also clear from Fig. 4(b) that the currents of thetwo coupled inductors have the same fundamental componentand no dc component exist in them. Fig. 5(a) and (b) shows thesteady-state performance of the inverter in this paper when themodulation index is 0.8. One can see that the output voltage ofthe inverter increases from three to five levels. Still, the ripplecomponents in ib and ic are almost complementary to each otherand the fundamental components are almost the same. Besides,no dc components exist in ib and ic . From Figs. 4 and 5, thefundamental component of ib or ic is about half the load currentwhich can be explained by (10).

To test the dynamic performance of the proposed inverter,u12ref is changed from 40 cos(100πt) V to 80 cos(100πt) V atthe instant of t = 0.11 s and the simulation results are displayedin Fig. 6. It is seen from Fig. 6(a) that the level number of the out-put voltage increases to five at t = 0.11 s. The currents in the twocoupled inductors are well balanced even in dynamic state whichis proved by Fig. 6(b). In fact, a little difference is generated

LI et al.: NOVEL SINGLE-PHASE FIVE-LEVEL INVERTER WITH COUPLED INDUCTORS 2721

Fig. 5. Steady-state results when u12ref = 80 cos(100πt) V. (a) u12 and u12ref . (b) ib , ic , and iL .

Fig. 6. Dynamic state results when u12ref changes from 40 cos(100πt) V to 80 cos(100πt) V at t = 0.11 s. (a) u12 and u12ref . (b) ib , ic , and iL .

2722 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012

Fig. 7. Photo of the coupled inductors.

Fig. 8. u12 (upper yellow line: 100 V/div). ib and ic (lower pink and purplelines: 5 A/div) under no load when the modulation index is 0.4.

between ib and ic at t = 0.11 s. Anyway, the fundamental com-ponents of the two currents become balanced naturally althoughthe high-frequency components caused by the switching are stillcomplementary to each other. What is more, in all these simu-lations, the height of the staircase in the output voltage is 50 Vor half of the dc-link voltage either in three-level or in five-level

Fig. 9. Experimental results of the proposed inverter under RL load whenthe modulation index is 0.4. (a) u12 (upper yellow line: 100 V/div), iband ic (lower pink and purple lines: 5 A/div). (b) u12 (upper yellowline: 100 V/div) and iL (lower pink line: 5 A/div). (c) Spectrum of ib /ic .(d) Spectrum of iL .

LI et al.: NOVEL SINGLE-PHASE FIVE-LEVEL INVERTER WITH COUPLED INDUCTORS 2723

Fig. 10. u12 (upper yellow line: 100 V/div), ib and ic (lower pink and purplelines: 5 A/div) under no load when the modulation index is 0.8.

condition. Compared with the H-bridge inverter, this is a sub-stantial reduction of the dv/dt in the inverter output voltage.

VI. EXPERIMENTAL RESULTS

The proposed inverter together with the optimized modu-lation scheme has also been experimentally tested. In the ex-periments, six 1200 V insulated gate bipolar transistors aretaken as the power switches S1–S6 . The modulation algorithmsare implemented in a TMS320F28335 DSP (TI product). Theother parameters of this inverter are the same as those listed inTable IV and the photo of the coupled (center-tapped) inductorsis shown in Fig. 7.

Figs. 8–12 show the experimental results of the proposedinverter under no load and RL load conditions with the modu-lation index of 0.4 and 0.8. It is clear that the output voltage isof three-level when the modulation index is 0.4 while it is offive-level when the modulation index is 0.8. Whether the mod-ulation index is low or high, the currents in the two coupledinductors have no dc or fundamental component under no loadcondition, which are shown in Figs. 8 and 10. When the inverteris loaded, S3–S6 take only half of the load current and still nodc component exist in the coupled inductor currents, which canbe seen from Figs. 9 and 11. Meanwhile, the ripple componentsof the currents in the coupled inductors are almost complemen-tary to each other. Therefore, the load current has little ripplecomponents. It is clear from Figs. 9(c) and (d) and 11(c) and (d)that the total harmonic distortion (THD) of ib and ic are high,but the THD of the load current iL is much lower comparedwith that of ib and ic . This result cannot be achieved withoutthe optimized modulation scheme. Meanwhile, one can see thatthe high-order harmonics in ib and ic are around 2 kHz or halfof the carrier frequency of S3–S6 , but not the carrier frequency.This is because the ripple component of the currents in ib and icare determined by the difference of S3 and S5 . Taking the CaseI region of SP5 or SP6 in Fig. 3 as an example, the switching

Fig. 11. Experimental results of the proposed inverter under RL loadwhen the modulation index is 0.8. (a) u12 (upper yellow line: 100 V/div),ib and ic (lower pink and purple lines: 5 A/div). (b) u12 (upper yellowline: 100 V/div) and iL (lower pink line: 5 A/div). (c) Spectrum of ib /ic .(d) Spectrum of iL .

2724 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012

Fig. 12. Experimental results of the proposed inverter under RL load whenu12ref changes from 40 cos(100πt) V to 80 cos(100πt) V: u12 (upper yellowline: 100 V/div), ib / ic (middle pink and purple lines: 5 A/div) and −iL (lowergreen line: 5 A/div).

pattern for (S3 , S5) is selected as SS1→SS2→SS1→L. Withinone Ts , the difference between S3 and S5 or (S3–S5) is −1/0if SS1 is selected while it is 1/0 if SS2 is selected. The voltageon the coupled inductors ubc will change its sign at half of thecarrier frequency. Therefore, the high-order harmonics in ib andic are around half of the carrier frequency.

The dynamic performance of the inverter is also tested by ex-periment and the results are shown in Fig. 12. The test conditionis the same as the simulation. Clearly, the level number of theoutput voltage increases from three to five when the modulationindex changes from 0.4 to 0.8. A little difference is generatedbetween ib and ic at the transient state. However, the fundamen-tal components of the two currents also become balanced laterwhile the ripple components are complementary to each other.All these experimental results fit the simulation results well andshow the validity of the proposed topology with the optimizedmodulation scheme.

VII. CONCLUSION

This paper proposed a novel single-phase five-level inverterbased on coupled inductors. This inverter can output five-levelvoltage with only one dc source and no split of the dc voltagecapacitor, totally avoiding the voltage balancing problem. Theheight of the staircase in the output voltage is only half of thedc-link voltage under any modulation index. Meanwhile, thevoltage stresses on all the power switches are the same and onlyfour switches are operated at high frequency. Operation mecha-nism of this inverter was analyzed and the optimized switchingpatterns were also presented to minimize the passive component.Verification results show validity of the proposed topology to-gether with the modulation method. The coupled inductors maybe the flaw of this converter. However, the switches taking thehigh current have low-switching frequency while the switchestaking the low current have high-switching frequency. There-

fore, the presented topology is very suitable for low to mediumpower applications, especially for high-current cases.

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Zixin Li (S’08–M’10) was born in Hebei Province,China, in 1981. He received the B.Eng. degree inindustry automation from North China University ofTechnology, Beijing, China, in 2001 and the Ph.D. de-gree (Honor) in power electronics and power drivesfrom the Institute of Electrical Engineering, ChineseAcademy of Sciences, Beijing, in 2010.

He joined the Institute of Electrical Engineering,Chinese Academy of Sciences, in 2010, where he iscurrently a Associate Professor. His research inter-ests include circuit topology, control and analysis of

power converters, especially multilevel converters in high-power fields.Dr. Li has received many honors and awards, including the scholarship

awarded to excellent Ph.D. candidates at the Graduate University of ChineseAcademy of Sciences offered by the Australia company BHP-Billiton in 2009and the student scholarship at the IEEE ISIE in 2009.

Ping Wang was born in Shanghai, China, in 1955.He received the B.S. degree from Lanzhou Univer-sity, Lanzhou, China, in 1980.

Since 1980, he has been with the Institute of Elec-trical Engineering, Chinese Academy of Sciences,Beijing, China, where he become an Assistant En-gineer in 1985, a Senior Engineer in 1993, and aProfessor of Power Electronics and Drives in 2008.From 1995 to 1996, he was a Visiting Researcher withthe Fraunhofer Institute for Production Systems andDesign Technology, Berlin, Germany. His research

interests include power electronics, static power converters, active filter, and acdrives.

Prof. Wang is a member of the China Electrotechnical Society.

Yaohua Li was born in Henan, China, in 1966. Hereceived the Ph.D. degree in 1994 from TsinghuaUniversity, Beijing, China.

From 1995 to 1997, he was a Postdoctoral Re-search Fellow in the Institute of Electrical Machine,Technical University of Berlin, Berlin, Germany. Hejoined the Institute of Electrical Engineering, ChineseAcademy of Sciences, Beijing, China, in 1997, wherehe is currently a Professor and Director of the Labo-ratory of Power Electronics and Electrical Drives.

His research interests include analysis and controlof electrical machines, and power electronics.

Fanqiang Gao (S’10–M’11) was born in Hubei,China, in 1984. He received the B.Eng. degree in con-trol science and engineering from the Huazhong Uni-versity of Science and Technology, Wuhan, China, in2006, and the Ph.D. degree in power electronics andpower drives from the Institute of Electrical Engineer-ing, Chinese Academy of Sciences, Beijing, China,in 2011.

His research interests include design, digital con-trol, and analysis of power converters.