475 Electronics for physicists Introduction to FPGA ...idlab/andrejs/notes.pdf · 475 Electronics for physicists Introduction to FPGA programming Andrej Seljak, Gary Varner Department

475 Electronics for physicistsIntroduction to FPGA programming

Andrej Seljak, Gary VarnerDepartment of Physics

University of Hawaii at Manoa

November 18, 2015

Abstract

Digital circuits based on binary functions can be constructed using discrete compo-nents, however by increasing the number of required components, the circuitry becomesvery impractical. A solution for prototyping digital signal processing is available usingField Programmable Gate Arrays (FPGAs). The use of FPGAs is also common priorto designing a real chip, such as computer processors. This document will explain thebasic steps how to program an FPGA to behave according to your design.

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Contents

1 Introduction 1

2 USB EVALUATION board 2

3 Programming tools 3

4 ISE environment presentation 4

5 Basics of VHDL coding 7

6 ISim simulator 8

7 Impact - download firmware on the chip 97.1 Impact - FPGA programming . . . . . . . . . . . . . . . . . . . . . . . . . . 107.2 Impact - Prom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

8 ADC/DAC expansion board 12

9 Firmware example using ADC and DAC 139.1 ADC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159.2 DAC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169.3 Glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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List of Figures

1 Left a picture of an FPGA on a printed circuit board. Right, a simplifiedbasic cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 A picture of the USB evaluation board developed in the ID laboratory. . . . 23 Xilinx ISE window project creation. . . . . . . . . . . . . . . . . . . . . . . . 44 Xilinx ISE device setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Adding files to project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Define inputs and outputs of your module. . . . . . . . . . . . . . . . . . . . 57 File text editor window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Schematic representation of the module . . . . . . . . . . . . . . . . . . . . . 69 Creation of a test file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 Configuration of stimulus signals. . . . . . . . . . . . . . . . . . . . . . . . . 911 Simulation result is as expected, the output signal is inverted. . . . . . . . . 912 Impact window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 Screenshot of Impact program showing how to make an MCS file. . . . . . . 1114 A picture of the ADC/DAC board. . . . . . . . . . . . . . . . . . . . . . . . 1215 A picture of the setup used for the firmware example. . . . . . . . . . . . . . 1316 Block diagram of the system. . . . . . . . . . . . . . . . . . . . . . . . . . . 1417 ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518 DAC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619 Glue logic block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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1 Introduction

Contemporary FPGAs have large resources of logic gates and RAM blocks to implementcomplex digital computations. Some FPGAs have analog features in addition to digitalfunctions. The most common analog feature is programmable slew rate and drive strengthon each output pin, allowing the engineer to set slow rates on lightly loaded pins that wouldotherwise ring or couple unacceptably, and to set stronger, faster rates on heavily loadedpins on high-speed channels that would otherwise run too slowly[1].

Figure 1: Left a picture of an FPGA on a printed circuit board. Right, a simplified basiccell.

Programming an FPGA requires the use of description languages. The most commonlyused are Verilog and VHDL (VHSIC Hardware Description Language). VHDL language is ahardware description language used in electronic design automation to describe digital andmixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDLcan also be used as a general purpose parallel programming language[1].Once the description of the circuit has being made, the compiler will take over and generatea programming file. This file is introduced into the FPGA via a JTAG controller and setsthe basic cells to behave as described in the program. Worth mentioning, that FPGAs comein different sizes and clocking speed options. FPGA vendors provide also a programmingenvironment for their products. We will use Xilinx tools for the demonstration.

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2 USB EVALUATION board

An evaluation board is commonly used during the development process of a project. It allowsto advance quickly with the proof of concept for a particular project.

Figure 2: A picture of the USB evaluation board developed in the ID laboratory.

The evaluation board you are about to use holds an Xilinx Spartan3AN FPGA, a JTAGconnector, power supply connector, a reset button, push buttons, a 16 bit configurableinput/output (IO) connected also to LEDs and an expansion connector. The expansionconnector allows to extend the number of I/O ports with another board which will bedescribed later. The schematic drawings of the board are available within the folder providedby your instructor.

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3 Programming tools

In order to program an FPGA we need an environment which allows us to write the code,compile it, simulate the code and download it on the target device. The tools are vendorspecific, but for our purposes we will use Xilinx tools. The following steps are a rudimentarypath explanation on how to successfully make a custom circuit:

• For programming the evaluation board we use ISE in the Xilinx.

• Once the code is written, it can be synthesized and simulated using Isim.

• Satisfied with the code working as expected, we can now generate the bitfile. Beforedoing so, we need to include the so called UCF file. This file links the signals from ourcode to the physical pins of the device. The generation of the bitfile is made in ISEprogram.

• Using Impact software we download the code on the FPGA. As soon as the file iswritten in the chip the operation starts. By pressing the hard reset button, a newdownload will be needed.

• The Spartan3AN has also a PROM memory inside, which allows do store a bit fileindefinitely. This file will automatically load at every power up of the device. We willsee later how to proceed in order to achieve so.

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4 ISE environment presentation

Go to start menu, find the Xilinx folder and start ISE.

Invoke File, follow new project, choose a directory and the name of your project.

Figure 3: Xilinx ISE window project creation.

Define the device you want to use. For our case, copy the settings from the picture below.

Figure 4: Xilinx ISE device setting.

Finish the process by clicking next.

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In order to make a file you can write in, click marked icon and choose VHDL module.Give it a name and click next.

Figure 5: Adding files to project.

In the next window you can name and define your inputs and outputs.

Figure 6: Define inputs and outputs of your module.

Click next to finish the process.

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A window like this will appear.

Figure 7: File text editor window

The left top window shows the files which are present in the project. Under the windowwhich allows you to run commands. The entire right window is typically used to displaythe code. The bottom window is a console window, where compiler warnings and errors willappear. Double click on View RTL schematic will show the block diagram.

Figure 8: Schematic representation of the module

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5 Basics of VHDL coding

Internet is a good staring point. There are a number of VHDL tutorials. For convenience,here are a few useful web pages:

• VHDL operators

• VHDL designers guide

• More manuals

A good starting point is to understand the definition for signals followed by logical op-erators. The next step would be to instantiate modules inside other modules and proceedwith the understanding how to build state machines. Its a lot to digest, so make sure, youunderstand thing well before proceeding. Keep in mind you are building your own digitalchip!

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6 ISim simulator

The next thing we need is to simulate the code. Coming back to our model of inverter. Wewant to see if the code behaves accordingly. In order to do so, add a new file. This timechoose VHDL Test Bench

Figure 9: Creation of a test file.

Associate the file with the file you want to simulate. The software generates a new filefor you. Note that the file does not appear in the left top window. However if you switchfrom Implementation to Simulation you will see it. This is convenient to separate the designwith the test benches. You can now define the stimulus signals. Test bench files are writtenin VHDL code as well.

Selecting Simulation in the menu, selecting your test file containing your file under testand double clicking on Simulate Behavioral Model will start Isim. This is what you expectto see. Your code behaving as you expect.

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Figure 10: Configuration of stimulus signals.

Figure 11: Simulation result is as expected, the output signal is inverted.

7 Impact - download firmware on the chip

Connect the USB Joint Test Action Gropu (JTAG) cable to the board and computer. UseImpact program to download the firmware on the FPGA. The process is straight forward.

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7.1 Impact - FPGA programming

When the Impact window opens, double click Boundary scan and next the marked icon. Thiswill open a connection to the FPGA. In short JTAG is standard upon which many devicesrelay for programming. You will notice, that along the FPGA another device is present.This is programmable read only memory (PROM) which is used to start up the FPGA instand alone mode.

Figure 12: Impact window

Select the device you want to program, right click and choose Assign new configurationfile. Find a bit file in the folder where your project resides. Next, right click and chooseprogram. A progress bar appears showing the process. That’s it.

7.2 Impact - Prom programming

The process is exactly the same as for the FPGA, however the prom uses a different typeof file which needs to be generated first. This will be an MCS file. The process is simple,choose Create Prom file from the left top window. Next choose the type of prom you have,click on the green arrow, set the Prom configuration as shown in the image, click the nextgreen arrow, define the file name and location to be stored. Finish with OK.

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Figure 13: Screenshot of Impact program showing how to make an MCS file.

In order to generate the file you need to click Operations, Generate file. The procedurefor loading the Prom is the same as for the FPGA. Next time you power cycle the board,the FPGA will start a program stored in the Prom.

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8 ADC/DAC expansion board

An extension board for the USB evaluation board is available. This board extends the IOpins from the high density connectors and has built in Analog to Digital Converters (ADCs)and Digital to Analog Converters (DACs.)

The following picture describes the board layout and connections.

Figure 14: A picture of the ADC/DAC board.

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9 Firmware example using ADC and DAC

The project is called USBeval and can be found within the folder structure.

The firmware example, will make use of the ADC and DAC converters in order to createa replicated signal. The ADC chip samples the signals on the input, digitized data are thenmoved into the DAC to replicate the signal on the input.

A number of interesting things can be learned by comparing the input and output signalon the oscilloscope. The more interesting once would be; the transfer function of the system,the time and amplitude resolution of the system, understand signal aliasing, to mention afew. You can test the firmware, by connecting the board to a 5V power supply, ADC ch0 toa function generator (and scope) and the DAC ch3 to the oscilloscope. The provided bit filewill enable its operation.Explore the ADC input headroom, offset the input signal, change functions on the generator,sweep across the frequency range. In addition, the digitized value is displayed on the LEDs.By choosing a low frequency (100 mHz), the LEDs behave as a binary counter.

Figure 15: A picture of the setup used for the firmware example.

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Firmware might be written in a number of ways however some modularity may sparea significant amount of time when trying to rewrite code for another project. Within theproject, you will encounter binary vectors, counters, state machines etc.In order to use the ADC and DAC, a serial communication with the chips is necessary. De-tails on serial protocols for reading and writing the chips can be found in the correspondingdata sheets in the provided documentation.

A way to start the design is to make drivers for external components. These should haveparallel inputs and outputs for internal data on one hand and serial communication withthe chips on the other. Once the drivers operate properly an internal logic is constructedto read data from the ADC driver and write into the DAC driver. A block diagram of thesystem is presented below.

Figure 16: Block diagram of the system.

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9.1 ADC driver

The purpose of the ADC driver is to release the programmer from the low level detailsdealing with the communication with the ADC chip.

Figure 17: ADC block diagram.

A clock of 40MHZ is required for operation. The driver reads the chip continuously viathe serial interface. Whenever the busy signal goes low (check at clock event), a fresh set ofconverted data is available on the 12bit rxdata port. While busy is high, a conversion andtransmission is taking place. The channel you want to read can be switched by changing thevalue at the chan(3:0). The ADC has 16 inputs you can choose from, however, only one canbe read at the time.

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9.2 DAC driver

The purpose of the DAC driver is to release the programmer from the low level details dealingwith the communication with the DAC chip.

Figure 18: DAC block diagram.

A clock of 40MHZ is required for operation. Similarly to the ADC driver, the DAC driverhas an 12bit input port, a busy output port and a go input pin. Whenever busy is high, thetransmission to the chip is active. During this time you are allowed to change the value onthe data port. As soon as busy goes low, strobe the go input for a clock cycle. This willactivate the driver and the data will be loaded on the chip.

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9.3 Glue logic

This module glues together the ADC and DAC. Its also a simple introduction to the con-struction of state machines. The glue logic takes the data from the ADC driver and writesthem in the DAC driver.

Figure 19: Glue logic block diagram.

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References

[1] Wikipedia

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