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Apr 06, 2018

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    Advantages:very highperformance andefficient

    Disadvantages:not flexible (cantbe altered afterfabrication) expensive

    Hardware

    (Application SpecificIntegrated Circuits)

    Software-programmed

    processors

    Advantages:software is veryflexible to change

    Disadvantages:performance cansuffer if clock is notfastfixed instruction setby hardware

    Chameleon

    computing

    Advantages:fills the gapbetween hardwareand software

    much higherperformance thansoftwarehigher level offlexibility than

    ASICs

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    y Conductors vs. Semiconductors

    y Periodic Table

    y Semiconductorsy Intrinsic SCy Extrinsic SC

    y P type

    y N type

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    y Junction Theory

    y Diode

    y Biasing p-n junction

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    y BipolarJunction Transistor

    y How does a transistor work?

    y Biasing a transistor

    y Characteristics of a transistor (regions)

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    Fig316_bjt_operation.swf

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    y An application-specific integrated circuit (ASIC) is anintegrated circuit (IC) customized for a particular use

    y For example, a chip designed solely to run a cell phone

    is an ASIC.y Designers of digital ASICs use a hardware description

    language (HDL), such as Verilog or VHDL, to describethe functionality of ASICs.

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    y A field-programmable gate array (FPGA) is anintegrated circuit designed to be configured by thecustomer or designer after manufacturing.

    y

    FPGAs contain programmable logic components called"logic blocks", and a hierarchy of reconfigurableinterconnects that allow the blocks to be wiredtogether.

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    y COPACOBANA, the Cost-Optimized Parallel COdeBreaker, is an FPGA-based machine which isoptimized for running cryptanalytical algorithms.

    COPACOBANA is suitable for parallel computationproblems which have low communicationrequirements. DES cracking is such a parallelizableproblem: an exhaustive key search of the DataEncryption Standard (DES) takes no longer than aweek on average with COPACOBANA.

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    128 Virtex-4 SX 35 FPGAsbrute-force attack against DES cracked in 7 days

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    Uses 28 Spartan-3 5000 FPGAs

    Data Encryption Standard (DES) was cracked in just 22hours and 15 minutes.

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    A chameleon processor is a reconfigurable microprocessor with erasablehardware that can rewire itself dynamically.

    This allows the chip to adapt effectively to the programming tasksdemanded by the particular software they are interfacing with at any giventime.

    Reconfigurable processor usually contains several parallel processingcomputational units known as functional blocks.

    While reconfiguring the chip, the connections inside the functional blocksand the connections in between the functional blocks are changing,

    that means when a particular software is loaded the present hardwaredesign is erased and a new hardware design is generated by making aparticular number of connections active while making others idle.

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    This will define the optimum hardware configuration for thatparticular software.

    It takes just 20 microseconds to reconfigure the entire

    processing array.

    Reconfigurable processors are currently available fromChameleon Systems, Billions of Operations (BOPS), andPACT (Parallel Array Computing Technology).

    Among those only Chameleon is providing a designenvironment, which allows customers to convert theiralgorithms to hardware configuration by themselves.

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    In a conventional ASIC or FPGA, multiple algorithms are

    implemented as separate hardware modules. Four algorithms

    would divide the chip into four functional areas.

    With Reconfigurable Technology, many algorithms are loaded

    into the entire reconfigurable Fabric one at a time.

    So finally the result is: much higher performance, lower cost

    and lower power consumption

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    32-bit RISC processor @125MHz

    64 bit memory controller

    32 bit PCI controller

    reconfigurable processing fabric (RPF)

    high speed system bus

    programmable I/O (160 pins)

    DMA(Direct Mem Access) Subsystem

    Configuration Subsystem

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    The Fabric provides unmatched algorithmic computation power to ChameleonChip. It consists of84,32-bit Data path Units24, 1624-bit MultipliersOperating at 125Mhz, they provide up to 3,000 16-bit Million Multiply-Accumulates

    Per Second

    24,000, 16-bit Million Operations Per Second.

    The fabric is divided into Slices, the basic unit of reconfiguration.

    y The CS2112 has 4 Slices with 3 Tiles in each. Each tile can be reconfigured atruntime

    y Tiles contain : Datapath Units Local Store Memories 16x24 multipliers Control Logic Unit

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    These chips includes banks of Programmable I/O (PIO)

    pins which provide tremendous bandwidth.

    Each Programmable I/O bank (ie each slice) of 40

    Programmable I/O pins delivers 0.5 GBytes/sec I/Obandwidth.

    Totally 2GBytes/sec aggregate I/O bandwidth isavailable from all the slices.

    These PIO banks can provide interface and handshakingsignals for SRAM, A/D, D/A, FPGA and other devices.

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    eCONFIGURABLE TECHNOLOGY:

    This technology reconfigures fabric in one clock

    cycle and increases voice/data/video channels per chip. As

    mentioned earlier, each Slice can be configuredindependently. Loading the Background Plane from external

    memory requires just 3 sec per Slice; this operation does

    not interfere with active processing on the Fabric. Swapping

    the Background Plane into the Active Plane requires just one

    clock cycle. with eConfigurable Technology;

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    C~SIDE Development Tools :With this software development tool , Chameleon Systems

    are providing the ability for the customers to do the

    programming themselves thus keeping the secrecy of theiralgorithms.

    The Chameleon Systems Integrated DevelopmentEnvironment (C~SIDE) is a complete toolkit fordesigning, debugging and verifying RCP designs.

    C~Side uses a combined C language and Verilog flow tomap algorithms into the chips reconfigurable processingfabric (RPF).

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    eBIOS (eConfigurable Basic I/O Services ):It provides a interface between the Embedded Processor

    System and the Fabric.

    eBIOS provides resource allocation, configuration

    management and DMA services.

    The eBIOS calls are automatically generated at compile

    time, but can be edited for precise control of any function.

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    Todays system architects have at their disposal an arsenal ofhighly integrated, high-performance semiconductortechnologies, such as application-specific integrated circuits(ASICs), application-specific standard products (ASSPs),

    digital signal processors (DSPs), and field-programmable gatearrays (FPGAs). However, system architects continue tostruggle with the requirement that communication systemsdeliver both performance and flexibility.

    Enter the reconfigurable processor, an entirely new category ofsemiconductor solution that serves as a system-level platformfor a broad range of applications.

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    can create customized communications signal processors

    increased performance and channel count

    can more quickly adapt to new requirements and standards

    lower development costs and reduce risk.

    Reducing power

    Reducing manufacturing cost.

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    Inertia Engineers slow to change

    y Inertia is the worst problem facing reconfigurable

    computing

    RCP designs requires comprehensive set of tools

    'Learning curve' for designers unfamiliar with reconfigurable

    logic

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    Wireless Base stations The reconfigurable technology mainly focuses onbase stations and their unpredictable combination of voice and data-traffic.Base-station infrastructure will have to be adaptive enough to accommodatethose requirements. With a fixed processor the channels must be able tosupport both simple voice calls and high-bandwidth data connections

    Wireless Local Loop (WLL) Reconfigurable technology is widely appliedin Wireless Local Loops also because of their high processing power,bandwidth and reconfigurable nature.

    High-Performance DSL (Digital Subscriber Line Technology) DSLtechnology brings high Bandwidth to homely users.

    Software-Defined Radio (SDR) SDR concept is applied in Cell phoneTechnology

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    y These new chips called chameleon chips are able to rewirethemselves on the fly to create the exact hardware needed torun a piece of software at the outmost speed.

    y Its applications are in, data-intensive Internet, DSP, wirelessbase-stations, voice compression, software-defined radio, high- performance embedded telecom and datacom applications,xDSL concentrators, fixed wireless local loop, multichannelvoice compression, multiprotocol packet and cell processing

    protocols. Its advantages are that it can create customized

    communications signal processors ,it has increasedperformance and channel count, and it can more quickly adaptto new requirements and standards and it has lowerdevelopment costs and reduce risk.

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