43503387_eng

DOK- 3

ModiconCompact 984Ladder LogicManual043503387

April, 1993

MODICON, Inc., Industrial Automation SystemsOne High StreetNorth Andover, Massachusetts 01845

GM-A120-LDR iiiPreface

PrefaceThe data and illustrations in this bookare not binding. We reserve the right tomodify our products in line with ourpolicy of continuous product improve-ment. Information in this document issubject to change without notice andshould not be construed as a commit-ment by Modicon, Industrial AutomationSystems. Modicon, Inc. assumes noresponsibility for any errors that mayappear in this document.

No part of this document may be re-produced in any form or by any means,electronic or mechanical, without theexpress written permission of Modicon,Inc., Industrial Automation Systems. Allrights reserved.

Modbus is a trademark of Modicon, Inc.

MODSOFT® Lite is a registered trade-mark of Modicon, Inc.

Copyright© 1993 by Modicon, Inc. Allrights reserved.

GM-A120-LDR Contents v

Contents

Chapter 1 Compact Controllers 1. . . . . . . . . . . . . . . .The Compact Controllers 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Common 984 Architecture 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Ladder Logic Programming 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .A120 I/O Support 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Power Supplies 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Auxiliary Memory Upload-Download Capabilities 3. . . . . . . . . .

Relocating Logic from One 984 to Another 4. . . . . . . . . . . . . . . . . .Relocating 984 Logic 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Compact CPU and User Memory Choices 5. . . . . . . . . . . . . . . . . .User Memory 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reference Numbering 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Logic Elements and Instructions 7. . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2 Modbus Plus 11. . . . . . . . . . . . . . . . . . . . . . . . . . . .Modbus Plus Capability for the Compact-984 Controller 12. . . . . .Modbus Plus Token Rotation 12. . . . . . . . . . . . . . . . . . . . . . . . . . . .How the 984-145 Initiates Modbus Plus Transactions 13. . . . . .

Modbus Plus Node Addressing 14. . . . . . . . . . . . . . . . . . . . . . . . . . . .Bridge Mode Between Modbus and Modbus Plus 16. . . . . . . . . . . .The Standard Modbus Setting 16. . . . . . . . . . . . . . . . . . . . . . . . . . .The Modbus Plus Bridge Mode Setting 16. . . . . . . . . . . . . . . . . . .Addressing Ranges on Modbus Plus 17. . . . . . . . . . . . . . . . . . . . .

Modbus Plus Address Routing Schemes 18. . . . . . . . . . . . . . . . . . .Destination Device Requirements 18. . . . . . . . . . . . . . . . . . . . . . .

Direct, Explicit, and Implicit Attaches 20. . . . . . . . . . . . . . . . . . . . . . .Modbus Plus Communication Paths 21. . . . . . . . . . . . . . . . . . . . . . . .Four Types of Communication Paths 21. . . . . . . . . . . . . . . . . . . . .

Chapter 3 Essentials of Ladder LogicProgramming 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Segments and Networks 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PREContentsvi GM-A120-LDR

Ladder Logic Segments 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Ladder Logic Networks 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Placing Relay Logic and Instructions in a Network 24. . . . . . . . .How Ladder Logic Is Solved 25. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Relay Logic Elements 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Relay Contacts 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Normal and Memory-retentive Coils 27. . . . . . . . . . . . . . . . . . . . . .Vertical and Horizontal Shorts 27. . . . . . . . . . . . . . . . . . . . . . . . . . .

Application Example:A Motor Start/Stop Circuit 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4 Counters and Timers 31. . . . . . . . . . . . . . . . . . .Counter Instructions 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Timer Instructions 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Application Example: Logic for a Real-time Clock 34. . . . . . . . . . . .

Chapter 5 Basic Math Instructions 35. . . . . . . . . . . . . . . .Integer Math Instructions 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Application Example: Fahrenheit-to-Centigrade Conversion 38. . .

Chapter 6 Data Management Instructions 39. . . . . . . .Moving Register and Table Data 40. . . . . . . . . . . . . . . . . . . . . . . . . . .Building a FIFO Stack 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Searching a Table 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Moving a Block of Data 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 7 Data Manipulation Instructions 47. . . . . . . .Boolean Logic Instructions 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .An Application Example: Simple Table Averaging 51. . . . . . . . . . . .Bit Complementing in a Data Matrix 52. . . . . . . . . . . . . . . . . . . . . . . .Bit Comparison in a Data Matrix 53. . . . . . . . . . . . . . . . . . . . . . . . . . .Sensing and Manipulating Bits in a Data Matrix 54. . . . . . . . . . . . . .

Chapter 8 The MSTR Instruction 57. . . . . . . . . . . . . . . . . .Overview 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .MSTR Function Error Codes 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Read andWrite MSTR Functions 61. . . . . . . . . . . . . . . . . . . . . . . . . .Get Local Statistics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clear Local Statistics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Write Global Data 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Read Global Data 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Get Remote Statistics 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GM-A120-LDR Contents vii

Clear Remote Statistics 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Read Peer Cop Communication Health 65. . . . . . . . . . . . . . . . . . . . .Network Statistics 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 9 Other Standard Instructions 71. . . . . . . . . . .Skipping Networks 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Checking Compact Health Status 73. . . . . . . . . . . . . . . . . . . . . . . . . .The Subroutine Instructions 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Sweep Instructions 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 10 Enhanced Instructions 81. . . . . . . . . . . . . . . .BlockeTable Move Instructions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . .The Checksum Instruction 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .The Proportional-Integral-Derivative Instruction 84. . . . . . . . . . . . . .Extended Math Instructions 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GM-A120-LDR Compact Controllers 1

Chapter 1Compact Controllers

The Compact Controllers

Relocating Logic from One 984 to Another

Compact CPU and User Memory Choices

Logic Elements and Instructions

PRECompact Controllers2 GM-A120-LDR

The Compact Controllers

Modicon’s Compact Programmable Log-ic Controllers bring the high perform-ance, application flexibility, and pro-gramming compatibility of the 984 familyto the small controller market. Like oth-er controllers in the 984 family, theCompacts implement a common instruc-tion set for developing user logic, alongwith Modbus and optional Modbus Pluscommunication capabilities.

Common 984 Architecture

The Compact Controllers share the fol-lowing processing architecture with allother controllers in the 984 family:

A memory section that stores userlogic, I/O tables, and system over-head in battery-backed CMOS RAMand holds the system’s Executivefirmware in nonvolatile EPROM

A CPU section that solves the userlogic program based on the currentinput values in state RAM, then up-dates the output values in state RAMAn I/O processing section that directsthe flow of signals from input mod-ules to state RAM and provides apath over which output signals fromthe CPU’s logic solve are sent to theoutput modulesA communications section that pro-vides one or more port interfaces.These interfaces allow the controllerto communicate with programmingpanels, host computers, hand-helddiagnostic tools and other master de-vices, as well as with additional con-trollers and other nodes on a Mod-bus (or Modbus Plus) network

984 Compact Controller

InputModules

State RAM

Register InsRegister Outs

Discrete InsDiscrete Outs

User Logic

Ladder logicnetworks &segments

Memory

CPU

from ApplicationSensing Devices

to ApplicationSwitching Devices

OutputModulesI/O Processor

Communications Processor

Peripheral(Host) Devices

Other Nodeson a Network


This architectural consistency allows theCompact Controllers to achieve ma-chine compatibility with the other con-trollers in the family. This means thatuser logic created on a midrange orhigh performance controller—such as a984-685 or a 984B Controller—can berelocated to a Compact if the specifica-tions of the Compact are not exceeded.Also, user logic you generate for thesmall controller is upwardly compatibleto a larger 984. It also means that aCompact can be easily integrated into amulti-controller network.

Ladder Logic Programming

All 984 Controllers can be programmedvia ladder logic, a powerful and highlygraphical language for control opera-tions. A database of standard ladderlogic instructions is stored in the systemExecutive.

A120 I/O Support

The Compact Controllers work with Mo-dicon’s low-cost series of A120 I/Omodules. A120 modules are availablein various densities of discrete I/Opoints and various numbers of analog I/O channels. For detailed descriptionsof available A120 modules, see theA120 Series I/O Modules User Guide(GM-A984-IOS).

Each module uses a standardized pairof screw-type terminal blocks that facili-tate easy access and easy field wiring.Because the terminal blocks are stan-dardized and removeable, they allowyou to make module changes withoutdisturbing connections.

A tool (AS-0TBP-000) to facilitate theremoval of terminal blocks is shippedwith the Compact.

Power Supplies

The Compact Controllers have a built-in5 VDC power supply that provides up to2.5 A across the I/O bus to all I/O mod-ules in the system.

An external 24 VDC source (--15% to+20% range, 1 A minimum) must beconnected to the Compact to power thesystem. If you are operating in an all-AC environment, you can use theAS-P120-000 Power Supply to convertAC source power to 24 VDC.

Some A120 I/O modules require anexternal 24 VDC supply, and othersrequire an external 115 or 230 VACsupply.

Auxiliary Memory Upload-Download Capabilities

All Compact Controllers contain an aux-iliary memory socket for a credit card-sized EEPROM card. You can write thecurrent system configuration and userlogic program to an EEPROM cardwhile the controller is stopped and readthe data back to the controller from theEEPROM card as part of the power-upsequence. This utility allows you to re-cord, store, and reload applications us-ing an easily accessible medium.


Relocating Logic from One 984 toAnother

The only constraints on logic relocationare that the program in the source con-troller must generate logic that imple-ments only instructions acceptable tothe target controller, and that the size ofthe source logic program must not ex-ceed the memory limits of the targetcontroller.

Relocating 984 Logic

Ladder logic from one 984 controllercan be easily downloaded to another984 using your panel software—e.g.,MODSOFT Lite. First you upload thesource program to your programmingpanel by selecting PLC on the mainmenu, then selecting Transfer from thetop level menu line.

The select PLC to File commandfrom the pulldown menu saves the con-tents of the target controller in a file.The File to PLC command from thepulldown loads the contents of the fileto a target controller.

PLC to FileVerify AllFile to PLC

Transfer


Compact CPU and User MemoryChoices

Several Compact models are currentlyavailable with different user memorysizes and various comm port offerings:

The 984-120 CPU with 1.5K words ofuser memory and one Modbuscommunication portThe 984-130 CPU with 4K words ofuser memory and one Modbuscommunication portThe 984-131 CPU with 4K words ofuser memory and two Modbuscommunication portsThe 984-141 CPU with 8K words ofuser memory and two Modbus com-munication portsThe 984-145 CPU with 8K words ofuser memory, one Modbus port, andone Modbus Plus network interface

User Memory

User memory is the amount of memoryspace (one word comprises 16 bits)provided for your user logic programand for the system overhead. Approxi-mately 1K of user memory is used forsystem overhead, and the remainingwords are available for application logic.

An additional 2048 (16-bit) words areprovided for state RAM—up to 1920words can be used for register/analoginputs, outputs, and internal data stor-age while the remainder is dedicated todiscrete I/O. Up to 2048 bits can beused for discrete inputs, outputs, and in-ternal coils.

All Compact models provide up to 256points of I/O under local control.

All Compact models solve logic at therate of 4.25 ... 6 ms/K nodes of stan-dard ladder logic.

Reference Numbering

For ladder logic programming, the Com-pact Controllers use a reference num-bering system to handle input/output in-formation and internal logic. Eachreference number has a leading digitthat identifies the I/O data type; theleading digit is followed by a string offour digits that defines that I/O point’sunique location in user data memory.

There are four reference types:

I/O Reference Numbering System

0xxxx A discrete output (or coil). A 0x referencecan be used to drive real output data throughan output unit in the control system or it canbe used to set one or more coils in stateRAM. A specific 0x reference may be usedonly once as a coil in a logic program, but thatcoil status may be used multiple times to drivecontacts in the program

1xxxx

ReferenceNumber Description

A discrete input. The ON/OFF status of a1x reference is controlled by field data sentto the CPU from an input unit. It can beused to drive contacts in a logic program

3xxxx An input register. A 3x register holds infor-mation represented by A 16-bit number andreceived from an external source—e.g., athumbwheel, an analog signal, data from ahigh speed counter. A 3x register can alsohold 16 consecutive discrete input signals,which may be entered into the register inbinary or binary coded decimal (BCD)format.

4xxxx An output or holding register. A 4x registermay be used to store numerical data (binaryor decimal) in state RAM or to send the datafrom the CPU to an output unit in the controlsystem.

Note:The x following the leading character in each refer-ence type represents a four-digit address location in userdata memory—e.g., the reference 40201 indicates thatthe reference is a 16-bit output or holding register locatedat address 201 in state RAM.


Each word in user memory is 16 bitslong. The (ON/OFF) state of each dis-crete I/O point is represented by the 1or 0 value assigned to an individual bitin a word (16 0x or 1x references perword).

Physical input points

User memoryreferences

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16

10001 10016. . . . . . . . . . . . . . . . . . . . . . . .

Discrete outputs are traffic copped to 0xregisters in a similar way

In the case of analog I/O, each inputchannel and each output channel is traf-fic copped to a full word in user datamemory (3x registers for inputs and 4xregisters for outputs).


Logic Elements and Instructions

Standard Ladder Logic Programming Elements

Symbol Meaning

--| |-- A normally open contact

--(L)-- A latched coil

--( )-- A normal coil

--|↓|-- A negative transitional contact

--|↑|-- A positive transitional contact

--|\|-- A normally closed contact

Compact Instruction Set

Instruction Meaning

T.01 Timer that measures in hundredths of a second

Counter and Timer Instructions (Two-Node Functions)

UCTR Counts up from 0 to a preset value

DCTR Counts down from a preset value to 0

T1.0 Timer that measures in seconds

T0.1 Timer that measures in tenths of a second

Instruction Meaning

Calculation Instructions (Three-Node Functions)

ADD Adds top node value to middle node value

SUB Subtracts middle node value from top node value

MUL Multiplies top node value by middle node value

DIV Divides top node value by middle node value

Instruction Meaning

DX Move Instructions (Three-Node Functions)

R→T Moves register values to a table

T→R Moves table values to a register

T→T Moves a specified set of values from one table toanother table

BLKM Moves a specified block of data

TBLK Moves a block of data from a table to anotherspecified block area

BLKT Moves a block of registers to specified locations in a table

FIN First-in operation to a queue

FOUT First-out operation from a queue

SRCH Performs a table search for a value

STAT Displays system status from locations in the controller’smemory


Compact Instruction Set (concluded)

Instruction Meaning

DX Matrix Instructions (Three-Node Functions)

AND Logically ANDs two matrices

OR Does logical inclusive OR of two matrices

XOR Does logical exclusive OR of two matrices

COMP Performs the logical complement of values in a matrix

CMPR Logically compares the values in two matrices

MBIT Logical bit modify

SENS Logical bit sense

BROT Logical bit rotate

CKSM Performs one of four possible checksum operations (Thisfunction is not available on the 984-145 Controller.)

Instruction Meaning

Skip-Node Instruction (One-Node Function)

SKP Skips a specified number of networks in ladder logic

Instruction Meaning

Ladder Logic Subroutine Instructions (One- and Two-Node Functions)

JSR Jumps from scheduled logic scan to a ladder logic subroutine

LAB Labels the entry point of a ladder logic subroutine

RET Returns from the subroutine to scheduled logic

Instruction Meaning

PID Instruction (Three-Node Function)

PID2 Performs a specified proportional-integral-derivative function

Instruction Meaning

Enhanced Math (Three-Node Function)

EMTH Performs 38 math operations, including floating point mathoperations and extra integer math operations such assquare root

Instruction Meaning

Modbus Plus Networking Instruction (Three-Node Function)

MSTR Specifies a function from a menu of networking operations(This function is available only on the 984-145 Controller,which supports Modbus Plus communications.)

The following chapters of this book pro-vide more details on the usage of thesestandard ladder logic elements andinstructions.


Loadable InstructionsThe Compact Controllers also supportvarious loadable instructions, including:

EARS, a tool for developing an earlyalarm reporting system (see EventAlarm Reporting System UserGuide, GM-EARS-001)EUCA, an engineering unit conver-sion algorithm (see EUCA LoadableFunction Block User Guide,GM-EUCA-001)FNxx, user-designed loadable in-structions created with our customloadable tool (see Custom LoadableSupport Software ProgrammingManual, GM-CLSS-001)DRUM and ICMP, which can be usedto create control logic for tenor drumsequencing applications (see DrumSequencer Demo S/W User Guide,GI-0984-SAS)HLTH, which creates history and sta-tus matrices that can be programmedto alert a user to changes in a PLCsystem (see Health Loadable UserGuide, GM-HLTH-001)

GM-A120-LDR Modbus Plus 11

Chapter 2Modbus Plus

Modbus Plus Capability for the Compact-984 Controller

Modbus Plus Node Addressing

Bridge Mode Between Modbus and Modbus Plus

Modbus Plus Address Routing Schemes

Direct, Explicit, and Implicit Attaches

Modbus Plus Communication Paths

PREModbus Plus12 GM-A120-LDR

Modbus Plus Capability for theCompact-984 ControllerModbus Plus is a local area network de-signed for industrial control applications.It enables the 984-145 Controller to be-come a node on the network and tocommunicate with other 984 controllers,host computers, and special bridge and

multiplexer devices. A network maycomprise one or more communicationsections—one section may support upto 32 nodes. Up to 64 nodes may existon a network.

RR85Repeater

6000 ft (1800 m), 64 Nodes per Network Max.

EndNode

EndNode

32 Nodes/Section Max.

RR85Repeater

RR85Repeater

Multiple Modbus Plus networks may beinterconnected using a BP85 BridgePlus device.

Network A (Up to 64 Nodes)

Network B (Up to 64 Nodes)

Node 5

Node 7

Node 5

BP85

Node Node

Node

Node

Node

= Terminating Connector

= Inline Connector

Node

Node 6 Node 8

Node 3 Node 4 Node 6

Each node within a network must havea unique address number in the range 1... 64. The node address of a 984chassis mount controller is specified us-ing a set of DIP switches provided onthe top front of the 984-145 module.

Modbus Plus uses a proprietary proto-col that delivers high performance inter-communication capabilities at a datatransfer rate of 1 Mbit/s. The networkmedium is twisted-pair shielded cable,laid out in a sequential multidrop pathdirectly between successive nodes.Taps and splitters are not used.

Modbus Plus TokenRotation

Each node on a Modbus Plus networkfunctions as a peer on a logical ring,gaining access to the network upon re-ceipt of a token frame. The token is abit grouping that is passed in a rotatingaddress sequence from one node to thenext. While an individual node holdsthe token, it may initiate data read/writeand statistical transactions with othernodes; when the node passes its token,it may write to a global database that ismaintained by all nodes on the network.Use of this global database allows rapid


updating of alarms, setpoints, and otherdata.

How the 984-145 InitiatesModbus Plus Transactions

A 984-145 (or any programmable con-troller with Modbus Plus capability) mayinitiate network communication using aladder logic function called MSTR.MSTR allows you to specify the type ofcommunications transaction you want tocarry out and to define the routing pathover which you wish the transaction totake place.

The MSTR block is part of the standard984-145 instruction set, contained in thesystem executive.

Note In order to thoroughly un-derstand Modbus Plus theory ofoperations, to be able to plan thelayout of the total network, and tomeet all the requirements of thenetwork cable installation, refer toModicon Modbus Plus NetworkPlanning and Installation Guide(GM-MBPL-001).

For a full description of the MSTR func-tion block, see Chapter 8 of this book.


Modbus Plus Node Addressing

Each node on a Modbus Plus networkmust be assigned a unique address inthe range 1 ... 64 using switches 1 ... 6

on the addressing DIP switch on the topfront of the 984-145 bezel.

Switches Shown in OFF Position

12345678

R = OFFL = ON

L R

Location of the Modbus Plus Addressing Switches


Modbus Plus Node Address Settings for the 984-145 Controller

Address

Switch Position

1234567891011121314151617181920212223242526272829303132

1 2 3 4 5 6 7 8

RLRLRLRLRLRLRLRLRLRLRLRLRLRLRLRL

RRLLRRLLRRLLRRLLRRLLRRLLRRLLRRLL

RRRRRRRRLLLLLLLLRRRRRRRRLLLLLLLL

RRRRRRRRRRRRRRRRLLLLLLLLLLLLLLLL

RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR

----------------------------------------------------------------

----------------------------------------------------------------

Address

Switch Position

1 2 3 4 5 6 7 8

----------------------------------------------------------------

----------------------------------------------------------------

3334353637383940414243444546474849505152535455565758596061626364

LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL

RLRLRLRLRLRLRLRLRLRLRLRLRLRLRLRL

RRLLRRLLRRLLRRLLRRLLRRLLRRLLRRLL

RRRRRRRRLLLLLLLLRRRRRRRRLLLLLLLL

RRRRRRRRRRRRRRRRLLLLLLLLLLLLLLLL

RRRRLLLLRRRRLLLLRRRRLLLLRRRRLLLL

RRRRLLLLRRRRLLLLRRRRLLLLRRRRLLLL


Bridge Mode Between Modbus andModbus PlusThe standard Modbus port on the984-145 Controller can be used in ei-ther of two ways: as a slave port to aModbus master device or as a bridgebetween a Modbus master device andthe Modbus Plus network nodes. Makethis selection by setting the comm pa-rameter slide switch (the bottom slideswitch) on the 984-145 Controller.

The Standard ModbusSetting

If you want the standard Modbus mode,set the switch to the mem (↓) position.You must set the desired Modbus portparameters in software—using the con-figurator editor.

The Modbus Plus BridgeMode Setting

Bridge mode allows you to accessnodes on a Modbus Plus network froma Modbus master device (connected tothe standard Modbus port). To set theModbus Plus bridge mode, set the slideswitch to default position—the control-ler’s bridge mode is automatically en-abled.

The Modbus port parameters are set to9600 baud, RTU mode (8 data bits and1 stop bit), and EVEN parity, the same

default conditions as the -120 and -130Controllers. Unique to the 984-145,however, is the default port address.Instead of defaulting to Modbus port ad-dress 1, it defaults to the Modbus Plusport address set by the DIP switch atthe top of the 984-145 Controller.

When a Modbus master device is con-nected to the Modbus port while the984-145 is in bridge mode, the masterdevice can be attached to the local con-troller or to any other node on ModbusPlus. When you attach to the local con-troller, messages from the Modbus mas-ter are sent directly to the local 984-145without being routed over a ModbusPlus communication path. When youattach to any other node on the net-work, the message is routed throughthe Modbus Plus port to the destinationdevice.

When you are connecting a Modbusmaster device to a node on ModbusPlus, always use the desired node’sModbus Plus address. If you are at-taching to the local 984-145 in bridgemode, the master automatically at-taches to the Modbus Plus node ad-dress set by the DIP switches on the lo-cal controller; however, if you want toattach to any other Modbus Plus node,the Modbus master device must specifythat node by Modbus Plus address.


Caution If you are accus-tomed to using Modbus masterdevices (such as programmingpanels) with Modicon program-mable controllers in un-networked environments, youmay be used to attaching tothe local controller by address-ing it as device #1—the defaultdevice address in the configu-rator editor. Be aware that in aModbus Plus network environ-ment you must know the Mod-bus Plus address of the con-troller (or any other nodaldevice) with which you want tocommunicate and you mustspecify that address correctlyin the attach procedure.

If you want to attach to a nodeon Modbus Plus but do notknow its network address, getthis information from your net-work supervisor before pro-ceeding.

Note When a Modbus port isused in bridge mode, it must beconnected to a single Modbusmaster device—the bridge can-not be used as a connection fora Modbus device network.

Addressing Ranges onModbus Plus

A single Modbus Plus network can haveup to 64 addressable nodes, each witha unique address in the range 1 ... 64).The Modbus master device connectedto the Modbus port can attach to anyone of these nodes using direct attachaddress routing, simply by specifyingthe correct address in the range 1 ...64.

Multiple networks can be joined viaBP85 Bridge Plus devices, and nodesacross multiple networks can be ad-

dressed. In cases such as this, you willrequire an addressing capability outsidethe 1 ... 64 range. Two address routingstrategies—explicit and implicit attachaddress routing—are available in Mod-bus Plus. These routing techniquesare described in the following sections.


Modbus Plus Address Routing SchemesModbus devices use addresses of onebyte in the range 1 ... 255. ModbusPlus devices are addressed in therange 1 ... 64, with five consecutiverouting bytes contained in each mes-sage. When a Modbus message is re-ceived at the Modbus port on the984-145 Controller, the single-byte ad-dress contained in the message is con-verted into a five-byte routing path forModbus Plus. The five bytes of routingare imbedded in a Modbus Plus mes-sage frame as it is sent from the origi-nating node.

Destination DeviceRequirements

The structure of the Modbus Plus rout-ing address is determined by the type ofdevice at the destination node:

If you are initiating a transaction withanother 984 controller, the last(rightmost) nonzero byte in the rout-ing scheme is the destination nodeaddress

If you are initiating a transaction witha network adapter in a non-controllernode—e.g., an SA85—the next tothe last nonzero byte is the destina-tion node address, and the last non-zero byte is the task # (range: 1 ... 8)

If you are initiating a transaction witha single slave on a Bridge MUX port,the next to the last nonzero byte isthe Bridge MUX node address, and

the last nonzero byte is the desiredMUX port # (range: 1 ... 4)

If you are initiating a transaction witha slave device on a Modbus networkconnected to a Bridge MUX, the sec-ond from the last nonzero byte is thenode address of the MUX, the nextto the last nonzero byte is the de-sired MUX port # (range: 1 ... 4), andthe last nonzero byte is the desiredModbus slave address (range:1 ... 247)

Any leading nonzero bytes ahead of theaddress bytes described above areBridge Plus node addresses.

Assume, for example, that your routingpath is to a controller two networks re-moved from the originating 984. Themessage is routed first to a BP85Bridge Plus at node address 25. Thebridge forwards the message to node20, a BP85 Bridge Plus device on thesecond network. Node 20 forwards themessage to the destination controllernode address 12 on the third network.The zero-content bytes in the fourth andfifth routing bytes specify that no furtherrouting is required beyond the thirdbyte:

Note The routing addressscheme must be developed aspart of an overall network plan-ning process—for details, seeModbus Plus NetworkPlanning and InstallationGuide (GM-MBPL-001).


Start End

RoutingBytes

Modbus Plus Message Frame

Routing Address 1Routing Address 2

Routing Address 3

Routing Address 4

Routing Address 5

25 20 12 0 0

A Message Frame Routing Path


Direct, Explicit, and Implicit AttachesThe manner in which Modbus Plus con-verts a Modbus message using bridgemode is determined by the range of theModbus address (1 ... 255):

Reserved

Direct AttachAddress

Reserved

Explicit AttachAddress

Implicit AttachAddress

01

6465

7069

8079

255

Modbus-to-Modbus Plus AddressConversion

If the address range in the Modbusmessage is between 1 ... 64, the mes-sage is routed to the correspondingModbus Plus node address on the localnetwork. This routing procedure iscalled direct attach address. Direct at-tach address routing implies that a non-zero value exists in only routing address1 in the Modbus Plus message frame; itdoes not allow you to send the incom-ing Modbus message beyond the localnetwork.

If the address range in the Modbusmessage is between 70 ... 79, the con-troller initiates an explicit attach addressprocedure which compares the Modbusaddress to an address table stored inthe controller. Up to 10 addresses inthe range 70 ... 79 become pointers tothe table, which contains up to 10stored routing paths for Modbus Plus.

(This table starts with the register thatimmediately follows the register se-lected for the free-running timer in thecontroller.)

Each routing path is five bytes in length.The routing path pointed to by each ad-dress is applied to the correspondingmessage.

Explicit attach address routing impliesthat nonzero values may exist in any orall routing addresses in the ModbusPlus message frame; it allows you tosend incoming Modbus messagesthrough as many as four BP85 BridgePlus devices across as many as fiveModbus Plus networks.

If the address range in the Modbusmessage is between 80 ... 255, the con-troller initiates an implicit attach addressprocedure which divides the address by10 and uses the quotient and remainderas the first and second bytes, respec-tively, in a routing path. Implicit attachaddress routing implies that there maybe nonzero values in routing addresses1 and 2 in the Modbus Plus messageframe; it allows you to send incomingModbus messages through one BP85Bridge Plus device across up to twoModbus Plus networks.


Modbus Plus Communication Paths

With multiple devices processing mes-sages asynchronously on a ModbusPlus network, it becomes possible foran individual device to have severalconcurrent transactions in process. The984-145 Controller opens a communica-tion path when a transaction begins,keeps it open during the transaction,and closes it when the transaction ter-minates. When the path is closed, itbecomes available for anothertransaction.

Four Types of Communica-tion Paths

A 984-145 Controller maintains fourtypes of communication paths

Data master paths—For read andwrite data or get and clear remotestatistics operations originated by aMSTR block in the 984-145Controller going to a destination de-vice on the network. A 984-145 sup-ports up to five data master paths—paths DM01 ... DM04 for processingup to four concurrent MSTR blocks,and path DM05 that may be usedfor data master transactions via theModbus port. Design your applica-tion to use a maximum of four MSTRdata master paths at any one time.

Data slave paths—For data readsand writes received over the network.The 984-145 supports up to four dataslave (DS) paths handling up to fourconcurrent network transactions.

Program master paths—For sendingprogramming commands from the lo-cal controller to the Modbus Plus net-work. Program master paths canhandle all Modbus commands—i.e.,function codes. When a Modbusmaster is connected to the Modbusport on the 984-145, it may be usedfor either programming or monitoringfunctions. A 984-145 supports oneprogram master (PM) path.

Program slave paths—For acceptingprogramming commands receivedover the network. A 984-145 sup-ports one program slave (PS) path.

Both the originating and destination de-vices open paths and maintain them un-til the transaction completes. If thetransaction passes through one or moreBridge Plus devices to access a desti-nation across multiple networks, eachbridge opens and maintains a path ateach of its two network ports. Thus alogical path is maintained between theoriginating and destination devices untilthe transaction is finished.

All paths are independent of one anoth-er, and activity on one path does not af-fect the performance of the other paths.

GM-A120-LDR 23Ladder Logic Programming

Chapter 3Essentials of Ladder LogicProgramming

Segments and Networks

Standard Ladder Logic Elements

Application Example: A Motor Start/Stop Circuit

Standard PLC Instructions

Instructions Available on Select Compact Models

PRELadder Logic Programming24 GM-A120-LDR

Segments and Networks

Ladder Logic Segments

All the ladder logic required to controlyour application is stored in a logic seg-ment in user memory. If you are callingsubroutines as part of your application,the subroutine logic must be placed in aseparate segment.

The Compact Controllers allow you toconfigure up to 32 logic segments. Thelast segment is where all subroutinelogic is stored. Subroutines logic isscanned only when it is called, eitherfrom the ladder logic or from an externalevent that triggers an interrupt.

Ladder Logic Networks

Each segment is composed of a groupof contiguous networks. Each networkis a small, clearly defined ladder dia-gram bounded on the left by a power

rail and on the right by a rail that, byconvention, is not displayed. The lad-der is seven rungs high by eleven col-umns wide.

The intersection of each rung and col-umn in the network is called a node—each network contains 77 nodes.

The number of networks in a segmentis limited by the amount of user pro-gram memory available in the CPU andby the time it takes for the CPU to scanthe ladder logic program.

Placing Relay Logic andInstructions in a Network

Each time you use an relay logicelement—e.g., a contact, a coil, a hori-zontal short—in ladder logic, the ele-ment consumes one node in the logicnetwork.

1 2 3 4 5 6 7 8 9 10 11

1

2

3

4

5

6

7

Ladder Logic Network Structure

PowerRail

NOTE Only coils canbe shown in column 11


An instruction in ladder logic may con-sume one, two, or three nodes in a net-work, depending on the instruction type.A counter instruction, for example, is atwo-high nodal instruction—it consumestwo contiguous nodes that must be oneover the other. An ADD instruction, onthe other hand, is a three-high nodal in-struction consuming three contiguousnodes stacked over each other.

How Ladder Logic Is Solved

A Compact Controller scans the ladderlogic program sequentially in the follow-ing order:

Segment by segmentNetwork 1 through network n se-quentially within each segmentNode by node within each network,starting in the upper left node of theladder and moving top to bottom,then left to right

Network 1

Network 2

Next Network

Power Flow in and between Ladder Logic Networks


Relay Logic Elements

There are three general types of relaylogic elements used in ladder logic pro-gramming—contacts, coils, and shorts.

Each relay logic element consumes onenode in a ladder network.

Relay Contacts

Contacts are used to pass or inhibitpower flow in a ladder logic program.Four kinds of contacts may be used:

The normally open (N.O.) contact,which passes power when its refer-enced coil or input is ON:

OFF

OFF

ON

ON

OFF

OFF

N.O. Contact

Power Flow

The normally closed (N.C.) contact,which passes power when its refer-enced coil or input is OFF:

OFF

ON

ON

OFF

OFF

ON

N.C. Contact

Power Flow

The positive transitional contact,which passes power for only one

scan as the contact or coil transitionsfrom OFF to ON:

OFF

OFF

ON

ON

OFF

PositiveTransitionalContact

Power Flow

OneScan

The negative transitional contact,which passes power for only onescan as the contact or coil transitionsfrom ON to OFF:

OFF

ON

ON

OFF

OFF

NegativeTransitionalContact

Power Flow

OneScan

The symbols used in ladder logic to rep-resent contact types are shown in thetable below.

Element Function

N.O. Contact

Symbol

N.C. Contact

PositiveTransitionalContact

NegativeTransitionalContact

Passes power whenits referenced coil orinput is ON

Passes power whenits referenced coil orinput is OFF

Passes power for onescan as the contact orcoil transitions fromOFF to ON

Passes power for onescan as the contact orcoil transitions fromON to OFF

Memory Utilization

Can be referenced to a logic coilin a 0x register or to a discreteinput in a 1x register





Normal and Memory-retentive Coils

Element FunctionSymbol

NormalCoil

Memory-retentiveCoil

M

Turns OFF whenpower is removed

Coil comes back inthe same state whenpower is restored forone scan

Memory Utilization

A discrete output value represented by a0x reference number; may be usedinternally in the logic program orexternally to a discrete output

A discrete output value represented by a0x reference number; may be usedinternally in the logic program orexternally to a discrete output

( )

( )

A coil is a discrete output value repre-sented by a 0x reference bit. Becauseoutput values are updated in state RAMby the CPU, a coil may be used inter-nally in the logic program or externallyvia the I/O map to a discrete output unitin the control system.

A coil is either ON or OFF, dependingon power flow. When a coil is ON, it ei-ther passes power to a discrete outputcircuit or changes the state of the asso-ciated internal relay contact in stateRAM.

There are two types of coils—normalcoils and memory-retentive coils. Whenpower is applied or restored to a normalcoil, any value previously held by thecoil is cleared prior to the first logicscan of the PLC. With a memory-reten-tive coil, the value previously held bythe coil is retained for one scan, thenthe logic takes control.

Displaying Coils in a NetworkA ladder network can contain a maxi-mum of seven coils. No logic elementsexcept coils are allowed in the eleventhcolumn. If a coil appears on a rung in acolumn other than 11, no other logicelement can be placed to the right ofthe coil on that rung.

Vertical and Horizontal Shorts

Shorts are simply straight-line connec-tions between instruction blocks and/orcontacts in a ladder logic network.

A vertical short connects contacts or in-struction blocks one above the other ina network column. Vertical shorts canalso be used to connect inputs or out-puts to create either/or conditions suchas the one illustrated on the followingpage. When two contacts are con-nected by a vertical short, power ispassed when one or both contact(s) re-ceive power. A vertical short does notconsume any user memory.

Horizontal shorts are used to expand arung in a ladder logic network withoutbreaking the power flow. Each horizon-tal short used in a program consumesone word of user logic memory.

On the following page are two examplesof how horizontal and vertical shortscan be used together with relay con-tacts to create ladder logic.

The first example is a simple either/orcondition—the top rung of ladder con-tains two N.O. contacts (10001 and10002), and the lower rung contains asingle contact (10003) followed by ahorizontal short. A vertical short con-nects the two rungs after the secondcolumn. Power can pass through thenetwork to energize coil 00001 wheneither contacts 10001 and 10002 areenergized or when contact 10003 isenergized.


The second example shows an Exclu-sive-OR circuit built with similar contactsand shorts. This circuit can be used toprevent coil 00001 from energizingwhen two conditions, represented bycontact 10001 and contact 10002, areactivated simultaneously.

In both examples, the vertical shorts,which do not consume any user pro-gram memory, are treated as part of thenode in which contact 10002 isprogrammed.

Example 1: Either/Or Relay Logic

10002 0000110001

10003

Example 2: Exclusive-OR Relay Logic

10002 0000110001

10001 10002


Application Example:A Motor Start/Stop Circuit

R1

LT

M1

C1

C2

MOTORSTART PB MOTOR

STOP PB OL1MOTOR START

RELAY

PUMPMOTOR

L1 L2

MOTOR STARTAUXILIARY CONTACT

STARTMOTOR

OL1

Above is an example of a standardacross-the-line electrical diagram for apushbutton-activated motor start/stopcircuit.

Pushing the motor start pb energizesmotor control relay R1 and closes con-tact C2 to start motor M1. The auxiliarycontacts on motor control relay C1 alsoclose, allowing the motor start/stop cir-cuit to be latched ON. Two things cancause relay R1 to drop out:

An overload (OL1) on motor M1The motor stop pb is pushed

Now let’s look at an implementation ofthe same circuit using contacts, coils,and shorts in a ladder logic network.

We see in the illustration below that thesequence of operation remains essen-tially the same when the motor start/stop circuit is designed for the control-ler. The big difference is that all the I/Opoints are wired directly to input/outputmodules contained in the programmablecontrol system, and the actual control isprogrammed in ladder logic.

The ladder logic implementation allowsgreater flexibility of control and de-creased development time, since all thehard-wiring between points of control isdone electronically.

R1

C1

START

STOPLT

10002 0000110001

10003 00002

10004INPUT

OL1

OUT-PUT

Field Inputs

Ladder Logic

Field Outputs

GM-A120-LDR 31Counters and Timers

Chapter 4Countersand Timers

Counter Instructions

Timer Instructions

Application Example: Logic for a Real-time Clock

PRECounters and Timers32 GM-A120-LDR

Counter InstructionsTwo counter instructions are provided.The up-counter (UCTR) counts up from0 to a preset value, and the down-

counter (DCTR) counts down from apreset value to 0. Both are two-highnodal instructions.

Up-counter

UCTR

I

I

O

O

Top:ON initiatescounter

Top:counter preset

Top:count = preset3x, 4x, or

K*

4x

Counts up from 0 toa preset value

Bottom:0 = reset1 = enabled

Bottom:accumulatedcount

Bottom:count < preset

Down-counter

DCTR

I

I

O

O

Top:ON initiatescounter

Top:counter preset

Top:count = 03x, 4x, or

K*

4x

Counts down from apreset value to 0


Bottom:accumulatedcount

Bottom:count > preset

Instruction Inputs(I)

Nodes Outputs

(O)

FunctionStructure

*K is an integer constant in the range 1 ... 999.

A Simple Up-counter ExampleWhen contact 10027 is energized, thetop input to UCTR receives power;since contact 00077 also passes power,the instruction is enabled. Each timecontact 10027 transitions from OFF toON, the accumulated count incrementsby 1. When the value reaches 100,the top output passes power—coil00077 is energized, and coil 00055 isde-energized. Contact 00077 openswhen coil 00077 is energized, and theaccumulated count is reset to 0 on thenext scan. On the next scan, coil00077 is de-energized; contact 00077closes and the UCTR is enabled.

0007710027

00077 00055

100

40007UCTR

GM-A120-LDR 33Counters and Timers

Timer InstructionsThe three timer instructions can beused to time events or create delays in

an application. They are two-high nodalinstructions.

One-secondtimer


Nodes Outputs

(O)

FunctionStructure

Timer incrementsat intervals of onesecond

T1.0

I

I

O

O4x

Top:ON when bot-tom input = 1

Top:timer preset

Top:time = preset


Bottom:accumulatedtime

Bottom:time < preset

3x, 4x, orK*

Tenth-of-asecond timer

Timer incrementsat intervals of 0.1 s

T0.1

I

I

O

O4x


Top:timer preset

Top:time = preset




3x, 4x, orK*

Hundredth-ofa-second timer

Timer incrementsat intervals of 0.01 s

T.01

I

I

O

O4x


Top:timer preset

Top:time = preset




3x, 4x, orK*


A One-second Timer ExampleWhen contact 10002 is closed—i.e., thetimer is enabled—the value contained inregister 40040 is 0. Coil 00108 is ONand 00107 is OFF. When contact10001 is closed, the count accumulatesin register 40040 at one-second inter-vals until 5 is reached; coil 00107 goesON and 00108 goes OFF. When con-tact 10002 is opened, the value in regis-ter 40040 is reset to 0, coil 00107 goesOFF, and 00108 goes ON.

0010710001

10002 00108

5

40040T1.0

PRECounters and Timers34 GM-A120-LDR

Application Example: Logic for aReal-time Clock

0060

T1.0

00001

00001

0060

40052UCTR

00001

00002

00002

00003

24

40051UCTR

00003

40053

00002

This example shows the ladder logic fora real-time clock with one-second accu-racy. The T1.0 instruction is pro-grammed to pass power at 1 min inter-vals. When logic solving begins, coil00001 is OFF, and both the top and bot-tom inputs of the timer instruction re-ceive power.

Register 40053 in the bottom node ofthe T1.0 instruction starts incrementingtime in seconds. After 60 increments,the top output passes power to energizecoil 00001 and opens N.C. contact00001 to reset register 40053 to 0.

N.C. contact 00001 closes and passespower to the count input of the firstUCTR. The accumulated count value inregister 40052 increments by 1, indicat-ing that one minute has passed.

Because the accumulated time count inT1.0 no longer equals the timer preset,coil 00001 loses power, N.C. contact00001 closes, and the timer begins tore-accumulate time in seconds and con-tinues to increment the first UCTR.When the accumulated count in register40052 of the first UCTR instruction in-crements to 60, the top output passespower and energizes coil 00002.

N.C. contact 00002 opens, and the val-ue in register 40052 resets to 0. N.C.contact 00002 closes, and the accumu-lated count in register 40051 of the sec-ond UCTR instruction increments by 1.This indicates that an hour has passed.

The time of day can be read in registers40051 (indicating the hour count),40052 (indicating the minute count), and40053 (indicating the second count).

GM-A120-LDR 35Basic Math Instructions

Chapter 5Basic MathInstructions

Integer Math Instructions

Application Example: Fahrenheit-to-Centigrade Conversion

PREBasic Math Instructions36 GM-A120-LDR

Integer Math InstructionsStandard addition, subtraction, multipli-cation, and division instructions are pro-vided for calculating integer math opera-

tions. Each of the four instructions is athree-high nodal instruction.

I O


Nodes Outputs

(O)

FunctionStructure

I O

O

O

I O

I

I

O

O

O

IntegerAddition

Absolute (nosigns in thevalues) IntegerSubtraction

IntegerMultiplication

IntegerDivision withremainder

3x, 4x, orK*

3x, 4x, orK*

3x, 4x, orK*

3x, 4x, orK*

3x, 4x, orK*

3x, 4x, orK*

3x, 4x, orK*

3x, 4x, orK*

ADD4x

Top:ON enables a(val 1) + (val 2)operation

Top:value 1

Middle:value 2

Bottom:sum

Top:sum > 9999 Adds the values in the

top and middle nodes,then stores the resultin a 4x register in thebottom node

Top:ON enables a(val 1) -- (val 2)operation

Top:value 1

Middle:value 2

Bottom:difference

Top:val 1 > val 2

Middle:val 1 = val 2

Bottom:val 1 < val 2

Subtracts the middlenode value from thetop node value andstores the differencein a 4x register in thebottom node

SUB4x


MUL4x

Top:ON enables a(val 1) x (val 2)operation

Top:value 1

Middle:value 2

Bottom:product (highorder digits)

Top:echos thetop input

DIV4x

Multiplies the valuesin the top and middlenodes, then stores theproduct in two contig-uous 4x registers

Top:ON enables a(val 1) / (val 2)operation

Middle:0 = fractional

remainder1 = decimal

remainder

Top:value 1**

Middle:value 2

Bottom:result(remainder inreg 4x + 1)

Top:divisionsuccessful

Middle:if result > 9999a value of 0 isreturned

Bottom:value 2 = 0

Divides the top nodevalue by the middlenode value, thenstores the result inthe 4x register in thebottom node and theremainder in register4x + 1

** If value 1 of the DIV instruction is stored 3x or 4x registers, then the register shown in the top node is the firstof two contiguous registers. The high-order half of value 1 is stored in the displayed register (3x or 4x) andthe low-order half of value 1 is stored in the next contiguous register (3x + 1 or 4x + 1).

GM-A120-LDR 37Basic Math Instructions

The MUL and DIV blocks require thattwo contiguous registers be used in thebottom node. The first of the two regis-ters is seen in the block, and the pres-ence of the second register is implicit.

In the MUL instruction block, the high-order portion of the calculated productis stored in the first bottom-node regis-ter and the low-order portion of theproduct is stored in the second bottom-node register.

In the DIV instruction block, the quotientis stored in the first bottom-node regis-ter and the remainder is stored in thesecond bottom-node register. If you donot use a constant as the top-node val-ue in a DIV instruction, then it the valuemust be placed in two contiguous 3x or4x registers. The high-order half of thevalue is stored in the displayed register,and the low-order half of the value isstored in the implied register.

For example, if the top-node value is105 and it were to be placed in twocontiguous registers, 40025 and 40026,instead of being given as a constant,then register 40025 would contain allzeros and register 40026 would containthe value 105.

A DIV ExampleHere is an example of a DIV operationwhere the top-node value, 105, isdivided by the middle-node value, 25.The quotient (4) is stored in register40271, and the remainder (5) is storedin register 40272.

10001

10002

105

40271DIV

25

When the middle input—contact10002—is open, the remainder is ex-pressed as a fraction (0005); when con-tact 10002 is closed, the remainder isexpressed as a decimal (2000).

PREBasic Math Instructions38 GM-A120-LDR

Application Example:Fahrenheit-to-Centigrade ConversionThis example implements the formula

°C = (°F -- 32) x 5/9When the top input to the SUB instruc-tion block receives power, the value inthe middle node, 32, is subtracted fromthe value stored in register 40007,some number of degrees Fahrenheit.The difference is placed in register41201.

The top input to the MUL instructionblock then receives power, regardless ofwhether the subtraction result is posi-tive, negative, or 0. In the case wherethe subtraction result is negative, coil00011 is energized to indicate a nega-tive value.

The value in the top-node register of theMUL block—register 41201—is thenmultiplied by 5 and the product isplaced in register 41202 and implicitregister 41203.

The top node in the DIV instructionblock is then energized, and the valuein registers 41202 and 41203 is dividedby 9. The quotient, which is the tem-perature conversion in degrees Centi-grade, is stored in register 40001 (andthe remainder in implicit register 40002).

Note: The vertical short to coil 00011 (indicating anegative value) must be placed to the left of the verticalshorts that link the three SUB block output.

40007

41201SUB

00011

32

41201

41202MUL

5

41202

40001DIV

9

GM-A120-LDR Dat39Data Management Instructions

Chapter 6Data ManagementInstructions

Moving Register and Table Data

Building a FIFO Stack

Searching a Table

Moving a Block of Data

PREData Management Instructions40 GM-A120-LDR

Moving Register and Table DataThree standard instruction blocks areprovided for moving the data stored inregisters and in tables of registers:

A register-to-table (R→T) DX move

A table-to-register (T→R) DX move

A table-to-table (T→T) DX move

A Compact Controller can accommo-date the transfer of one register perscan for each instruction in a ladderlogic program.

Each is a three-high nodal instruction.

I O


Nodes Outputs

(O)

FunctionStructure

I O

O

I O

Register-to-table move

0x, 1x, *3x, or 4x

4x

R→TK**

Top:source register

Middle:pointer to thetarget register(4x + 1) in thedestination table

Bottom:Table length*


** K is an integer constant in the range 1 ... 255.

I

I

O

Top:ON moves dataand incrementspointer

Middle:ON freezes thepointer

Bottom:ON resets thepointer to 0

Middle:pointer = table

length

Copies a 16-bit pat-tern in a source regis-ter to a register in thedestination table; thedestination register ispointed to by the 4xregister in the middlenode

Table-to-registermove

I

I

0x, 1x, *3x, or 4x

4x

T→RK**

Top:source table

Middle:pointer to thedestinationregister (4x + 1)







length

Copies the bit patternof a register in thesource table to adestination register(register 4x + 1 in themiddle node)

Table-to-tablemove OI

I

0x, 1x, *3x, or 4x

4x

T→TK**

Top:source table







length

Middle:pointer to thetarget register(4x + 1) in thedestination table

Copies the bit patternof a register in thesource table to aregister in the sameposition in a destina-tion table; thedestination register ispointed to by the 4xregister in the middlenode

* If you use a 0x or 1x reference, it must be given as a multiple of 16 + 1 (1, 17, 33, etc.), and it impliesthe use of 16 discrete bits (1 ... 16, 17 ... 32, 33 ... 48, etc.).


10001

10002 00135

30001

5R→T

10003

40340

The ladder logic example shown abovemoves the value stored in register30001 into a destination table of fiveholding registers, 40341 ... 40345. One30001 register value is moved into oneof the table registers in every scan.

The pointer to the destination table—re-gister 40340—is specified in the middlenode of the register-to-table instructionblock, and the number of holding regis-ters in the table, 5, is specified in thebottom node.

When contact 10001 transitions ON forthe first time, the current contents ofregister 30001 are copied to register40341, the first of five contiguous regis-ters in the destination table. The firsttable in the destination register is al-ways the next contiguous register afterthe pointer reference number given inthe middle node of the instruction block.When this DX move takes place, thevalue in the pointer register incrementsfrom 0 to 1.

In the next scan of contact 10001, thecontents of register 30001 are copiedinto register 40432, the second registerin the destination table; the value in thepointer register increments from 1 to 2.

This process continues until the con-tents of register 30001 are copied intoregister 40345 in the table and thepointer value has incremented to 5. Atthis point, the middle output from theblock passes power and energizes coil00135.

No further register-to-table moves arepossible while the value of the pointerequals the table length specified in thebottom node of the block.

Pointer

SourceRegister

DestinationTable

40340

40341

40342

40343

40344

40345

300011st transition

2nd transition

3rd transition

4th transition

5th transition

If, after the second transition of contact10001, contact 10002 were to becomeenergized, the pointer value would befrozen-i.e., it could not be incrementedor decremented—and subsequent tran-sitions of contact 10001 would causethe current value in register 30001 to becopied to register 40343.

If contact 10003 is energized, the valueof the pointer is reset to 0.


Building a FIFO StackInstruction Inputs

(I)Nodes Outputs

(O)

FunctionStructure

I O

O

O

I O

O

O

First-in toa queue stack

0x, 1x, *3x, or 4x

4x

FINK**

Top:ON inserts a bitpattern in thetop of the stack

Middle:pointer to theregister in thestack where thesource bits willbe insertedBottom:stack length*


Middle:stack is full

Bottom:stack isempty

Copies a 16-bit pat-tern into a register atthe top of a stack; thetable begins at regis-ter 4x + 1 of themiddle node

First-out ofa queue stack

0x or 4x

4x

FOUTK**

Top:ON removesthe bit patternfrom the bottomof the stack


Middle:stack is full

Bottom:stack isempty

Top:pointer to thesource registerin the stack

Middle:destination registerwhere source bitswill be moved

Bottom:stack length*

Moves the bit patternin the bottom registerof the stack to a des-tination register out ofthe stack

** K is an integer constant in the range 1 ... 255.

Top:The sourceregister in thestack


The two instructions above let youqueue data into a first-in/first-out stack.The FIN instruction copies the bit pat-tern of a register or of 16 discretes intoa register at the top of a table (or stack)of holding registers.

111 111

SourceFIN

Stack

222 222

SourceFIN

Stack

111

333 333

SourceFIN

Stack

111

222


The FOUT instruction moves the bit pat-tern down through the stack, then out ofthe stack and into a destination table.

Warning FOUT will overrideany disabled coils in a desti-nation table without enablingthem. If a coil has been dis-abled for repair or mainte-nance, there is the potentialfor injury, since that coil’sstate can change as a result ofthe FOUT operation.

When you are running a FIFO stack inladder logic, the FOUT instructionshould be executed in each scan beforethe FIN instruction so that the oldestdata in the stack can be cleared to thedestination table before the newest datais queued into the stack. If the FINblock is executed first, an attempt to en-ter data into a filled stack is ignored.

Destination

FOUT

Stack

333

222

111 111

444

333

SourceFIN

Stack

222

444


Searching a TableThe SRCH instruction allows you tosearch a table of registers for a specificbit pattern contained in one of the table

registers. SRCH is a three-high nodalinstruction.

I O


Nodes Outputs

(O)

FunctionStructure

Table search

3x or 4x

4x

SRCHK*

Top:first register inthe source table

Middle:4x pointer to thelocation in thetable of the regis-ter holding thevalue searchedfor; the next reg-ister, 4x + 1, con-tains the valuebeing searchedfor



I O

Top:ON initiates asearch

Middle:0 = search from

the beginning1 = search from

last match

Middle:match found

Searches a table ofregisters for the bitpattern specified inthe register immedi-ately following thepointer in themiddle node

* K is an integer constant in the range 1 ... 255.

An Example of a SRCH Operation

10001

10002 00142

40421

5SRCH

40430

The source table to be searched is fiveregisters long starting at holding register40421, and the content of the table reg-isters is as follows:

Source TableRegisters

RegisterContent

40421

40422

40423

40424

40425

=

=

=

=

=

1111

2222

3333

4444

5555

The bit pattern to be searched for is3333, which is the value that gets en-tered into register 40431 (the register

immediately following the pointer regis-ter in the middle node).

When contact 10001 transitions fromOFF to ON, the logic searches thesource table for the register that con-tains 3333. When that value is found(in register 40423), the pointer value inregister 40430 is set to 3, indicating thatthe third register in the source tablecontains the searched-for value; coil00142 is also energized for one scan.


Moving a Block of DataThe block move (BLKM) instruction co-pies the entire contents of a sourcetable of registers to a destination tablein one logic scan. BLKM is a three-highnodal instruction.

Warning BLKM will overrideany disabled coils in a desti-nation table without enablingthem. If a coil has been dis-abled for repair or mainte-nance, there is the potentialfor injury, since that coil’sstate can change as a result ofthe BLKM operation.


Nodes Outputs

(O)

FunctionStructure

I O

Block move

0x, 1x, *3x, or 4x

0x** or4x

BLKMK***

Top:source table

Middle:destination table



Top:ON initiates ablock move

Copies the entirecontents of one tableto another table ofoutputs or holdingregisters

*** K is an integer constant in the range 1 ... 100.


** If 0x references are used as the destination, they cannot be programmed as coils, only as contactsreferencing those coil numbers

Application Example: A Recipe Loading Routine Using Block MovesA ladder logic program can store a col-lection of specific process recipes, eachin a unique storage table and loadableon demand to a working table where ageneric process is being run. Therecipes must be structured with similartypes of information in correspondingregisters—if heating temperature infor-mation is kept in the third register ofone recipe, similar information shouldbe kept in the third register of all theother recipes as well.

Specific recipes can be loaded to andremoved from the generic process viaBLKM instructions.

The logic example shown on the nextpage contains an eight-register workingtable (registers 40201 ... 40208) inwhich three different recipes can be run.Recipe selection is handled by three in-put switches, contacts 10101, 10102,and 10103.


40101

40201

BLKM

10101 10102 10103

8

40109

40201

BLKM

10102 10101 10103

8

40117

40201

BLKM

10103 10101 10102

8

To run process A, for example, turncontact 10101 ON and leave contacts10102 and 10103 OFF. When input10101 is energized, it passes powerthrough N.C. contacts 10102 and10103, and the first BLKM block movesthe recipe for process A from registers40101 ... 40108 to registers 40201 ...40208.


Chapter 7Data ManipulationInstructions

Boolean Logic Instructions

An Application Example: Simple Table Averaging

Bit Complementing in a Data Matrix

Bit Comparison in a Data Matrix

Sensing and Manipulating Bits in a Data Matrix

PREData Manipulation Instructions48 GM-A120-LDR

Boolean Logic InstructionsThree instructions are available to per-form ANDing, ORing, and XORing logicoperations.

Warning These Boolean in-structions will override anydisabled coils in the destina-

tion matrix without enablingthem. If a coil has been dis-abled for repair or mainte-nance, there is the potentialfor injury, since that coil’sstate can change as a result ofthe logic operation.

I O


Nodes Outputs

(O)

FunctionStructure

0x, 1x, *3x, or 4x

0x** or4x

ANDK****

*** K is an integer constant in the range 1 ... 100

I O0x, 1x, *3x, or 4x

0x** or4x

ORK***

I O0x, 1x, *3x, or 4x

0x** or4x

XORK***

Top:Initiates a logicalAND operation


BooleanAND

BooleanOR

Booleanexclusive OR

Top:Initiates a logicalOR operation


Top:Initiates a logicalXOR operation


Top:source matrix

Middle:destination matrix

Bottom:matrix length*

Top:source matrix



Top:source matrix



ANDs the bits in thesource matrix withthe equivalently po-sitioned bits in thedestination matrix,then places the re-sults in the destina-tion matrix, over-writing the originalbit pattern

ORs the bits in thesource matrix withthe equivalently po-sitioned bits in thedestination matrix,then places the re-sults in the destina-tion matrix, over-writing the originalbit pattern

XORs the bits in thesource matrix withthe equivalently po-sitioned bits in thedestination matrix,then places the re-sults in the destina-tion matrix, over-writing the originalbit pattern




0 1 1 0

0 1100 0 01

Source Matrix Bits

Destination Matrix Bits

An ANDing Operation

An AND instruction logically ANDs eachbit in a source matrix with the corre-sponding bits in a destination matrix,then posts the results in the destinationmatrix—overwriting the previous bit pat-tern in the destination matrix.For example, when contact 10001passes power in the network below, thebit matrix comprising registers 40600and 40601 are ANDed with the bit ma-trix comprising registers 40604 and40605.

10001

40600

2AND

40604

The result is then copied into registers40604 and 40605, overwriting the pre-vious bit pattern.

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 040600

40601

Source Matrix

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

40604

40605

Original Destination Matrix

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

40604

40605

ANDed Destination Matrix

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

ORLikewise, an OR instruction logicallyORs the bits in a source matrix with thecorresponding bits in a destination ma-trix, then overwrites the destination ma-trix with the results of the operation.

Note Outputs and coils cannotbe turned OFF with the OR in-struction.

0 1 1 0

0 100 1

Source Matrix Bits

Destination Matrix Bits1

An ORing Operation

11


For example, if we were to OR thesame two matrixes as in the exampleshown above:

10001

40600

2OR

40604

the result would be:

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 040600

40601

Source Matrix

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

40604

40605


1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

40604

40605

ORed Destination Matrix

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

XORThe exclusive OR instruction logicallyXORs the bits in a source matrix with

the corresponding bits in a destinationmatrix, then overwrites the destinationmatrix with the results of the operation.

For example, if we were to XOR thesame two matrixes as in the exampleshown above:

10001

40600

2XOR

40604

the result would be:

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 040600

40601

Source Matrix

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

40604

40605


1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

40604

40605

XORed Destination Matrix

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 1 1 0

0 100 01

Source Matrix Bits

Destination Matrix Bits1

An XORing Operation

1

Archiving the Original Destination Matrix ValuesIf you want to save the original bit pat-tern from the registers in the destinationmatrix, use the BLKM instruction tocopy the information into another tablebefore running the Boolean logic opera-tion.


An Application Example: Simple TableAveraging

40101

84T→R

00003

40203

40202

40202ADD

40201

40201ADD

1

40201

40301DIV

40203

40201

3XOR

10006

40204

40201

Here is an application routine that com-bines three integer math calculationswith a data transfer and an XOR in-struction. It calculates the average val-ue of the 84 values stored in the tableof registers 40101 ... 40184.

When contact 10006 closes, the topnode in the table-to-register instructionreceives power, initiating the data trans-fer. The value in the first register of thetable is copied into the middle node ofthe first ADD instruction, and the tablepointer value increments register 40203in the middle node of both the table-to-register instruction and the DIV instruc-tion. Because the top output from thetable-to-register instruction passespower, the first ADD block receivespower and adds the value in register40204 to the value in register 40202(which is initially 0); then the sum of thisaddition overwrites the previous value inregister 40202.

The routine continues to run this wayuntil all the values in the table of 84registers have been added together. Atthis point, the pointer value in themiddle node of the table-to-register in-struction is 84, and the middle output

from that instruction passes power andenables the DIV instruction.

The values in registers 40201 (all 0s,representing the high-order portion ofthe sum of all the register values in thetable) and 40202 (the low-order portionof the sum) are divided by 84. The re-sult is placed in register 40301, and theremainder is placed in register 40302.(Because there is power to the middleinput of the DIV instruction, the remain-der is expressed as a decimal.) The re-sult of the DIV operation is the averagevalue of the current values stored in all84 registers in the table.

When the top output from the DIV in-struction passes power, the XOR in-struction becomes empowered. It ex-clusively ORs the values in registers40201 ... 40203 with themselves, clear-ing the matrix to 0s and indicating thatthe current table averaging operation iscomplete and that a new one shouldstart.


Bit Complementing in a Data MatrixThe COMP instruction complements thebit pattern in a matrix—i.e., changes allthe 0s to 1s and all the 1s to 0s—thencopies the result in a second matrix. Amatrix can be complemented in onescan.

COMP is a three-high nodal instruction.

Warning COMP will overrideany disabled coils in a desti-nation matrix without enablingthem. If a coil has been dis-abled for repair or main-tenance, there is the potentialfor injury, since that coil’sstate can change as a result ofthe COMP operation.


Nodes Outputs

(O)

FunctionStructure

*** K is an integer constant in the range 1 ... 100

I O0x, 1x, *3x, or 4x

0x** or4x

COMPK***

Top:ON initiates thebit complementoperation


Top:source matrix



Bitcomplement

Complements thebit values in thesource matrix andplaces the resultsin the destinationmatrix



A Bit Complement ExampleThe ladder logic below shows a COMPblock with a source matrix composed oftwo registers—40250 and 40251—anda destination matrix composed of regis-ters 40252 and 40253.

10001

40250

2COMP

40252

When contact 10001 passes power theblock complements the bit values in the

source register and places the results inthe destination register.

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 040250

40251

Source Matrix

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

40252

40253

Complemented Destination Matrix

All values stored in the destination reg-ister before the COMP instruction is en-abled will be overwritten by the com-plemented source values as a result ofthe COMP operation.


Bit Comparison in a Data MatrixThe CMPR instruction compares the bitpattern in one register matrix with thebit pattern in another matrix. When abit value in one matrix miscompares

with the correspondingly positioned bitvalue in the other matrix, a value indi-cating that matrix location is posted inthe middle node.


Nodes Outputs

(O)

FunctionStructure

** K is an integer constant in the range 1 ... 100

I O

O

O

4x

CMPR

I

0x, 1x, *3x, or 4x

K**

Bitcompare

Top:ON initiates thebit compare

Top:matrix a

Middle:posts the bit posi-tion of the current-ly detected mis-compared bit andpoints tomatrix b, whichbegins at 4x + 1


Middle:0 = restart at last

miscompare1 = restart at the

beginning


Middle:miscomparedetected

Bottom:state of mis-compared bitin matrix a

Compares bit patternsin matrixes a and b,and reports miscom-pares


A Bit Comparison Example

10001

10002 00143

44620

2CMPR

44622

00144

This example shows a bit comparisonbetween two two-register matrixes. Ma-trix a comprises registers 44620 and44621; matrix b comprises registers44623 and 44624:

1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 040600

40601

Matrix a

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

40604

40605

Matrix b

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Matrix a is compared against matrix bbit by bit on every scan that contact

10001 transitions from OFF to ON untilone miscompare is found.

In the first transition of contact 10001,the matrix bits are compared until bit17, where the value in matrix a = 1 andthe value in matrix b = 0. At this point,a value of 17 is posted in register44622, the comparison stops, and coils00143 and 00144 energize for onescan.

If contact 10002 is energized, the func-tion will begin to compare at matrix po-sition 1 in the next transition of 10001and stop again when the value in regis-ter 44622 = 17. If contact 10002 is notenergized, the function will begin tocompare at matrix position 18 in thenext transition of 10001 and stop whenthe value in register 44622 = 25.


Sensing and Manipulating Bits in aData MatrixThree instructions are provided to letyou examine and manipulate the bit pat-terns in a data matrix:

The bit-sense (SENS) instruction ex-amines and reports the sense—1 or0—of specific bits in the matrix

The bit-modify (MBIT) instruction mo-difies the sense of a specific bit in amatrix—i.e., changes a 0 bit to 1 andclears a 1 bit to 0

The bit-rotate (BROT) instructionshifts the bit pattern in a matrix to theleft or right, forcing the exiting bit toeither fall out of the matrix or wraponto the other end of the register

One bit per scan may be sensed, modi-fied, or rotated via these instructions.Each is a three-high nodal instruction.


Nodes Outputs

(O)

FunctionStructure

*** K is an integer constant in the range 1 ... 100 ;K1 is an integer constant in the range 1 ... 255

I O

O

MBIT

I O0x, 1x, *3x, or 4x

0x** or4x

BROTK***

I O3x, 4x,or K1***

0x** or4x

SENSK1**

I

K1***

Bitsensing

Bitmodification

Bitrotation

3x, 4x,or K1***

0x** or4x

I O

I O

OI

I O

I

Top:ON initiates thebit rotation

Middle:0 = start left1 = start right

Bottom:0 = bit falls outof the register1 = bit wraps tostart of register

Top:source matrix




Middle:sense of the bitrotating out ofthe matrix

Rotates or shifts thebit pattern in a matrix,shifting the bits oneposition per scan

Top:ON reports thesense of thematrix bits

Middle:increments thepointer after abit sense

Bottom:resets thepointer to 1

Top:pointer to thematrix

Middle:address of firstregister in thematrix

Bottom:matrix length**


Middle:copies thesensed bit

Bottom:pointer > matrix

length

Examines and reportsthe sense of specificbits—i.e., 1 or 0—in amatrix; one bit perscan can be sensed

Top:ON changesthe sense ofthe matrix bits

Middle:0 = clear bit1 = set bit

Bottom:increments thepointer after bitmodification

Top:pointer to thematrix

Middle:address of firstregister in thematrix

Bottom:matrix length**


Middle:echos themiddle input

Bottom:pointer > matrix

length

Changes the value ofa bit in the matrixfrom 0 to 1 or from 1to 0; one bit per scancan be modified




Warning MBIT and BROT willoverride any disabled coils inthe matrix without enablingthem. If a coil has been dis-abled for repair or mainte-nance, there is the potentialfor injury, since that coil’sstate can change as a result ofbit manipulation.

GM-A120-LDR 57The MSTR Instruction

Chapter 8The MSTR Instruction

Overview

MSTR Function Error Codes

Read andWrite MSTR Functions

Get Local Statistics

Clear Local Statistics

Write Global Data

Read Global Data

Get Remote Statistics

Clear Remote Statistics

Read Peer Cop Communication Health

Network Statistics

PREThe MSTR Instruction58 GM-A120-LDR

OverviewThe 984-145 Compact Controller sup-ports Modbus Plus communications. Aspecial instruction called MSTR is pro-vided with this controller to allow it toinitiate Modbus Plus message transac-tions via ladder logic. An MSTR in-struction allows you to initiate one ofeight possible operations:

MSTR Function CodeWrite data

Read data

Get local statistics

Clear local statistics

Write global database

Read global database

Get remote statistics

Clear remote statistics

1

2

3

4

5

6

7

8

Read peer cop health 9

Up to four MSTR instructions may be si-multaneously active in a ladder logicprogram. More than four MSTRs maybe programmed to be enabled by thelogic scan—i.e., as one active MSTRreleases the resources it has been us-ing and becomes inactive, the nextMSTR encountered by the logic scanmay be activated.

MSTR is a three-high nodal instruction:

Bottom:Operation hasbeen completedsuccessfully

Bottom:Maximum num-ber of registersin the data area


Nodes Outputs

(O)

FunctionStructure

Modbus Plusmaster function I

Top:ON activatesthe selectedMSTR function

Top:First of nine regis-ters in the MSTRcontrol block

* K is an integer constant in the range 1 ... 100

I

O

O

O

4x

4x

MSTR

K*

Middle:Terminates anactivates MSTRoperation

Middle:The data area**

Initiates a ModbusPlus communica-tion function fromladder logic

Top:Selected functionis active

Middle:Operation hasterminatedunsuccessfully

** For operations that provide the communications processor with data—e.g., write functions—the data area isthe source of the data. For operations that acquire data from the communications processor—e.g., readfunctions—the data area is the destination of the data


Register Function

MSTR Control Block (pointed to by the register in the top node)

4x Identifies one of the nine MSTR functions

4x + 1 Displays the error status in hex format (see error codes on the next page)

4x + 2 Displays the length (see descriptions of individual functions for specifics)

4x + 3 Displays function-dependent information (see descriptions of individual functions for specifics)

4x + 4 The Routing 1 register, which uses the bit value of the low byte to designate the address of thedestination device:

0 0 0 00 0 0 0 0 x x xx x x x

high byte low byte

displays a binary value in the range 1 ... 64

4x + 5 The Routing 2 register





MSTR Function Error CodesIf an error occurs during the executionof an MSTR function, a hexadecimal er-ror code is displayed in register 4x + 1of the MSTR control block.

The form of the code is Mmss, where:

M is the major code

m is the minor code

ss is a subcode

Hex Error Code Meaning

1001 User-initiated abort

2001 Invalid operation type

2002 User parameter changed

2003 Invalid length

2004 Invalid offset

2005 Invalid length + offset

2006 Invalid slave device data area

2007 Invalid slave device network area

2008 Invalid slave device network routing

2009 Route = your own address

200A Attempting to acquire more global data words than are available

30ss Modbus slave exception response

4001 Inconsistent Modbus slave response

wheress = 01 = Slave device does not support the requested functionss = 02 = Nonexistent slave device registers requestedss = 03 = Invalid data value requestedss = 04 = Unassignedss = 05 = Slave has accepted long-duration program commandss = 06 = Function cannot be performed now—a long-duration command is in effectss = 07 ... 255 = Unassigned

5001 Inconsistent network response

6mss Routing failurewhere the m subfield is an index into the routing information, indicating wherewhere an error has been detected. A value of 0 indicates the local node, avalue of 2 indicates the second device on the route, etc.

And where

ss = 01 = No response receivedss = 02 = Program access deniedss = 03 = Node offline and unable to communicatess = 04 = Exception response receivedss = 05 = Router node data path busyss = 06 = Slave device downss = 07 = Bad destination addressss = 08 = Invalid node type in the routing pathss = 10 = Slave has rejected the commandss = 20 = Initiated transaction forgotten by the slave devicess = 40 = Unexpected master output path receivedss = 80 = Unexpected response received

0007 Slave has rejected long-duration program command

200B Peer cop change on read/write global data

200C Bad pattern for change of address request

200D Bad address for change of address request

F001 Selected option is not present


Read and Write MSTR FunctionsAn MSTR write function transfers datafrom a master source device to a speci-fied slave destination device on theModbus Plus network.

An MSTR read function transfers datafrom a specified slave source device onthe network to the master destinationdevice.

Read and write functions use one datamaster transaction path and may becompleted over multiple scans.

The nine registers in the top node of theMSTR instruction contain the followinginformation when you implement a read/write function.

Control Block Utilization

Register MSTR Function Register Content

4x Operation type 1 = write, 2 = read

4x + 1 Error status A hex value representing an MSTR error where relevant, asshown on previous page

4x + 2 Length Write = # of registers to be sent to a slaveRead = # of registers to be read from a slave

4x + 3 Slave devicedata area

Specifies first register in the slave to be read or written(1 = 40001, 49 = 40049, etc.)

4x + 4, + 5,+6, +7, +8

Routing 1, 2, 3,4, 5, respectively

Specifies the first through the fifth routing path addresses, respectively.The last nonzero byte in the routing path is the destination device

Note If you attempt to programan MSTR instruction to read orwrite its own address, an error willbe generated in the second regis-ter of the control block.

Note It is possible to attempt aread/write operation with a nonex-istent register in a slave device.The slave will detect this conditionand report it as an error, but itmay take multiple scans to detectit.

Note For a full discussion ofModbus Plus routing path struc-tures, refer to Modbus Plus Plan-ning and Installation Guide(GM-MBPL-001).

Get Local StatisticsThe MSTR get local statistics functionobtains operational information relatedto the local node—i.e., the controllerwhere the MSTR instruction has beenprogrammed.

This function does not require a datamaster transaction path, and it takesone scan to complete.

The first four registers in the MSTRcontrol block are used with this function.




4x Operation type 3

4x + 1 Error status A hex value representing an MSTR error where relevant

4x + 2 LengthStarting from an offset, the # of words of statistics from thelocal processor’s statistics table. Must be > 0 < K as speci-fied in the bottom node of the instruction

4x + 3 OffsetA value relative to the first available word in the local proces-sor’s statistics table—if the offset = 1, the function obtainsstatistics starting with the second word of the table

Note The network statistics aregiven at the end of this chapter.

Clear Local StatisticsThe MSTR clear local statistics functionclears operational information related tothe local node—i.e., the controllerwhere the MSTR instruction has beenprogrammed.


The first two registers in the MSTR con-trol block are used with this function.



4x Operation type 4


Note The network statistics aregiven at the end of this chapter.

Write Global DataThe MSTR write global data functiontransfers data to the comm processor inthe current node so that it can be sentover the network when the nodes getsthe token. All nodes on the networkcan receive this data.


The first three registers in the MSTRcontrol block are used with this function.




4x Operation type 5


4x + 2 LengthSpecifies the # of registers from the data area to be sent tothe comm processor. Must be < 32 and must not exceed Kas specified in the bottom node of the instruction

Read Global DataThe MSTR read global data functiongets data from the comm processor inany node node on the local network linkthat is providing global data.

This function does not require a datamaster transaction path, and it may takemultiple scans to complete.




4x Operation type 6


4x + 2 LengthSpecifies the # of words of global data to be requested fromthe comm processor designated by the routing path 1 pa-rameter. Must be > 0 < 32 and must not exceed K as speci-fied in the bottom node of the instruction

4x + 3 Available wordsContains the # of words available from the requested node.automatically updated by the internal software.


Get Remote StatisticsThe MSTR get remote statistics functionobtains operational information relatedto remote nodes on the network.

This function does not require a datamaster transaction path, and it may takemultiple scans to complete.

The nine registers in the MSTR controlblock are used as shown below for thisfunction.

The remote comm processor always re-turns it complete statistics table when arequest is made, even if the request isfor less than the full table. The MSTRinstruction then copies only the amountof words you have requested to thedesignated registers.



4x Operation type 7


4x + 2 Length

Starting from an offset, the # of words of statistics from theremote node. Must be > 0 < the total number of statisticsavailable (54) and must not exceed the number of statisticwords available

4x + 3 OffsetA value relative to the first available word in the statisticstable—the value must not exceed the number of statisticwords available

4x + 4, + 5,+ 6, + 7, + 8



Clear Remote StatisticsThe MSTR clear remote statistics func-tion clears operational statistics relatedto a remote node from the data area ofthe local node.

This function uses one data mastertransaction path, and it may take multi-ple scans to complete.

Seven of the registers in the MSTRcontrol block are used for this function:



4x Operation type 8


4x + 4, + 5,+ 6, + 7, + 8



Note For a full discussion ofModbus Plus routing path struc-tures, refer to Modbus PlusPlanning and Installation Guide(GM-MBPL-001).


Read Peer Cop Communication HealthThe MSTR read peer cop communica-tion health function loads a specifiedsubset of the peer cop communicationhealth table into 4x registers in the con-troller’s state RAM. This table com-prises 12 words.




4x Operation type 9


4x + 2 # of words requested

4x + 3 Starting word index

The range is 1 ... 12

The range is 0 ... 11

The Peer Cop Communication Health Table

The peer cop communication healthtable contains 12 words, word 0 ... word11, as shown below.

WordType of

Health Status for Nodes

0 Global inputs 1 ... 16




4 1 ... 16

5 17 ... 32

6 33 ... 48

7 49 ... 64

Specific outputs

Specific outputs

Specific outputs

Specific outputs

8 1 ... 16

9 17 ... 32

10 33 ... 48

11 49 ... 64

Specific inputs

Specific inputs

Specific inputs

Specific inputs

The most significant bit of word 0 givesthe health of the global input communi-cation expected from node 16. Theleast significant bit on word 0 gives thehealth of the global input communica-tion expected from node 1. All words inthe table use this format.

The associated health bit is 0 for everynull peer cop entry. A health bit is setwhen the node accepts inputs for theassociated peer copped input datagroup or when it hears that anothernode has accepted specific output datafrom the associated peer copped outputdata group at this node. A peer cophealth bit is cleared when no communi-cation has occurred for the associateddata group within the configured peercop health timeout period.

All health bits are cleared when aSTART PLC command is executed.The specific input and global inputhealth words are not valid until at leastone full token rotation cycle has com-pleted. The peer cop health bits are al-ways valid when this peer node is not inthe normal token operation state.

During the first few scans that thespecific output health bits are declaredinvalid, the controller sets all specificoutput health bits. Upon initial start-upof the controller, all nodes peer coppedwith specific outputs have their asso-ciated health bits set to 1, meaning


healthy. This start-up condition enablesyou to create ladder logic that comparesthe health bits without having to createspecial conditions during start-up, whichwould be the case if the values of thehealth bits were unknown.


Network StatisticsYou can acquire the following networkstatistics by using the appropriateMSTR function or by using Modbusfunction code 8.

Note When you use a clear localstatistics or clear remote statisticsfunction, only words 13 ... 22 arecleared.

Modbus Plus Network Statistics

Word Byte Meaning

00 Node type I.D. :0 Unknown node type1 Standard programmable controller node2 Bridge MUX3 Host4 Bridge Plus5 Peer I/O

01 Comm processor version (the first release was 1.00 and was displayedas 0100 hex)

02 Network address for this station

03 MAC state variable :0 Power-up state1 Monitor offline state2 Duplicate offline state3 Idle state4 Use token state5 Work response state

6 Pass token state7 Solicit response state8 Check pass state9 Claim token state10 Claim response state

04 Peer status (LED code); provides the status of the unit relative to the network :0 Monitor link operation32 Normal link operation64 Never getting token96 Sole station128 Duplicate station

05 Token pass counter; increments each time the station gets the token

06 Token rotation time in ms

07 Data master failed during token ownership bit mapProgram master failed during token ownership bit map

LOHI

08 Data master token owner work bit mapProgram master token owner work bit map

LOHI

09 Data slave token owner work bit mapProgram slave token owner work bit map

LOHI

10 Data master/get master response transfer request bit mapData slave/get slave command transfer request bit map

LOHI

11 Program master/get master response transfer request bit mapProgram slave/get slave command transfer request bit map

LOHI

12 Program master connect status bit mapProgram slave automatic logout request bit map

LOHI


Modbus Plus Network Statistics (continued)

Word Byte Meaning

13 Pretransmit deferral error counterReceive buffer DMA overrun error counter

LOHI

14 Repeated command received counterNo try counter (nonexistent station)

LOHI

15 Cable A framing errorCable B framing error

LOHI

16 UART errorBad packet-length error counter

LOHI

17 Bad link address error counterTransmit buffer DMA-underrun error counter

LOHI

18 Bad internal packet length error counterBad MAC function code error counter

LOHI

19 Communication retry counterCommunication failed error counter

LOHI

20 Good receive packet success counterNo response received error counter

LOHI

21 Exception response received error counterUnexpected path error counter

LOHI

22 Unexpected response error counterForgotten transaction error counter

LOHI

23 Active station table bit map, nodes 1 ... 8Active station table bit map, nodes 9 ... 16

LOHI


LOHI


LOHI


LOHI

27 Token station table bit map, nodes 1 ... 8Token station table bit map, nodes 9 ... 16

LOHI


LOHI


LOHI


LOHI

31 Global data present table bit map, nodes 1 ... 8Global data present table bit map, nodes 9 ... 16

LOHI


LOHI


LOHI


LOHI

35 Receive buffer in use bit map, nodes 1 ... 8Receive buffer in use bit map, nodes 9 ... 16

LOHI

36 Receive buffer in use bit map, nodes 17 ... 24Receive buffer in use bit map, nodes 25 ... 32

LOHI

37 Receive buffer in use bit map, nodes 33 ... 40Station management command-processed initiation counter

LOHI


Modbus Plus Network Statistics (concluded)

Word Byte Meaning

38 Data master output path 1 command initiation counterData master output path 2 command initiation counter

LOHI

39 Data master output path 3 command initiation counterData master output path 4 command initiation counter

LOHI

40 LOHI

41 LOHI

42 LOHI

43 LOHI

44 LOHI

45 LOHI

46 LOHI

47 LOHI

48 LOHI

49 LOHI

50 LOHI

51 LOHI

52 LOHI

53 LOHI

Data master output path 7 command initiation counterData master output path 8 command initiation counter

Data master output path 5 command initiation counterData master output path 6 command initiation counter

Data slave input path 41 command processed counterData slave input path 42 command processed counter




Program master output path 81 command initiation counterProgram master output path 82 command initiation counter




Program slave input path C1 command processed counterProgram slave input path C2 command processed counter




GM-A120-LDR O71Other Standard Instructions

Chapter 9Other StandardInstructions

Skipping Networks

Checking the Controller’s Health Status

The Subroutine Instructions

Sweep Instructions

PREOther Standard Instructions72 GM-A120-LDR

Skipping NetworksThe SKP instruction allows you to skipa specified number of networks in a lad-der logic program.

When it is powered, the SKP operationis performed on every scan. The re-mainder of the network in which the in-struction appears counts as the first ofthe specified number of networks to beskipped; the CPU continues to skip net-works until the total number of networksskipped equals the number specified inthe instruction block or until a segmentboundary is reached. A SKP operationcannot cross a segment boundary.

A SKP instruction can be activated onlyif you specify in the controller set-upeditor that skips are allowed.

Warning If inputs and out-puts that normally effect con-trol are unintentionallyskipped (or not skipped), theresult can create hazardousconditions for personnel andapplication equipment.

SKP is a one-high nodal instruction.


Nodes Outputs

(O)

FunctionStructure

Skip logicnetworks I 3x, 4x,

or K*

SKPTop:ON activatesthe skip function

Top:Specifies the num-ber of logic net-works to beskipped

Bypasses networksof ladder logic in theprogram and doesnot solve skippedlogic

*K is an integer constant in the range 1 ... 255

A Simple SKP ExampleWhen contact 10001 is closed, the re-mainder of network 06 and all of net-work 07 are skipped. Power flow in theskipped networks is invalid. Coil 00001is still controlled by contact 10003 be-cause it is solved before the SKP.

0000110003

10001

SKP2

0000210003

Network 06

Network 07


Checking Compact Health StatusThe Compact Controllers maintain atable in memory that contains vital sys-tem diagnostic information regarding theCPU, I/O, and communications. Thistable is 56 words long, and its contentsare structured as follows:

StatusWord

Content ofStatus Register

1 ... 11 Controller status information

12 ... 15 Health of A120 I/O modules

182 ... 184 Global health and communicationsretry status

16 ... 181 Not used

Each status word is 16 bits long, andthe status information is conveyed bythe sense of the bits in each word. Theillustrations on the following pages showhow the status information is presentedin the status table.

The words in the status table can beaccessed in ladder logic using the STATinstruction. The STAT block displaysthe bit patterns of the status words in atable of contiguous 4x registers, the val-ues of which can then be seen in thepanel software.

Note Although you are allowedto specify either a 0x or 4x regis-

ter in the top node, we recom-mend that you specify a 4x be-cause of the excessive number of0x registers that would be requiredto manage the status information.

The register you specify in the top nodeof the block is loaded with the currentword 1 bit values, and as many regis-ters as you specify in the bottom nodewill be loaded with bit values from thecorresponding words in the status table.

For example, if you are interested onlyin accessing controller status informa-tion, you could specify a register ad-dress of, say, 40701 in the top node ofthe block and a value of 11 in the bot-tom node—the bit values of the first 11words in the status table will be loadedinto registers 40701 ... 40711, respec-tively.

If you want to load the whole statustable, specify 184 in the bottom node ofthe instruction. If you are not using ex-panded I/O, you need only specify 40 inthe bottom node to get all the relevantstatus information.

STAT is a two-high nodal instruction.


Nodes Outputs

(O)

FunctionStructure

I O0x or 4x

STATK*

Check CPU/I/O Status


Top:ON accessesthe status table

Top:operationcompleted

Top:First word inthe systemstatus table

Bottom:size of thestatus table

Gets status datafrom the statustable in systemmemory and dis-plays it in userregisters


The Compact Controller Status Table

Word 1 CPU Status

1 2 3 54 6 7 8 9 10 11 1312 14 15 16

If the bit is set to 1, the condition is TRUE

Constant Sweep enabled

Single Sweep enabled

1 = 16-bit user logic

RUN light OFF

Battery failed

Word 2 is not used

Word 3 Controller Status

1 2 3 54 6 7 8 9 10 11 12 14 161513

Single sweepsScan time has exceeded constant scan target

START command pending

First scan


AC power ON

Memory protect OFF

Exit dim awareness

Word 5 CPU Stop State Conditions

1 2 3 54 6 7 8 9 10 11 1312 14 15 16


Bad PLC setup

Coil disabled in RUN mode

Logic checksum error

Invalid node in ladder logic

CPU failure

Real time clock error

Watchdog timer has expired

State RAM test has failed

No start-of-network (SON) at the start of a segment

Invalid segment scheduler

Illegal peripheral intervention

Peripheral port stop

No end-of-logic (EOL)

Dim awareness

Word 4 is not used


The Compact Controller Status Table (continued)

Word 6 Segments in Program

8 11 1312 14 1615

Word 7 End-0f-Logic Pointer

Word 8 is used only with the 984-145; it provides memory sizing information to the programming panel.

Word 9 is not used

Word 10 RUN/LOAD/DEBUG Status

1 2 3 54 6 7 8 9 10 11 1312 14 1615

0 00 11 0

DEBUG =RUN =LOAD =

Word 11 is not used

1 2 3 54 6 7 9 10

Number of segments in the current ladder logic program

Address of the EOL pointer

8 11 1312 14 16151 2 3 54 6 7 9 10

Word 12 Rack 1Word 13 Rack 2Word 14 Rack 3Word 15 Rack 4

1 2 3 54 6 7 8 9 10 11 1312 14 15 16

Slot 2

Slot 1

Slot 5Slot 4

Slot 3

Words 12 ... 15 are used to display the health of the A120 I/O modules in the four racks:

Each word contains the health status of up to five A120 I/O modules. The most significant (leftmost) bitrepresents the health of the module in slot 1 of the rack:

If an I/O module is traffic copped and ACTIVE, the bit will have a value of 1. If the module is inactive ornot traffic copped, the bit will have a value of 0.

Slots 1 and 2 in rack 1 (word 12) are not used because the controller itself uses those two slots.

Words 16 ... 181 are not used


The Compact Controller Status Table (concluded)

1 2 3 54 6 7 8 9 10 11 1312 14 1615

The last three words describe health and communications on the installed A120 I/O modules

Unhealthy module counter

Word 182 Systemwide I/O Health Status

1 = All I/O modules are healthy

Bits 9 ... 16 are used as a counter that increments each time an unhealthy module is encountered. The counterrolls over at a count of 255.

1 2 3 54 6 7 8 9 10 11 1312 14 1615

Counts the number of scans inwhich a module stays unhealthy

Word 183 I/O Error Count

Bits 1 ... 16 are used as a counter that increments once on each logic scan while an I/O module is unhealthy.

Counts the number of consecutivecommunication retries on the PAB

Word 184 PAB Bus Retry Count

Normally, all bits in this word should be 0s. Bits 1 ... 16 are used as a counter that increments once each time acomm retry occurs. If after five retries a bus error is still detected, the controller stops and displays error code10 on the programming panel.

1 2 3 54 6 7 8 9 10 11 1312 14 1615


The Subroutine InstructionsSubroutine logic can be initiated by aprogram-based instruction (JSR) in thecontrol logic. When a subroutine is initi-ated, the logic scan jumps to an instruc-tion in the last segment called LAB.This instruction labels the beginning ofthat subroutine’s logic. When the logicscan reaches an instruction in the sub-

routine called RET, it jumps out of thatsubroutine and returns to its previousposition in the control logic.

Subroutine logic is always kept in thelast segment of the ladder logic pro-gram. No other logic except the sub-routine logic is stored there.


Nodes Outputs

(O)

FunctionStructure

I O4x orK*

JSR00001

Jump to asubroutine

Top:ON enables thesource subroutine


Top:A constant or reg-ister value that in-dicates the de-sired subroutine

Bottom:Always a con-stant value of 1

O Bottom:ON if an erroris detected

Causes the logic scanto jump to a specifiedsubroutine in the last(unscheduled) seg-ment of user logic

Label thesubroutine I O

K*LAB

Top:ON activatesthe specifiedsubroutine

Top:A unique constantvalue that identi-fies the selectedsubroutine

Top:ON if an erroris detected

Marks the startingpoint of the sub-routine in the userlogic segment

Return toladder logic I O

00001RET

Top:ON initiates thereturn out of thesubfunction

Top:Always a con-stant value of 1

Top:ON if an erroris detected

Returns the logicscan to the nodeimmediately follow-ing the placewhere the subrou-tine was entered



Below is a conceptual illustration of howa subroutine is called from ladder logic.When the logic scan in segment 1 en-counters an enabled JSR instruction, itjumps to the indicated subroutine insegment 2. Only the logic associatedwith the called subroutine is scanned in

segment 2—all other subroutine logic isignored.

When the logic scan encounters a RETinstruction in the subroutine logic, itjumps back to the node immediately fol-lowing the JSR instruction in segment 1.

SEGMENT 1

Network 1

Network 2

Network 3

10001

00002JSR00001

Network 2

LAB00002

Network 1

LAB00001

RET00001

Network 3

SEGMENT 2

Logic forsubroutine #1

RET00001

Logic forsubroutine #2


Sweep InstructionsSweep functions allow you to scan logicat fixed intervals—they do not make thecontroller solve logic faster or terminatescans prematurely. Sweeps may beconstant or predetermined over somefixed number of scans—i.e., singlesweeps.

Constant sweep allows you to targetyour scan times from 10 ... 200 ms (inmultiples of 10 ms). A target scan timeis the time that elapses between thestart of one scan and the start of thenext. If a constant sweep is invokedwith a time lapse smaller than the ac-tual scan time, the sweep time is ig-nored and the system uses its normalscan rate.

The target scan time in a constantsweep encompasses logic solve time,I/O and Modbus port servicing, and sys-tem diagnostics. If you set a constantsweep target scan at 40 ms and the ac-tual logic solve, port servicing, and diag-nostics require only 30 ms, the control-ler will wait for 10 ms at the end of eachscan before continuing to the next.

Single sweep functions allow your con-troller to execute a fixed number ofscans—from 1 ... 15—and then to stopsolving logic but continue servicing I/O.This function is useful for diagnosticwork. It allows solved logic, moveddata, and completed calculations to beexamined for errors.

Warning Single sweepsshould not be used to debugcontrols on machine tools,processes, or material handl-ing systems once they havebecome active. Once the spe-cified number of scans hasbeen solved, all the outputsare frozen in their last state;since no logic solving takesplace, the controller ignoresall input information. This canresult in unsafe, hazardous,and destructive operation ofthe tools or processes con-nected to the controller.

Consult your programming documenta-tion for procedures to invoke sweep in-structions.

GM-A120-LDR 81Enhanced Instructions

Chapter 10Enhanced Instructions

Block↔Table Move Instructions

The Checksum Instruction

The Proportional-Integral-Derivative Instruction

Extended Math Instructions

PREEnhanced Instructions82 GM-A120-LDR

Block↔Table Move Instructions


Nodes Outputs

(O)

FunctionStructure

I O4x

BLKTK*

O

I

4x


Top:ON initiates themove

Top:ON when opera-tion is completed

Middle:Error detected—Move not possible

Top:First register inthe source block

Middle:pointer to the firstregister (4x + 1) inthe destinationtable

Bottom:size of the desti-nation table

I

I O4x

TBLKK*

O

I

4x


Top:First register inthe source table

Bottom:size of the desti-nation block

I

Block-to-tablemove

Table-to-blockmove

Top:ON initiates themove





Middle:pointer to the firstregister (4x + 1) inthe destinationblock

Middle:Error detected—Move not possible

Moves large quantitiesof 4x registers from afixed source block to adestination in a table

Moves a large numberof contiguous registersin a table to a fixed-destination block


The Checksum InstructionThe CKSM instruction is not offered aspart of the standard instruction set forthe 984-145 Controller. Instead, the

-145 contains MSTR, which is specificto the Modbus Plus functionality of thatcontroller.


Nodes Outputs

(O)

FunctionStructure

I O4x

CKSMK*

Checksum

O

I

4x


Top:ON calculates thesource table cksm

Bottom:Used with middleinput to determinecksm type

Top:ON when calcula-tion is completed

Middle:Error detected:register count = 0

orregister count >size of the sourcetable

Performs straightcheck, binary addi-tion check, CRC-16check, or LRC check,depending on stateof the middle andbottom inputs (seetable below)

Top:First register inthe source table

Middle:First of two regis-ters containingthe result and theimplied registercount

Bottom:size of the sourcetable

CKSM Input Usage

CKSM Calculation

Straight check

I

Middle:Used with bottominput to determinecksm type

Middle Input Bottom Input

OFF ON

Binary addition ON ON

CRC-16 ON OFF

LRC OFF OFF


The Proportional-Integral-DerivativeInstruction


Nodes Outputs

(O)

FunctionStructure

I O4x

PID2K*

Proportional-Integral-Deriviative O

I

4x

* K is an integer constant in the range 1 ... 255

Top:0 = Manual Mode1 = Auto Mode

Bottom:0 = output in-

creases as E**increases

1 = output de-creases as E**increases

Top:invalid parameter

orloop active but notbeing solved

Middle:PV > low alarmlimit***

Implements an algo-rithm that performsthe specified P, PI, orPID operation, as de-fined in registers4x + 5, 4x + 6,4x + 7, and 4x + 8 ofthe source table

Top:First of 21 regis-ters in the sourcetable

Middle:First of 9 registersused by the blockfor calculations

Bottom:constant repre-senting the inter-val at which thecalculation is per-formed in tenths ofa second

I

Middle:0 = Tracking ON1 = Tracking OFF

O

Bottom:PV > low alarmlimit***

** E is error expressed in raw analog units*** PV is the process variable

BlockFunction

Source Table Register Value

4x + 5 4x + 6 4x + 7 4x + 8

P non-zero non-zerozero zero

PI non-zero zeronon-zero zero

PI non-zero non-zero zeronon-zero

PID2 Source Table (Top Node)

Register Number Register Content

4x

Scaled PV: loaded by the block each time it is scanned; a linear scaling is done on register 4x + 13using the high and low ranges in 4x + 11 and 4x +12:

scaled PV =reg 4x + 13

4095x (reg 4x + 11 -- reg 4x + 12) + reg 4x + 12

Truncate the result at the decimal point and discard all digits to the right of the decimal point—do notround off the result.

4x + 1 SP: the set point specified in engineering units; its value must be > 4x + 11 > 4x + 12

4x + 2Mv: loaded by the block every time the loop is solved; it is clamped to the range 0 ... 4095, makingthe output compatible with an analog output; the manipulated variable register may be used forfurhter CPU calculations such as cascaded loops

4x + 3 High alarm limit: load a value into this register to specify a high alarm for PV (at or above SP); enterthe value in engineering units within the range specified in registers 4x + 11 and 4x + 12

4x + 4 Low alarm limit: load a value into this register to specify a low alarm for PV (at or below SP); enterthe value in engineering units within the range specified in registers 4x + 11 and 4x + 12

4x + 5Proportional band: load this register with the desired proportional constant in the range 5 ... 500;the smaller the number, the larger the proportional contribution; a valid number is required in thisregister for PID2 to operate


Proportional-Integral-Derivative Instruction (continued)

PID2 Source Table (Top Node)


4x + 6

4x + 7

4x + 8

4x + 9

Reset time constant: load this register to add integral action to the calculation; the value is aninteger constant in the range 0000 ... 9999, representing a range of 00.00 ... 99.99 repetitionsper minute—values <9999 or >0000 stop the PID2 calculation; the larger the number, the largerthe integral contribution

Rate time constant: load this register to add derivative action to the calculation; the value is aninteger constant in the range 0000 ... 9999, representing a range of 00.00 ... 99.99 repetitionsper minute—values <9999 or >0000 stop the PID2 calculation; the larger the number, the largerthe derivative contribution

Bias: load this register to add a bias to the output—the value, which is added directly to Mv, must bebetween 0000 ... 4095

High integral wind-up limit: load this register with the upper limit of the output value (between0 ... 4095) where the anti-reset wind-up takes place; if the specified value (normally 4095) isexceeded, the integral sum is no longer updated

4x + 10 Low integral wind-up limit: load this register with the lower limit of the output value (between0 ... 4095) where the anti-reset wind-up takes place—the specified value is normally 0

4x + 11High engineering range: load this register with the highest value for which the measurementdevice is spanned—e.g., if a resistance temperature device ranges from 0 ... 500 degrees C,the high engineering range value is 500; the high range value must be specified as a positiveinteger between 0001 ... 9999, corresponding to a raw analog input value of 4095

4x + 12Low engineering range: load this register with the lowest value for which the measurementdevice is spanned; the low range value must be specified as a positive integer between0001 ... 9998, corresponding to a raw analog input value of 0—it must be less than the valuespecified in register 4x + 11

4x + 13 Raw analog measurement: the logic program loads this register with PV; the measurementmust be scaled and linear in the range 0 ... 4095

4x + 14

Pointer to loop counter register: the value you load in this register points to the register thatcounts the number of loops solved in each scan; the value entered in the register is the refer-ence number of the register where the loop count is kept—e.g., if register 41236 keeps thecount, enter the value 1236 in register 4x + 14 of the PID2 source table; the same value mustbe loaded to the 4x + 14 register in the source table of every PID2 block in a logic program

4x + 15 Maximum number of loops/scan: if register 4x = 14 contains a non-zero value, you may load avalue into this register to specify the limit on the number of loops to be solved in a single scan

4x + 16

Pointer to reset feedback input: the value you load in this register points to the holding registerthat contains the feedback value (F); integration calculations rely on the F value being connectedto Mv—as the PID2 output varies from 0 ... 4095, so should F vary from 0 ... 4095; the valueentered in the register is the feedback register reference number—e.g., if the feedback register is42250, enter the value 2250 in register 4x + 16 of the PID2 source table

4x + 17 Output clamp high: the value entered in this register determines the upper limit of Mv (normally 4095)

4x + 18 Output clamp low: the value entered in this register determines the lower limit of Mv (normally 0)

4x + 19RGL constant: the rate gain limit value entered in this register determines the effective degree ofderivative filtering; the range for this value is from 2 ... 30; the smaller the value, the more filteringtakes place

4x + 20

Pointer to track input: the value entered in this register points to the holding register containing thetrack input (T) value; the T value is connected to the input of the integral lag whenever the auto bitand track bit are both TRUE; the value entered in this register is the track input register referencenumber—e.g., if the track input register is 40956, enter 0956 in register 4x + 20 in the PID2 sourcetable



PID2 Calculation Block (Middle Node)


4x Loop status register

1 2 3 54 6 7 8 9 10 11 1312 14 15 16

see note

Man/Auto statusof top input

Tracking ON/OFFstatus of middle input

Output increase/decreasestatus of bottom input

Negative values inthe equation

Integral wind-up limit exceeded

Top output ON

Middle output ON

Bottom output ON

Loop in Auto Mode and time since last solution > solution interval

Always set to 1

Loop in Auto Mode but not being solved

0 = +E in source register 4x + 61 = --E in source register 4x + 6

Referencing of 4x + 14 by 4x + 15 is valid

In Wind-down Mode

Note: Bit 16 is set after initial start-up or installation of the loop. If the bit is cleared, thefollowing actions all take place in one scan:

The loop status register is rest

The current value in the real-time clock is stored in register 4x + 1 in thisblock

Registers 4x + 3, 4x + 4, and 4x + 5 in this block are set to zero

The value in source table register 4x + 13 is multiplied by 8 and stored inregister 4x + 6 of this block

Register 4x + 7 and 4x + 8 in this block are cleared





4x + 1 Error (E) status

BitCode Meaning

Check This Register in theSource Table (Top Node)

0000 No errors, all validations OK

0001 Scaled SP above 9999 4x + 1

0002 High alarm above 9999 4x + 3

0003 Low alarm above 9999 4x + 4

0004 Proportional band below 5 4x + 5

0005 Proportional band above 500

4x + 60006 Reset above 99.99 repeats/min

4x + 70007 Rate above 99.99 min

4x + 80008 Bias above 4095

4x + 90009 High integral limit above 4095

4x + 100010 Low integral limit above 4095

4x + 11

4x + 5

0011 High engineering unit scale above 9999

4x + 120012 Low engineering unit scale above 9999

4x + 11 and 4x + 120013 High engineering unit scale below low engineering unit

4x + 1 and 4x + 110014 Scaled SP above high engineering unit

4x + 1 and 4x + 110015 Scaled SP below low engineering unit

(4x + 15 = 0)0016 Loops/scan > 9999

4x + 160017 Reset feedback pointer out of range

4x + 170018 High output clamp above 4095

4x + 180019 Low output clamp above 4095

4x + 17 and 4x + 180020 Low output clamp above high output clamp

4x + 190021 RGL below 2

4x + 190022 RGL above 30

4x + 20 and middle input ON0023 Track F pointer out of range

4x + 20 and middle input ON0024 Track F pointer is zero

see note below0025 Node locked out (short of scan time)

4x + 14 and 4x + 150026 Loop counter pointer is zero

0024 4x + 14 and 4x + 15Loop counter pointer out of range

Note: If lockout occurs often and all the parameters are valid, increase the maximum allowablenumber of loops/scan. Lockout may also occur if the counting registers in use are not clearedas required.

4x + 2Loop timer register: stores the real-time clock reading on the system clock each time the loopis solved; the difference between the current clock value and the value stored in this register isthe elapsed time; if elapsed time > the solution interval (10 times the value given in the bottomnode of the PID2 block), the loop should be solved in the current scan

4x + 34x + 44x + 5

Reserved for internal use


Proportional-Integral-Derivative Instruction (concluded)



4x + 6Pv x 8 (filtered): stores the result of the filtered analog input (from source register 4x + 14)multiplied by eight; this value is useful in derivative control operations

Reserved for internal use4x + 8

4x + 7Absolute value of E: contains the absolute value of SP -- PV; bit 8 in register 4x + 1 ofthis block indicates the sign of E; the value in this register is updated after each loopsolution


Extended Math Instructions


Nodes Outputs

(O)

FunctionStructure

I O4x

EMTH

Doubleprecision(32-bit)addition

O4x

Top:ON initiates thedouble precisionaddition


Middle:an operand isinvalid or out ofrange

Adds operand 1 (thevalue in the top noderegister block) andoperand 2 (the valuein the first two regis-ters of the middlenode block), thenplaces the result inthe fourth and fifthregisters of themiddle node block

Top:First of two con-tiguous registerscontaining oper-and 1—its valueis in the range0 ... 99,999,999

Middle:First of six regis-ters in the blockdescribed below

Bottom:appropriate EMTHfunction code

1

Middle Node Block


4x and 4x + 1 the value of operand 2, in the range 0 ... 99,999,999

a non-zero value indicates that an overflow condition exists4x + 2

4x + 3 and 4x + 4 the result of the double precision addition

4x + 5 not used but must be configured


Extended Math Instructions (continued)


Nodes Outputs

(O)

FunctionStructure

Doubleprecision(32-bit)subtraction

Top:ON initiates thedouble precisionsubtraction


Middle:operand = operand

1 2

Subtracts operand 2(the value in the firstand second registersin the middle nodeblock) from operand1 (the value in thetop node block), thenplaces the result inthe third and fourthregisters of themiddle node block




I O4x

EMTH

O4x

O2

Bottom:operand < operand

1 2

Middle Node Block



non-zero value indicates that an out-of-range condition exists

4x + 2 and 4x + 3

4x + 4

the result of the double precision subtraction

4x + 5 not used but must be configured

Doubleprecisionmultiplication

Top:ON initiates thedouble precisionmultiplication


Top:First of two con-tiguous registerscontaining oper-and 1, whose val-ue is in the range0 ... 99,999,999



I O4x

EMTH

O4x

3

Middle:an operand isout of range

Multiplies operand 1(the value in the topnode register block)by operand 2 (thevalue in the first tworegisters of themiddle node block),then places the re-sult in the third,fourth, fifth, and sixthregisters of themiddle node block

Middle Node Block



4x + 2, 4x + 3,

4x + 4, and 4x + 5the result of the double precision multiplication




Nodes Outputs

(O)

FunctionStructure

Doubleprecisiondivision

Top:ON initiates thedouble precisiondivision





I O4x

EMTH

O4x

O4

Bottom:operand 2 = 0

Middle Node Block



4x + 2 and 4x + 3

4x + 4 and 4x + 5

the result (quotient) of the double precision division

Square root

Top:ON initiates the

√


Top:First of two regis-ters containing asource value inthe range0 ... 99,999,999

Middle:First of two regis-ters where the re-sult is stored inthe fixed-decimalformat:1234.5600


I O3x or 4x

EMTH

O4x

5

Middle:source valueis out of range

Divides operand 1(the value in the topnode register block)by operand 2 (thefirst two registers inthe middle nodeblock), then placesthe result in thethird and fourth reg-isters of the middlenode block and theremainder in thefifth and sixth regis-ters of the middlenode block

I

Middle:ON = remainderis stored as afractionOFF = remainderis stored as awhole number

Middle:an operand isout of range

the remainder of the double precision division

operation

Processsquare root


√


Top:First of two regis-ters containing asource value inthe range0 ... 99,999,999

Middle:First of two regis-ters where thelinearized resultis stored


I O3x or 4x

EMTH

O4x

6

Middle:source valueis out of range

operation

Calculates thesquare root of thesource value in thetop node registersand stores the resultin the middle noderegisters

Calculates thesquare root of thesource value in thetop node registers,linearizes it by multi-plying it by 63.9922(the square root of4095), then storesthe linearized resultin the middle noderegisters

Process squareroots are often usedin PID2 operations





Nodes Outputs

(O)

FunctionStructure

Logarithm

Top:ON initiates alogarithmicoperation


Middle:A holding registerwhere the result isstored


I O

EMTH

O4x

7

Antilogarithm


Top:A single registerthat contains asource valuestored in thefixed decimal for-mat 1.234 and inthe range0 ... 7.999

Middle:First of two con-tiguous registerswhere the result isstored


I O3x or 4x

EMTH

O4x

8

Performs a base 10logarithmic opera-tion on the value inthe source registersin the top node,then stores theresult in the middle-node register

Middle:an error hasbeen detectedor a value isout of range

Integer-to-floating pointconversion

Top:ON initiates theconversion


Top:First of two con-tiguous registerscontaining a dou-ble-precisioninteger sourcevalue

Middle:First in a block offour contiguousholding registers

I O

EMTH

4x

9

Converts a double-precision integervalue into a 32-bitfloating point valueand stores the resultin the third andfourth registers ofthe middle-nodeblock

The first two regis-ters in the block arenot used*

3x or 4x

Top:First of two con-tiguous registerscontaining asource value inthe range0 ... 99,999,999

Top:ON initiates alogarithmicoperation

Middle:an error has beendetected or a val-ue is out of range

Performs a base 10antilogarithmic op-eration on the valuein the source regis-ter and stores theresult in the middle-node registers inthe fixed-decimalformat:

12345678

4x

Integer + floatingpoint addition

Top:ON initiatesthe addition


Top:First of two con-tiguous registerscontaining a dou-ble-precisioninteger value



I O

EMTH

4x

10

4x Adds the double-precision integer val-ue in the top- noderegister block andthe FP value in thefirst two registers inthe middle-nodeblock then stores theresult in the thirdand fourth registersof the middle-nodeblock

* Note If you want to preserve registers, you may store the double-precisioninteger value in the first and second registers of the middle-node block andnot configure a top-node register block in the EMTH 9 instruction.




Nodes Outputs

(O)

FunctionStructure



I O

EMTH

4x

11



I O3x or 4x

EMTH

4x

12



I O

EMTH

4x

13

3x or 4x

4x

Integer -- floatingpoint subtraction

Top:First of two con-tiguous registerscontaining afloating pointvalue



I O

EMTH

4x

14

4x

Subtracts the FPvalue in the first tworegisters of themiddle-node blockfrom the integer val-ue in the top-noderegister block thenstores the result inthe third and fourthregisters of themiddle-node block

Integer x floatingpointmultiplication

Integer/floatingpoint division

Top:ON initiates thesubtraction

Top:ON initiates themultiplication

Top:ON initiates thedivision


Top:First of two con-tiguous registerscontaining adouble-precisioninteger value




Middle:First in a block offour contiguousregisters

floating point --integersubtraction



Subtracts the dou-ble-precision integervalue in the first tworegisters of themiddle-node blockfrom the FP value inthe top-node registerblock, then storesthe result in the thirdand fourth registersof the middle-nodeblock

Multiplies thedouble-precisioninteger value in thetop-node registerblock by the FP val-ue in the first tworegisters of themiddle-node block,then stores theproduct in the thirdand fourth registersof the middle-nodeblock

Divides the double-precision integer val-ue in the top-noderegister block by theFP value in the firsttwo registers of themiddle-node block,then stores thequotient in the thirdand fourth registersof the middle-nodeblock




Nodes Outputs

(O)

FunctionStructure



I O

EMTH

4x

15



I O3x or 4x

EMTH

4x

16

3x or 4x

Top:First of two con-tiguous registerscontaining afloating pointvalue



I O

EMTH

4x

17

4x

Integer-floatingpointcomparison

Top:ON initiates thecomparison


Top:First of two con-tiguous registerscontaining a dou-ble-precision inte-ger value


floating point-to-integerconversion


Divides the double-precision integer val-ue in the first tworegisters of themiddle-node blockby the FP value inthe top-node registerblock, then storesthe quotient in thethird and fourth reg-isters of the middle-node block

Compares the dou-ble-precision inte-ger value with thefloating point value(in the first two reg-isters of the middle-node block), thenindicates the rela-tionship via themiddle and bottomoutputs (see tablebelow)

The third and fourthregisters in themiddle-node blockare not used butmust be configured

floating point/integer division


O

O

Middle:used with thebottom output toindicate the valuerelationship

Bottom:used with themiddle output toindicate the valuerelationship

EMTH 16 OutputsMiddle Output State Bottom Output State Value Relationship

ON OFF I > FP

OFF ON I < FP

ON ON I = FP

O

Top:First of two con-tiguous registerscontaining a dou-ble-precision inte-ger


Bottom:0 = + integer value1 = -- integer value

Converts the FP val-ue stored in the thirdand fourth registersof the middle-nodeblock into a double-precision integer val-ue and stores theconverted value inthe top-noderegisters

The first and secondregisters in themiddle node are notused but must beconfigured*





Nodes Outputs

(O)

FunctionStructure



I O

EMTH

4x

18



I O

EMTH

4x

19


I O

EMTH

4x

20

4x

floating pointaddition


I O

EMTH

4x

21

4x

Adds FP value 1 (inthe top-node regis-ter block) and FPvalue 2 (from thefirst two registers ofthe middle-nodeblock), then storesthe sum in the thirdand fourth registersof the middle-nodeblock


Top:ON initiates themultiplication



Top:First of two con-tiguous registerscontainingFP value 1Middle:First in a block offour contiguousholding registers



Subtracts FP value 2(stored in the first andsecond registers ofthe middle-nodeblock) from FP value1 (in the top-noderegister block), thenstores the differencein the third and fourthregisters of themiddle-node block

floating pointsubtraction

floating pointmultiplication

floating pointdivision

4x

4x

Top:First of two con-tiguous registerscontaining FPvalue 1



Divides FP value 1(in the top-node reg-ister block) by FPvalue 2 (stored in thefirst and second reg-isters of the middle-node block), thenstores the quotient inthe third and fourthregisters of themiddle-node block




Multiplies FP value 1(in the top-node reg-ister block) by FPvalue 2 (stored in thefirst and second reg-isters of the middle-node block), thenstores the product inthe third and fourthregisters of themiddle-node block




Performs a squareroot operation onthe FP value in thetop-node block andstores the result inthe third and fourthregisters of themiddle-node block.

The first and sec-ond registers in themiddle-node blockare not used butmust beconfigured*


ON FP value 1 = FP value 2


Nodes Outputs

(O)

FunctionStructure

Top:ON when compari-son is complete


I O

EMTH

4x

22

I O

EMTH

4x

23

4x

floating pointcomparison

Top:ON initiates thecomparison



floating pointsquare root


Compares FP value1 (in the top-noderegister block) andFP value 2 (in thefirst two registers ofthe middle-nodeblock), then indi-cates the relation-ship via the middleand bottom outputs(see table below)

The third and fourthregisters in themiddle node blockare not used butmust be configured

O

O

Middle:used with thebottom output toindicate the valuerelationship

Bottom:used with themiddle output toindicate the valuerelationship

EMTH 22 OutputsMiddle Output State Bottom Output State Value Relationship

ON OFF FP value 1 > FP value 2

OFF ON FP value 1 < FP value 2

ON

Top:First of two con-tiguous registerscontaining an FPvalueMiddle:First in a block offour contiguousholding registers

4x


√ operation


I O

EMTH

4x

24

4xfloating pointsign change


Top:First of two regis-ters containing anFP value


Top:ON initiates thesign changeoperation

Changes the sign ofthe FP value in thetop-node registerblock and stores theresult in the thirdand fourth registersof the middle-nodeblock.

The first and secondregisters of themiddle-node blockare not used

I O

EMTH

4x

25

floating point πloading

Top:ON when loadingis completed

Middle:First of four regis-ters where theFP value of pi isloaded

ON loads π intothe middle-register block

Loads the FP valueof pi into the thirdand fourth registersof the middle-nodeblock; the first andsecond registers ofthe middle-nodeblock are not used


Top: Top:Not used



Top:First of two con-tiguous registerscontaining the FPvalue of an anglein radians; themagnitude is< 65536.0

Top:ON initiates thecalculation



Nodes Outputs

(O)

FunctionStructure



I O

EMTH

4x

26



I O

EMTH

4x

27


I O

EMTH

4x

28

4x

floating pointsine of anangle

Calculates in radialsthe sine of the float-ing point value in thetop-node registersand stores the resultin the third and fourthregisters of themiddle-node block.





floating pointcosine of anangle

floating pointtangent of anangle

4x

4x



Calculates in radiansthe cosine of thefloating point value inthe top-node registersand stores the resultin the third and fourthregisters of themiddle-node block.


Calculates in radiansthe tangent of thefloating point valuein the top-node regis-ters and stores theresult in the third andfourth registers of themiddle-node block.


The first and secondregisters of themiddle-node blockare not used but mustbe configured.*








Top:First of two con-tiguous registerscontaining the FPvalue of the tan-gent of an anglebetween


Nodes Outputs

(O)

FunctionStructure


I O

EMTH

4x

31

4x

I O

EMTH

4x

30

4x





floating pointarctangent ofan angle

floating pointarc cosine ofan angle


Top:First of two reg-isters containingthe FP value ofthe cosine of anangle between0 ... π radians; inthe range of--1.0 ... +1.0

Calculates in radiansthe arc cosine of thefloating point valuein the top-node regis-ters and stores theresult in the third andfourth registers of themiddle-node block.

The first and secondregisters in themiddle-node blockare not used but mustbe configured*


--π/2 ... π/2radians

Calculates in radiansthe arctangent of thefloating point valuein the top-node regis-ters and stores theresult in the third andfourth registers of themiddle-node block.





The first and secondregisters of themiddle-node blockare not used but mustbe configured.*Bottom:

appropriate EMTHfunction code

I O

EMTH

4x

29

4x



floating pointarcsine of anangle


Top:First of two reg-isters containingthe FP value ofthe sine of anangle between--π / 2 ... π / 2radians; the valuemust be in therange --1.0 ... +1.0

Calculates in radiansthe arcsine of thefloating point valuein the top-node regis-ters and stores theresult in the third andfourth registers of themiddle-node block;.





Nodes Outputs

(O)

FunctionStructure

Top:ON when conver-sion is completed


I O

EMTH

4x

33



I O

EMTH

4x

34


I O

EMTH

4x

35

4x

floating pointdegree-to-radianconversion

Converts the FP val-ue in the top-noderegisters to an FPrepresentation of thatvalue in degrees, andstores the convertedvalue in the third andfourth registers of themiddle-node block.




Top:First of two con-tiguous registerscontaining the FPvalue of an anglein degrees



floating pointnumber raisedto an integerpower

4x

4x

Top:First of two regis-ters containing anFP value


Raises the FP valuein the top-node regis-ters to the integerpower specified in thesecond register of themiddle-node block,and stores the resultin the third and fourthregisters of themiddle-node block;the first register in themiddle node must beset to zero

floating pointexponential

Top:First of two con-tiguous registerscontaining an FPvalue in the range--87.34 ... +88.72


Calculates the expo-nential value of theFP number in thetop-node registersand stores the resultin the third and fourthregisters of themiddle-node block.

The first and secondregisters of themiddle-node blockare not used butmust be configured.*





floating pointradian-to-degreeconversion

I O

EMTH

4x

32

4x


Top:ON when conver-sion is completed

Top:First of two contig-uous registerscontaining the FPvalue of an anglein radians


Converts the FP val-ue in the top-noderegisters to an FP re-presentation of thatvalue in radians, andstores the conversionin the third and fourthregisters of themiddle-node block.



Extended Math Instructions (concluded)



Nodes Outputs

(O)

FunctionStructure


I O

EMTH

4x

37

4x


Top:ON when calcula-tion is completedfloating point

commonlogarithm

Top:First of two con-tiguous registerscontaining an FPvalue > 0


Calculates the com-mon logarithm of theFP number in thetop-node registersand stores the resultin the third and fourthregisters of themiddle-node block.

Error reportlog I O

EMTH

4x

38



O

Middle:1 = nonzeros in

the register0 = all bits set to

zero

Middle:First of four regis-ters that containthe error log data(see below)

Error data are loggedin the third register ofthe middle-nodeblock, and the fourthregister is always setto zero

The first and secondregisters in themiddle-node blockare not used, butmust be configured.

1 2 3 54 6 7 8 9 10 11 1312 14 15 16

FP underflow

FP overflow

Invalid FP valueor operation

Integer/FP conversion error

Register 4x + 2 in the Middle Node of EMTH 38

Exponential functionpower too large

Function code of last logged error




I O

EMTH

4x

36

4x


Top:ON when calcula-tion is completedfloating point

naturallogarithm

Top:First of two con-tiguous registerscontaining an FPvalue > 0


Calculates the natu-ral logarithm of theFP value in the top-node registers andstores the result inthe third and fourthregisters of themiddle-node block



Top:Not used

43503387_eng

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motor startstop

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