42

3624 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 9, SEPTEMBER 2012

Design Considerations for DSP-Controlled400 Hz Shunt Active Power Filter

in an Aircraft Power SystemHaibing Hu, Member, IEEE, Wei Shi, Ying Lu, and Yan Xing, Member, IEEE

Abstract—A multiresolution control strategy is proposed fora digital signal processor (DSP)-controlled 400 Hz active powerfilter (APF) to reduce the real-time computational requirements.By rearranging the computational elements into high- and low-frequency control groups, the proposed control strategy takesbest advantages of the DSP computation resources to increase thecontrol frequency for the high computational group, which mainlydetermines the APF performance. Based on bandwidth featuresof different control plants in APF, detailed analysis is given todetermine the control and sampling frequencies for these plants.Anti-aliasing filters are designed to avoid aliasing when down-sampling scheme is used to further reduce computation resource.A 20 kVA prototype is set up to verify the validity of the pro-posed strategy and analysis. Experimental results show that theproposed control strategy meets the computational requirementsfor the control system using a DSP. The proposed control strategyachieves the total harmonic distortion as low as 5.7%, which meetsthe avionic DO-160F standard, and also exhibits good dynamicperformance.

Index Terms—Active power filter (APF), aircraft power sys-tems, digital signal processor (DSP), multiresolution.

I. INTRODUCTION

IN TODAY’s aircraft industry, the concepts of “all-electricaircraft” and “more electric aircraft” have been introduced

to achieve better efficiency, lower cost, and better performance[1]–[8]. As a result, the number of electrical loads equipped on-board is increasing, and the onboard power capacity is gettinglarger. Unfortunately, most of the dc loads in airborne systemsare typically powered by the uncontrolled diode rectifier con-verters due to their high reliability, relatively high efficiency,and low cost, which in turn generate large amount of harmoniccurrents and poor power factor. The high harmonic current dis-tortion and poor power factor would be a major concern whenthe percentage of total system power processed by uncontrolledrectifiers is high. To address this problem, some standards suchas DO-160F and ISO-1540 have been revised to keep strictlimits on harmonic currents which user equipment can draw

Manuscript received August 1, 2010; revised March 23, 2011 and May 30,2011; accepted July 21, 2011. Date of publication August 18, 2011; date ofcurrent version April 13, 2012.

The authors are with the College of Automation, Nanjing University ofAeronautics and Astronautics, Nanjing 210016, China (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2165452

Fig. 1. Potential solutions. (a) Multiphase transformer rectifier. (b) Activepower filter. (c) PWM rectifier.

from the ac source [9]. The potential solutions to this powerquality problem are to employ some techniques such as powerfactor correction, multiphase (12- or 18-pulse) transformer-rectifier, and active power filter (APF) [6], [7], [10]–[19] asshown in Fig. 1. Reference [6] has made detailed comparisonsbetween PWM rectifier and 12-pulse auto-transformer based onpower density, losses, cost, and reliability. However, these twotechniques have to deal with all the power flow supplied to theload, resulting in high volume and heavy weight. APF com-pensates only the harmonics for the load and thus much lowercapacity and lighter weight can be achieved in comparison tothe above two techniques. Furthermore, the other benefit of theAPF is that it does not change the existing power stage anddegrade the reliability of the old ones as it can be switched offthe grid when faults in APF occur.

Extensive research has been conducted on APFs applied tothe 50 Hz or 60 Hz commercial power systems [20]–[26].Although the principle for APF applied to the commercialutility and to the aircraft power system is the same, there existsa great challenging in designing high performance 400 Hz APF

0278-0046/$26.00 © 2011 IEEE

HU et al.: DESIGN CONSIDERATIONS FOR DSP-CONTROLLED 400 Hz SHUNT ACTIVE POWER FILTER 3625

Fig. 2. Structure of APF.

due to its wider bandwidth and limited switching frequency.There have been few publications on 400 Hz APFs appliedto the aircraft power systems [10]–[17]. In [10], analysis andsimulation were given to illustrate the harmonic cancellationusing APF, and a hysteresis current controller was used to fasttrack the current reference; however, the paper did not giveany information about highest switching frequency and anycontrol delay issues, which are the main issues for 400 HzAPF’s performance. In [11], [12], a multilevel APF was pro-posed to reduce the switching frequency, which may lead tolow reliability due to the complicated control and power stage.In [13], a unified power quality conditioner was applied to the400 Hz single-phase microgrid based on modified PQ theory.In [14], [15], the detailed design procedures including controlissues and key power stage parameters were given.

Many researches have been conducted on fully digital-controlled APF for 50 Hz or 60 Hz applications [23]–[25].However, fully digital-controlled APF for 400 Hz applicationshas never been applied before according to reported literaturesas the control delay in a digital controller may lead to the greatdegradation of harmonics cancellation performance. To addressthis problem, a multiresolution control strategy is presentedin this paper to achieve the high current control bandwidthwith limited computation resources in DSP. High-frequencycontrol group and low-frequency control group are partitionedbased on their individual control plant bandwidth. Detailedanalysis is given to determine the control and the samplingfrequencies for different plants in APF. The paper is organizedas follows. The principle of the 400 Hz shunt APF is givenin Section II. Section III deals with the control delay effectson the current loop performance. A multiresolution controlstrategy is proposed to reduce the control delay in Section IV.Determining the sampling and control frequency for the low-frequency control group is analyzed in Section V. Simulationresults are presented in Section VI. Experimental results aregiven in Section VII with conclusions drawn in Section VIII.

II. PRINCIPLE OF SHUNT APF

As seen in Fig. 2, the control system consists of four mainfunctional blocks: 1) software phase-locked loop (PLL); 2) dcbus voltage regulator; 3) low-pass filter (LPF); and 4) currentcontrol loop. The measured load phase currents (iLa, iLb) aretransformed into the synchronous reference frame to obtainiLq and iLd. The synchronous reference frame phase anglecan be obtained by processing the measured system voltageswith software PLL algorithm. LPFs are employed to filterout the dc components in the synchronous reference frame,which represents the fundamental frequency components of theload currents. The harmonic components, (iLq, iLd), are easilyobtained by a simple subtraction of the filtered components(iLq, iLd) and the transformed components (iLq, iLd). Due tolosses in power devices and other components, a small amountof real power is consumed, which would result in dc voltagedecrease. To keep the dc voltage constant, dc voltage regulatoris used by adding dc regulating value ∆id to the d-axis filtercurrent. All these computations are implemented in a digitalsignal processor (DSP).

III. EFFECT OF CONTROL DELAY ON CURRENT LOOP

In a balanced three-phase system, the inverter model in thesynchronous reference frame can be described as[

Ldid

dt

Ldiq

dt

]=

[−R ωL−ωL −R

] [idiq

]−

[ud

uq

]+

[ed

eq

](1a)

Cdudc

dt=

3ed

udcid (1b)

[ ed eq eo ]T = C32[ ea eb ec ] (1c)

[ id iq io ]T = C32[ ica icb icc ] (1d)

[ud uq uo ]T = C32[ da db dc ]Udc (1e)

3626 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 9, SEPTEMBER 2012

Fig. 3. Diagram of the current loop with pure delay time Td.

whereL and R are the equivalent inductance and resistance of

the grid-tied inductor Lc;C is the dc bus capacitance;ω is the angular frequency of the grid;[id iq io] are the corresponding currents in the synchro-

nous reference frame;[ea eb ec] are the three-phase grid voltages;[ed eq eo] are the voltages in the synchronous reference

frame;[ica icb icc] are three-phase currents from APF;[da db dc] are control duty cycles of three phases;Udc is the dc bus voltage;[ud uq uo] are the voltages in synchronous reference

frame.C32 is the transformation matrix from the stationery

frame to the synchronous reference frame,which is given by

C32 =23

sin ωt sin

(ωt − 2π

3

)sin

(ωt − 4π

3

)cos ωt cos

(ωt − 2π

3

)cos

(ωt − 4π

3

)32

32

32

.

The inverter plant depicted in expression (1a) is a nonlinearand coupling system. With the feedforward and dc-couplingterms, the transfer functions of the current loop being controlledcan be linearized as

Gq_c = Gd_c(s) =1

R + Ls. (2)

Due to the computational delay in digital control system,a pure control delay is unavoidably introduced to the system,which has a negative effect on the control bandwidth. The delaytime Td depends on the current loop control strategy, whosetransfer function can be expressed as

Gdelay(s) = e−sTd . (3)

A P regulator, as shown in Fig. 3, is employed in the currentloop control, where Kp and Kpwm are proportional coefficientin current loop and PWM gain of the three-phase inverter,respectively. The parameters of the APF are listed in Table I.The bandwidth of the current loop will decide the compensatingeffect of the APF. To achieve a better compensating effect,the current bandwidth should be designed as wide as possiblewithin the region of system stability. For simplification, thecontroller was designed based on continuous linear systemwithout introducing the pure delay unit. In this application case,the cutoff frequency fc of the current open loop is designed at10 kHz, which is one-fifth of the switching frequency 50 kHz,and the phase margin is designed at 90 to make sure the currentloop has enough stability margin when introducing a pure delay

TABLE IKEY PARAMETERS OF THE 400 Hz SHUNT APF

Fig. 4. Relationship between phase delay and delay time.

unit. In a delay system, the decrease in phase margin can becalculated by the pure delay time Td, which translates to a phaselag as:

Phaselag = ωTd = 2πfcTd (4)

where, fc = 10 kHz is the cutoff frequency at which the phaselag can be calculated.

Fig. 4 shows the relationship between delay time and phasemargin decrease. It clearly shows that the current loop will fallin the unstable region when the delay time Td is greater than25 us. As aforementioned, the delay time Td depends on theDSP computation time and the duty cycle updating scheme.Many multisampling methods have been proposed to reducedelay time in the digital controller for PWM converters [18].However, all these methods are unavoidable to sample theswitching ripples, resulting in a degradation of the expecteddynamic response, and they also require more hardware re-sources and computational efforts. In this paper, two typical“synchronous sampling methods,” as shown in Fig. 5, werechosen to compare their effects on the harmonic compensation.Two schemes have Ts and Ts/2 delay time, respectively, whereTs is the switching period. The closed-current loop transferfunction can be expressed as

Gi_close =kpkpwme−Tds

R + Ls + kpkpwme−Tds. (5)

According to the closed-loop transfer function, we cancalculate the phase lag and amplitude for each harmonic asshown in Fig. 6. For an ideal closed-loop transfer function, thephase lag should be equal to 0 and the gain should be equalto unity within its control bandwidth. As seen in Fig. 6(a),

HU et al.: DESIGN CONSIDERATIONS FOR DSP-CONTROLLED 400 Hz SHUNT ACTIVE POWER FILTER 3627

Fig. 5. Two synchronous sampling schemes and their delay time. (a) Scheme 1.(b) Scheme 2.

Fig. 6. Comparison of control effect with different delays. (a) Phase delayversus harmonic order. (b) Closed-current loop gain versus harmonics order.

TABLE IISUMMARY OF COMPUTATIONAL ELEMENTS

AND THEIR EXECUTION TIME

due to the current limited bandwidth (10 kHz), the phase lagincreases as the harmonic order increases in all three cases(no delay, 10 us delay, and 20 us delay). Fig. 6(b) shows thegain changes as the harmonic order increases. The followingshould be noted. 1) In the 10 kHz bandwidth design, the phaselag performance of the case with no delay is better than thatwith 10 us delay; however, the gain performance of the casewith 10 us delay is better than that of no delay. 2) Due tolimited current bandwidth, the harmonic orders more than 15thwill be impossible to achieve the good compensating effect;however, these high-order harmonics can be easily filtered outusing small reactive filter installed at the source side. Basedon above analysis, we choose synchronous sampling scheme 2to implement the digital control. However, the computationamount in scheme 2 would be twice that in scheme 1, whichresults in high computation resources in DSP. In this paper, weadopted the multiresolution control strategy to reduce real-timecomputation requirements.

IV. MULTIRESOLUTION CONTROL STRATEGY

In this paper, all the computations are executed in theDSP, TMS320F2812, whose maximal operating frequency is150 MHz. The computational elements and their execution timeare listed in Table II.

As aforementioned in Section III, since the APF is designedto operate with 50 kHz switching frequency, the control fre-quency reaches up to 100 kHz when employing the “synchro-nous sampling” scheme 2. However, due to the computationlimitation in the DSP, all these computational elements as seenin Table II, whose total execution time is 11.7 us, cannot becompleted within a control period of 10 us.

As well known, the bandwidth of the different plants decidestheir control frequencies. In the APF system, the bandwidthof the current loop is expected to be wide enough to achievegood current tracking performance, while the dc bus voltagewith support of bulky capacitors can be well regulated evenwith slow control. The software PLL, which usually takesseveral fundamental cycles (400 Hz) to lock the phase, canbe implemented in slow control. To address the computationlimitation issue in the 400 Hz digital-controlled APF applica-tions, the multiresolution control strategy partitions the APF

3628 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 9, SEPTEMBER 2012

Fig. 7. Diagram of control timing sequence for multiresolution strategy.

Fig. 8. Diagram of dc voltage control loop.

controller into high- and low-frequency control groups, respec-tively, based on their control bandwidth. The high-frequencycontrol group, which executes twice in one switching period,has to complete its computations within a half switching cycle.The low-frequency control group, which executes once in nswitching periods, is allocated to one switching period, duringwhich the DSP completes all the computation elements forboth groups. The timing sequence of the multiresolution controlstrategy is shown in Fig. 7. Computational elements, (3, 4, 6,7, 8, and 9), in Table II, which are related to the current loopcalculation, operate with 100 kHz control frequency, and havea total execution time of 6.56 us (less than 10 us). In thismanner, the high-frequency group can reach up to 100 kHzcontrol frequency, while other computational elements can beexecuted with much lower frequency. A problem arose whenapplying the multiresolution control strategy: How to determinethe control and sampling frequencies for the low-frequencycontrol group without the degradation of the APF systemperformance.

V. DETERMINATION OF SAMPLING

AND CONTROL FREQUENCY

A. Control Frequency for DC Voltage Regulator

DC bus voltage regulator is designed to maintain the dccapacitor voltage constant. During steady-state operations, thedc capacitor voltage will not vary much due to the fact thatno real power is transferred across the APF. The only lossescome from switching devices and other components. In thiscase, only a small amount of real power is needed to chargethe dc capacitor. The dc voltage regulator could be designed tobe a low cutoff frequency. The diagram of the dc voltage controlloop is shown in Fig. 8, where Kvp and Kvi are the coefficientsof PI controller and Gi_close is the closed-current loop transfer

Fig. 9. Bode diagram of the open dc voltage loop.

function. In the proposed control strategy, one switching cycledelay (Ts) is supposed to be introduced in the voltage controlloop. The bode diagram of the open dc voltage control loopwithout PI regulator is plotted as shown in Fig. 9. As seenfrom Fig. 9, the cutoff frequency of the dc voltage open loopis around 55 Hz, which will be fast enough to regulate the dccapacitor voltage when operating in steady state. In the steadystate, a very low sampling frequency of the dc voltage could beapplied to stabilize the dc voltage.

However, during APF transient response, a great amount ofreal power will be transferred back and forth across the APFdue to the fact that LPFs “treat” the transient currents caused bysudden load changes as “harmonics,” which are real power andwill charge or discharge the dc capacitors, resulting in the greatvoltage fluctuations across the dc capacitor. Fig. 10 shows thediagram of real power transfer during load step-down transientresponse. The output current drops rapidly when the load stepsdown. The d-axis current in the synchronous reference frame,which is fed to the LPF to filter out the dc components, will dropcorrespondingly. Since the LPFs are designated to extract the dccomponents from the load currents, the bandwidth of LPFs isdesigned to be low (in the next subsection, a detailed design forthe bandwidth of LPFs will be given). Therefore, the transientcurrents will be filtered out and be treated as “harmonics.” Realpower is needed to compensate these “harmonics,” and the dccapacitor will be charged or discharged during this real power

HU et al.: DESIGN CONSIDERATIONS FOR DSP-CONTROLLED 400 Hz SHUNT ACTIVE POWER FILTER 3629

Fig. 10. Real power transfer during load step down.

Fig. 11. Bode diagram of open loop with PI controller.

transfer. If the bandwidth of the dc voltage loop is designedtoo low, the disturbance from load changes cannot be restrainedto a low level, resulting in high voltage fluctuations across thedc capacitor, and thus a higher voltage stress on switches andthe dc capacitor. To lower the voltage fluctuations, a higherbandwidth is desired to better track the disturbance.

On the other hand, during the steady-state operation, theharmonics compensation will cause the dc voltage ripples.In this case, the bandwidth of the voltage loop should beless than the frequency of the dc voltage ripples; otherwise,the compensating performance could become worse as theharmonic currents will be offset by the currents charging ordischarging to the dc bus capacitor. In a balanced three-phasesystem, the lowest harmonic order is fifth, which causes 2 kHzfrequency dc bus voltage ripples, while the bandwidth of theLPFs (explained in the next part) is designed at 300 Hz.Therefore, the bandwidth for the voltage loop is supposed tobe somewhere between 300 Hz and 2000 Hz. In this design,we made a tradeoff decision on the bandwidth of the voltageloop as the wider bandwidth needs high sampling and controlfrequency. A 600 Hz bandwidth is selected for the voltage loopas shown in Fig. 11. The attenuation at 5 kHz is −50 dB,which will keep anti-aliasing effect to be a neglectablelevel. Therefore, the 10 kHz sampling and control frequencywill be enough in accordance with the Shannon samplingtheorem.

Fig. 12. Downsampling structure for LPFs.

B. Low-Pass Filter

A LPF with a bandwidth of 300 Hz is designed to removethe harmonic components, whose s-domain transfer function isexpressed as

H(s) =2189299295

s3 + 1390.7s2 + 3631900s + 2189299295. (6)

To achieve good compensating performance, load currents(iLa iLb) are sampled at a frequency of 100 kHz, which inthe conventional implementation will be transformed into thecorresponding currents (iLd iLq) in the synchronous referenceframe and then be fed to the LPFs. In this case, LPF wouldrequire a significant amount of computation resources, as seenin Table II. As known, a LPF with a cutoff frequency of 300 Hzcan use a much lower sampling frequency, which will greatlyreduce its computation efforts. Since the load currents containhigh-order harmonics, to avoid the aliasing effect when down-sampling at a low frequency, a digital anti-aliasing filter hasto be inserted to filter out the high-order harmonics to satisfythe Shannon sampling theorem. The structure of extraction ofthe current fundamental component is modified as shown inFig. 12, where fk1 is 100 kHz and fk2 will be determined later.

The anti-aliasing filter operating at 100 kHz is designed tofilter out the high-order harmonics. To reduce computationalefforts of the anti-aliasing filter, the coefficients of the filterare deliberately designed for easy implementation in DSP. Thedifference equation of the anti-aliasing filter is expressed as

y(n) =x(n) − y(n − 1)

25+ y(n − 1). (7)

The cutoff frequency of the digital anti-aliasing filter isaround 1 kHz, beyond which the signals will be attenuated.In the three-phase system, the typical harmonic componentsare (6n ± 1) orders. After C32 transformation, the harmoniccomponents will be transformed into [(6n ± 1) − 1], whichmeans the 13th-order harmonic will be changed to 12th orderafter transformation. The 12th-order harmonic (4.8 kHz) willbe attenuated around 20 dB through the anti-aliasing filter.According to the Shannon sampling theorem, if the downsam-pling frequency for the LPFs is set to 9.6 kHz (twice the fre-quency of the 12th harmonic order), the high-order harmonicsabove 12th order will have little aliasing effect on the LPFsdue to a great attenuation of these high-order harmonics by thedigital anti-aliasing filter.

C. Phase-Locked Loop

Fig. 13 shows the block diagram of three-phase PLL sys-tem. The phase tracking performance would be improved bydesigning a controller with a wide bandwidth. However, the

3630 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 9, SEPTEMBER 2012

Fig. 13. Block diagram of the three-phase PLL system.

Fig. 14. Structure of a two-order band pass filter.

Fig. 15. Multisampling control strategy for PLL.

use of higher bandwidth does not provide better results in thisapplication, due to limited power capacity and relatively highoutput impedance in the 400 Hz power system, which causethe distorted voltages when connected by nonlinear loads. Inthe 400 Hz power system, the fundamental frequency is fixedat 400 Hz with small variation. To reduce sampling frequencyof the distorted phase voltages, a two-order band pass filter withband pass [300 Hz 500 Hz], functioned as an anti-aliasing filter,is inserted before ADC sampling, whose structure is shown inFig. 14.

Based on the aforementioned considerations, the bandwidthof the PLL control loop is chosen to be 400 Hz. With two orderband pass filter, sampling 20 points in one 400 Hz fundamentalcycle would be enough to reconfigure the fundamental wave-form. Therefore, the sampling frequency for phase voltagescould be reduced to as low as 8 kHz. Although the samplingfrequency for phase voltages fs1 is only 8 kHz, the accuratephase angle θ can still be obtained by employing the multisam-pling structure as shown in Fig. 15, where fs2 is 100 kHz.

In this way, the phase angle θ will be updated at each high-frequency control cycle as shown in Fig. 16.

Fig. 16. Voltage phase angle θ calculation within a PLL control cycle.

TABLE IIISUMMARY OF SAMPLING FREQUENCIES

TABLE IVCONTROL FREQUENCIES

D. Sampling and Control Frequencies

Based on above analysis and for the sake of the easy im-plementation, a sampling frequency of 12.5 kHz is selectedfor the low-frequency computation group. In this applica-tion, the sampling and control frequencies are summarized inTables III and IV.

VI. SIMULATION

To verify the performance of the proposed multiresolutioncontrol strategy, a 20 kVA APF model was set up in MatlabSimulink. The control system is digitalized in the simulation,and pure delay units are taken into consideration, which fullyemulates the digital implementation in DSP.

To demonstrate the performance difference between the pro-posed one and the one with 100 kHz control frequency for allcontrol plants, two control schemes were simulated. Fig. 17shows the grid current and the compensating current both inphase A. The THD of the proposed control scheme is 5.6% atfull load, while the THD of the control scheme with 100 kHzis 5.4%, which indicates that there is only very slight differ-ence in the current compensating performance. Fig. 18 showsdynamic performance of dc bus voltage during load step downfrom 20 kW to 0 kW, which also indicates that the dynamicperformance of the proposed scheme is almost as same as that

HU et al.: DESIGN CONSIDERATIONS FOR DSP-CONTROLLED 400 Hz SHUNT ACTIVE POWER FILTER 3631

Fig. 17. Grid current in Phase A and its compensating current.

Fig. 18. Comparison on the dc voltage dynamic performance of two controlcases.

Fig. 19. 20 kVA prototype.

of the case with 100 kHz control frequency. The comparisonson the performances of other control plants are also made in thesimulation and only show very slight difference.

VII. EXPERIMENTAL RESULTS

A 20 kVA APF prototype was set up in the laboratory asshown in Fig. 19. Considering current stress on the powerdevices, two inverter modules were paralleled with a common

dc bus and same PWM signals as shown in Fig. 20. Apart fromthe key parameters of the inverter modules listed in Table I,some other key circuit parameters are listed as follows:

• Switches Q1A-Q6A Q1B-Q6B: IXGN60N60C2D1.• Dead time: 400 ns.• Current sensor: HNC-661/662 (bandwidth: 200 kHz).• Voltage sensor: HNV500D (bandwidth:10 kHz).

Uncontrolled diode rectifier with LC filter and R function asa nonlinear load, whose parameters are 0.1 mH, 330 uF, and3.6 Ω, respectively. To minimize the execution time, mixedC and assembly language were adopted. For the time-criticalcodes like PI controller, dq-transformation, software PLL, etc.,assembly language is used, while for non-time-critical codes,C language is used for easy coding.

Fig. 21 shows the phase A voltage and current waveformwithout operation of APF, whose current total harmonic dis-tortion (THD) reaches up to 28.9%. To demonstrate the per-formance of two control schemes with 10 us and 20 us delaytime mentioned in Fig. 5, a comparative experiment studyis given. Fig. 22 shows the compensating performance whenemploying the 20 us control delay time. The current waveformstill has some distortion around zero-crossing area, and its THDis only reduced to 12.3%, which still cannot comply with theDO-160F standard. Fig. 23 shows the phase A voltage and cur-rent waveform with the proposed control method. The currentTHD is lowered down to 5.7%. Meanwhile, the distortion of thevoltage waveform is alleviated due to the load drawing nearlysinusoidal currents from the source. Fig. 23 also shows thattwo channel compensating currents are totally the same, whichindicates that there are no circulating currents between thesetwo inverter modules.

Since in the three-balanced system there only exist (6n ± 1)harmonic orders, Table V only shows the 5th, 7th, 11th, and13th harmonic components. The high-order components arenot listed in Table V as they can be easily filtered out usingsmall reactive filters to meet the standard. From Table V, wecan see that without APF compensating the current harmoniccomponents are far above those in DO-160F standard. Whenthe APF control system has 20 us control delay time, the currentharmonic components still cannot comply with the standard.However, when the proposed control strategy is employed toreduce the current loop control period to 10 us, harmoniccomponents are lower than those specified in the standard.

Due to wide bandwidth of the voltage loop control, the dcvoltage is well controlled during load change from 20 kW to3.5 kW as illustrated in Fig. 24, whose overshoot is only 30 Vabove the nominal dc bus voltage 400 V. Figs. 25 and 26 showthe dynamic performances with load change between 3.5 kWand 20 kW. From Fig. 25, it can be inferred that during loadchange from 3.5 kW to 20 kW (the load change rate is set to5 A/ms), the dc bus voltage is still maintained the same. Thismeans that during the slow load change condition, the dc volt-age regulator with its low control frequency has the capabilityto keep the dc bus voltage well regulated. As seen from Fig. 26,(the load change rate is set to 20 A/ms), APF current settlingtime is less than 11 ms, indicating good harmonics trackingperformance.

3632 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 9, SEPTEMBER 2012

Fig. 20. Overall APF structure with two paralleled inverters.

Fig. 21. Phase voltage and current before APF operation.

Fig. 22. Phase voltage and current with 20 us control delay.

VIII. CONCLUSION

The proposed multiresolution control strategy divides thecomputational elements in the APF into high- and low-frequency control groups. The high-frequency control groupexecutes twice every switching period. After high-frequency

Fig. 23. Phase voltage and currents with 10 us control delay.

TABLE VHARMONIC COMPONENT REQUIREMENT AND THEIR

COMPARISONS WITH DIFFERENT CASES

control elements execute eight times, an entire switching periodis allocated to all computation elements. The proposed methodovercomes the limitation of the DSP computation resources inthe 400 Hz APF control system by rearranging the computationelements based on their different requirements of control band-width. The detailed analysis is given to determine the controland sampling frequencies for different control plants in theAPF. The experimental results verified the proposed control

HU et al.: DESIGN CONSIDERATIONS FOR DSP-CONTROLLED 400 Hz SHUNT ACTIVE POWER FILTER 3633

Fig. 24. Transient response during load change from 20 kW to 3.5 kW.

Fig. 25. Phase voltage and current during load change from 3.5 kW to 20 kW.

Fig. 26. Phase voltage and current during load change from 20 kW to 3.5 kW.

strategy, indicating that the control system has good harmoniccurrent compensating effect, in addition to exhibiting a gooddynamic response.

This multiresolution control strategy and its analysis methodcan be easily extended to digital power conversion systems withhigh computation requirements.

REFERENCES

[1] J. Sun, “Aircraft power system harmonics involving single-phase PFCconverters,” IEEE Trans. Aerosp. Electron. Syst., vol. 44, no. 1, pp. 217–226, Jan. 2008.

[2] J. A. Rosero, J. A. Ortega, E. Aldabas, and L. Romeral, “Moving towardsa more electric aircraft,” IEEE Aerosp. Electron. Syst., vol. 22, no. 3,pp. 3–9, Mar. 2007.

[3] M. C. Jorge, A. C. Rafael, J. G. Felipe, J. G. Francisco, and S. R. Pedro,“A review of aeronautical electronics and its parallelism with automotiveelectronics,” IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 3090–3100,Jul. 2011.

[4] P. Athalye and D. Maksimovic, “High-performance front-end converterfor avionics applications,” IEEE Trans. Aerosp. Electron. Syst., vol. 39,no. 2, pp. 462–470, Apr. 2003.

[5] A. Eid, H. EI-Kishky, M. Abdel-Salam, and M. T. EI-Mohandes, “Onpower quality of variable-speed constant-frequency aircraft electric powersystems,” IEEE Trans. Power Del., vol. 25, no. 1, pp. 55–65, Jan. 2010.

[6] G. Gong, M. L. Heldwein, U. Drofenik, J. Minibock, and J. W. Kolar,“Comparative evaluation of three-phase high-power factor AC-DC con-verter concepts for application in future more electric aircraft,” IEEETrans. Ind. Electron., vol. 52, no. 3, pp. 727–737, Jun. 2005.

[7] M. Hartmann, J. Miniboeck, H. Ertl, and J. Kolar, “A three-phase deltaswitch rectifier for more electric aircraft applications employing a novelPWM current control concept,” in Proc. 24th IEEE APEC, Washington,DC, Feb. 2009, pp. 1633–1640.

[8] A. Uan-Zo-li, R. Burgos, F. Wang, D. Boroyevich, F. Lacaux,and A. Tardy, “Comparison of prospective topologies for aircraftautotransformer-rectifier units,” in Proc. 29th IEEE IECON, Roanoke,VA, Nov. 2003, pp. 1122–1127.

[9] DO-160F, Section 16-Power Input Environmental Conditions and TestProcedures for Airborne Equipment.

[10] A. Eid, M. Abdel-Salam, H. EI-Kishky, and T. EI-Mohandes, “Activepower filters for harmonic cancellation in conventional and advancedaircraft electric power systems,” Elect. Power Syst. Res., vol. 79, no. 1,pp. 80–88, Jan. 2009.

[11] M. Odavic, M. Sumner, and P. Zanchetta, “Control of a multi-level activeshunt power filter for more electric aircraft,” in Proc. 13th Eur. Conf.Power Electron. Appl., Barcelona, Spain, Sep. 2009, pp. 1–10.

[12] M. Odavic, P. Zanchetta, and M. Sumner, “A low switching frequencyhigh bandwidth current control for active shunt power filter in aircraftspower networks,” in Proc. 33rd IEEE IECON, Taipei, Taiwan, Nov. 2007,pp. 1863–1868.

[13] E. Lavopa, P. Zanchetta, M. Sumner, and F. Cupertino, “Real-time esti-mation of fundamental frequency and harmonics for active shunt powerfilters in aircraft electrical systems,” IEEE Trans. Ind. Electron., vol. 56,no. 8, pp. 2875–2884, Aug. 2009.

[14] H. Hu, W. Shi, J. Xu, Y. Lu, and Y. Xing, “A multi-resolution controlstrategy for DSP controlled 400 Hz shunt active power filter in an aircraftpower system,” in Proc. 25th IEEE APEC, Palm Spring, CA, Feb. 2010,pp. 1785–1791.

[15] H. Hu, W. Shi, Y. Lu, and Y. Xing, “Design and implementation of fullydigital-controlled 400 Hz active power filter for aircraft applications,” inProc. IEEE ECCE, Atlanta, GA, Sep. 2010, pp. 4223–4229.

[16] J. M. Correa, F. A. Farret, and M. G. Simoes, “Application of a modifiedsingle-phase P-Q theory in the control of shunt and series active filtersin 400 Hz microgrid,” in Proc. 36th IEEE Power Electron. Spec. Conf.,Recife, Brazil, Jun. 2005, pp. 2585–2591.

[17] D. Chen, T. Guo, S. Xie, and B. Zhou, “Shunt active filters applied in theaircraft power utility,” in Proc. 36th IEEE Power Electron. Spec. Conf.,Recife, Brazil, Jun. 2005, pp. 59–63.

[18] Z. Li, Y. Li, P. Wang, H. Zhu, and C. Liu, “Single-loop digital control ofhigh-power 400-Hz ground power unit for airplanes,” IEEE Trans. Ind.Electron., vol. 57, no. 2, pp. 532–543, Feb. 2010.

[19] S. Lopez Arevalo, P. Zanchetta, P. W. Wheeler, A. Trentin, andL. Empringham, “Control and implementation of a matrix-converter-based AC ground power-supply unit for aircraft servicing,” IEEE Trans.Ind. Electron., vol. 57, no. 6, pp. 2076–2084, Jun. 2010.

[20] M. EI-Habrouk, M. K. Darwish, and P. Mehta, “Active power filters:A review,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 147, no. 5,pp. 403–413, Sep. 2000.

3634 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 9, SEPTEMBER 2012

[21] A. Chandra, B. Singh, and K. Al-Haddad, “An improved control algorithmof shunt active filter for voltage regulation, harmonic elimination, power-factor correction, and balancing of nonlinear loads,” IEEE Trans. PowerElectron., vol. 15, no. 3, pp. 495–507, May 2000.

[22] J. Allmeling, “A control structure for fast harmonics compensation inactive filters,” IEEE Trans. Power Electron., vol. 19, no. 2, pp. 508–514,May 2004.

[23] J. Mossoba and P. W. Lehn, “A controller architecture for high bandwidthactive power filters,” IEEE Trans Power Electron., vol. 18, no. 1, pp. 317–325, Jan. 2003.

[24] P. Jintakosonwit, H. Fujita, and H. Akagi, “Control and performance ofa fully-digital-controlled shunt active filter for installation on a powerdistribution system,” IEEE Trans. Power Electron., vol. 17, no. 1, pp. 132–140, Jan. 2002.

[25] H. Fujita, “A single-phase active filter using an H-bridge PWM converterwith a sampling frequency quadruple of the switching frequency,” IEEETrans. Power Electron., vol. 24, no. 4, pp. 934–941, Apr. 2009.

[26] T. Jin and K. M. Smedley, “Operation of one-cycle controlled three-phaseactive power filter with unbalanced source and load,” IEEE Trans. PowerEletron., vol. 21, no. 5, pp. 1403–1412, Sep. 2006.

Haibing Hu (M’09) received the B.S. degree fromHunan University of Technology, Zhuzhou, China,in 1995, the M.S. and Ph.D. degrees in electricalengineering from Zhejiang University, Hangzhou,China, in 2003 and 2007, respectively.

From 2007 to 2009, he was an Assistant Professorin the Department of Control Engineering, NanjingUniversity of Aeronautics and Astronautics, wherehe is currently an Associate Professor. In 2009, hejoined the Department of Electrical Engineering,University of Central Florida as a Postdoctoral Re-

search Fellow. He has authored and coauthored more than 40 technical paperspublished in journals and conference proceedings. His research interests coverdigital control in power electronics, multilevel inverter, digital control systemintegration for power electronics and applying power electronics to distributedenergy systems and power quality.

Wei Shi was born in Jiangsu Province, China, in1987. He received the B.S. and M.S. degrees inelectrical engineering from Nanjing University ofAeronautics and Astronautics, Nanjing, China, in2008 and 2011, respectively.

His main research interests include dc-ac con-verter, high efficiency dc-dc converters, and powerquality control technology.

Ying Lu was born in Jiangsu Province, China, in1984. He received the B.S. and M.S. degrees inelectrical engineering from Nanjing University ofAeronautics and Astronautics, Nanjing, China, in2006 and 2009. In 2009, he joined the Ever-solarNew Energy company, Shouzhou, China.

His main research interests include dc-ac con-verter and power quality control technology.

Yan Xing (M’03) was born in Shandong Province,China, in 1964. She received the B.S. and M.S. de-grees in automation and electrical engineering fromTsinghua University, Beijing, China, in 1985 and1988, respectively, and the Ph.D. degree in electricalengineering from Nanjing University of Aeronauticsand Astronautics (NUAA), Nanjing, China, in 2000.

Since 1988, she has been with the Faculty ofElectrical Engineering, NUAA, and is currently aprofessor with the Aero-Power Sci-Tech Center, Col-lege of Automation Engineering, NUAA. She has

authored more than 60 technical papers published in journals and conferenceproceedings and has also published three books. Her research interests includetopology and control for dc-dc and dc-ac converters.