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v3.1
40MX and 42MX Automotive FPGA Families
Features
High Capacity• Single-Chip ASIC Alternative for Automotive
Applications• 3,000 to 54,000 System Gates• Up to 2.5 kbits Configurable Dual-Port SRAM• Fast Wide-Decode Circuitry• Up to 202 User-Programmable I/O Pins
Ease of Integration• Up to 100% Resource Utilization and 100% Pin
Locking• Deterministic, User-Controllable Timing • Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II• Low Power Consumption • IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Note: While the automotive-grade MX devices are offered in standard speed grade only, the MX family is also offered in commercial,industrial and military temperature grades with -F, Std, -1, -2 and -3 speed grades. Refer to the 40MX and 42MX Family FPGAsdatasheet for more details.
Contact your local Actel representative for device availability.
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded basedon characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. Iftesting to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office todiscuss testing options available.
_
Part Number
Speed Grade
Package Type
Package Lead Count
A = Automotive (–40 to +125˚C)Application (Temperature Range)
A40MX02 = 3,000 System GatesA40MX04 = 6,000 System GatesA42MX09 = 14,000 System GatesA42MX16 = 24,000 System GatesA42MX24 = 36,000 System GatesA42MX36 = 54,000 System Gates
General DescriptionActels' automotive-grade MX families provide a high-performance, single-chip solution for shortening thesystem design and development cycle, offering a cost-effective alternative to ASICs for in-cabin telematics andautomobile interconnect applications. The 40MX and42MX devices are excellent choices for integrating logicthat is currently implemented in multiple PALs, CPLDs,and FPGAs.
The MX device architecture is based on Actel’s patentedantifuse technology implemented in a 0.45µm triple-metal CMOS process. With capacities ranging from 3,000to 54,000 system gates, the MX devices are live onpower-up and have one-fifth the standby powerconsumption of comparable FPGAs. Actel’s MX FPGAsprovide up to 202 user I/Os and are available in a widevariety of packages and speed grades.
The automotive-grade 42MX24 and 42MX36 includesystem-level features such as IEEE Standard 1149.1 (JTAG)Boundary Scan Testing and fast wide-decode modules. Inaddition, the A42MX36 device offers dual-port SRAM forimplementing fast FIFOs, LIFOs, and temporary datastorage. The storage elements can efficiently addressapplications requiring wide datapath manipulation.
MX Architectural OverviewThe MX devices are composed of fine-grained buildingblocks that enable fast, efficient logic designs. All deviceswithin these families are composed of logic modules, I/Omodules, routing resources and clock networks, whichare the building blocks for fast logic designs. In addition,the A42MX36 device contains embedded dual-portSRAM modules, which are optimized for high-speeddatapath functions such as FIFOs, LIFOs and scratchpadmemory. A42MX24 and A42MX36 also contain wide-decode modules.
Logic ModulesThe 40MX logic module is an eight-input, one-outputlogic circuit designed to implement a wide range of logicfunctions with efficient use of interconnect routingresources (Figure 1-1).
The logic module can implement the four basic logicfunctions (NAND, AND, OR and NOR) in gates of two,three, or four inputs. The logic module can alsoimplement a variety of D-latches, exclusivity functions,AND-ORs and OR-ANDs. No dedicated hardwired latchesor flip-flops are required in the array; latches and flip-
flops can be constructed from logic modules wheneverrequired in the application.
The 42MX devices contain three types of logic modules:combinatorial (C-modules), sequential (S-modules) anddecode (D-modules). Figure 1-2 illustrates thecombinatorial logic module. The S-module, shown inFigure 1-3 on page 1-2, implements the samecombinatorial logic function as the C-module whileadding a sequential element. The sequential element canbe configured as either a D-flip-flop or a transparentlatch. The S-module register can be bypassed so that itimplements purely combinatorial logic.
A42MX24 and A42MX36 devices contain D-modules,which are arranged around the periphery of the device.D-modules contain wide-decode circuitry, providing afast, wide-input AND function similar to that found inCPLD architectures (Figure 1-4 on page 1-2). The D-module allows A42MX24 and A42MX36 devices toperform wide-decode functions at speeds comparable toCPLDs and PALs. The output of the D-module has aprogrammable inverter for active HIGH or LOWassertion. The D-module output is hardwired to anoutput pin, and can also be fed back into the array to beincorporated into other logic.
Figure 1-1 • 40MX Logic Module
Figure 1-2 • 42MX C-Module Implementation
D00D01D10D11
S0
S1
Y
A0B0
A1B1
v3.1 1-1
40MX and 42MX Automotive FPGA Families
Dual-Port SRAM ModulesThe A42MX36 device contains dual-port SRAM modules,which are arranged in 256-bit blocks and can beconfigured as 32x8 or 64x4. SRAM modules can becascaded together to form memory spaces of user-definable width and depth. A block diagram of theA42MX36 dual-port SRAM block is shown in Figure 1-5on page 1-3.
The A42MX36 SRAM modules are true dual-portstructures containing independent read and write ports.Each SRAM module contains six bits of read and writeaddressing (RDAD[5:0] and WRAD[5:0], respectively) for64x4-bit blocks. When configured in byte mode, thehighest order address bits (RDAD5 and WRAD5) are notused. The read and write ports of the SRAM block
contain independent clocks (RCLK and WCLK) withprogrammable polarities offering active HIGH or LOWimplementation. The SRAM block contains eight datainputs (WD[7:0]) and eight outputs (RD[7:0]), which areconnected to segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimalsolution for high-speed buffered applications requiringFIFO and LIFO queues. The ACTgen Macro Builder withinActel's Designer software provides capability to quicklydesign memory functions with the SRAM blocks.
Figure 1-3 • 42MX S-Module Implementation
Figure 1-4 • A42MX24 and A42MX36 D-Module Implementation
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 4-Input Function Plus Latch with Clear
D0
D1S
Y D Q
GATECLR
OUT
Up to 8-Input Function (Same as C-Module)
D00
D01
D10
D11S1
S0
Y OUT
Up to 7-Input Function Plus Latch
D00D01
D10
D11S1
S0
Y OUT
GATE
D Q
D00D01
D10
D11S1
S0
Y D Q OUT
7 Inputs
Hard-Wire to I/O
Feedback to Array
Programmable Inverter
1-2 v3.1
40MX and 42MX Automotive FPGA Families
Routing StructureThe MX architecture uses vertical and horizontal routingtracks to interconnect the various logic and I/O modules.These routing tracks are metal interconnects that may becontinuous or split into segments. Varying segmentlengths allow the interconnect of over 90% of designtracks to occur with only two antifuse connections.Segments can be joined together at the ends usingantifuses to increase their lengths up to the full length ofthe track. All interconnects can be accomplished with amaximum of four antifuses.
Horizontal RoutingHorizontal routing tracks span the whole row length orare divided into multiple segments and are located inbetween the rows of modules. Any segment that spansmore than one-third of the row length is considered along horizontal segment. A typical channel is shown inFigure 1-6. Within horizontal routing, dedicated routingtracks are used for global clock networks and for powerand ground tie-off tracks. Non-dedicated tracks are usedfor signal nets.
Vertical RoutingAnother set of routing tracks run vertically through themodule. There are three types of vertical tracks: input,output, and long. Long tracks span the column length ofthe module, and can be divided into multiple segments.Each segment in an input track is dedicated to the inputof a particular module; each segment in an output trackis dedicated to the output of a particular module. Longsegments are uncommitted and can be assigned duringrouting. Each output segment spans four channels (two
above and two below), except near the top and bottomof the array, where edge effects occur. Long verticaltracks contain either one or two segments. An exampleof vertical routing tracks and segments is shown inFigure 1-6.
Antifuse StructuresAn antifuse is a "normally open" structure. The use ofantifuses to implement a programmable logic deviceresults in highly testable structures as well as efficientprogramming algorithms. There are no pre-existingconnections; temporary connections can be made usingpass transistors. These temporary connections can isolateindividual antifuses to be programmed and individualcircuit structures to be tested, which can be done beforeand after programming. For instance, all metal tracks canbe tested for continuity and shorts between adjacenttracks, and the functionality of all logic modules can beverified.
Figure 1-5 • A42MX36 Dual-Port SRAM Block
SRAM Module32 x 8 or 64 x 4
(256 Bits)
ReadPortLogic
WritePortLogic
RD[7:0]
Routing Tracks
Latches
ReadLogic
[5:0] RDAD[5:0]
REN
RCLK
LatchesWD[7:0]
LatchesWRAD[5:0]
WriteLogic
MODEBLKEN
WEN
WCLK
[5:0]
[7:0]
Figure 1-6 • MX Routing Structure
SegmentedHorizontalRouting
LogicModules
Antifuses
Vertical Routing Tracks
v3.1 1-3
40MX and 42MX Automotive FPGA Families
Clock NetworksThe 40MX devices have one global clock distributionnetwork (CLK). A signal can be put on the CLK networkby being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanoutclock distribution networks, referred to as CLKA andCLKB. Each network has a clock module (CLKMOD) thatcan select the source of the clock signal from any of thefollowing (Figure 1-7):
• Externally from the CLKA pad, using CLKBUFbuffer
• Externally from the CLKB pad, using CLKBUFbuffer
• Internally from the CLKINTA input, using CLKINTbuffer
• Internally from the CLKINTB input, using CLKINTbuffer
The clock modules are located in the top row of I/Omodules. Clock drivers and a dedicated horizontal clocktrack are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices canalso be used as normal I/Os, bypassing the clocknetworks.
The A42MX36 device has four additional register controlresources, called quadrant clock networks (Figure 1-8).Each quadrant clock provides a local, high-fanoutresource to the contiguous logic modules within itsquadrant of the device. Quadrant clock signals canoriginate from specific I/O pins or from the internal arrayand can be used as a secondary register clock, registerclear, or output enable.
Figure 1-7 • Clock Networks of 42MX Devices
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
CLKB
CLKAFromPads
ClockDrivers
CLKMOD
CLKINB
CLKINA
S0S1
InternalSignal
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
QuadClockModul
QCLKA
QCLKB
*QCLK1IN
S0 S1
QCLK1
QuadClockModul
*QCLK2IN
S0 S1
QCLK2
QuadClockModul
QCLKC
QCLKD
*QCLK3IN
S0S1
QCLK3
QuadClockModul
*QCLK4IN
S0S1
QCLK4
1-4 v3.1
40MX and 42MX Automotive FPGA Families
I/O ModulesThe I/O modules provide the interface between thedevice pins and the logic array. Figure 1-9 is a blockdiagram of the 42MX I/O module. A variety of userfunctions, determined by a library macro selection, canbe implemented in the module. (Refer to the AntifuseMacro Library Guide for more information.) All 42MX I/Omodules contain tristate buffers, with input and outputlatches that can be configured for input, output, orbidirectional operation.
42MX devices contain flexible I/O structures, where eachoutput pin has a dedicated output-enable control(Figure 1-9). The I/O module can be used to latch input oroutput data, or both, providing fast setup time. Inaddition, the Actel Designer software tools can build a D-type flip-flop using a C-module combined with an I/Omodule to register input and output signals. Refer to theAntifuse Macro Library Guide for more details.
Actel's Designer software development tools provide adesign library of I/O macro functions that can implementall I/O configurations supported by the MX FPGAs.
Other Architectural Features
User SecurityThe Actel FuseLock provides robust security againstdesign theft. Special security fuses are hidden in thefabric of the device and prevent unauthorized users fromaccessing the programming and/or probe interfaces. It isvirtually impossible to identify or bypass these fuseswithout damaging the device, making Actel antifuseFPGAs immune to both invasive and noninvasive attacks.
Special security fuses in 40MX devices include the ProbeFuse and Program Fuse. The former disables the probingcircuitry while the latter prohibits further programmingof all fuses, including the Probe Fuse. In 42MX devices,
there is the Security Fuse which, when programmed,both disables the probing circuitry and prohibits furtherprogramming of the device.
Look for this symbol to ensure your valuable IP is secure.
For more information, refer to Actel's Implementation ofSecurity in Actel Antifuse FPGAs application note.
ProgrammingDevice programming is supported through the SiliconSculptor series of programmers. Silicon Sculptor II is acompact, robust, single-site and multi-site deviceprogrammer for the PC. With standalone software,Silicon Sculptor II is designed to allow concurrentprogramming of multiple units from the same PC.
Silicon Sculptor II programs devices independently toachieve the fastest programming times possible. Afterbeing programmed, each fuse is verified to insure that ithas been programmed correctly. Furthermore, at the endof programming, there are integrity tests that are run toensure no extra fuses have been programmed. Not onlydoes it test fuses (both programmed andnonprogrammed), Silicon Sculptor II also allows self-testto verify its own hardware extensively.
The procedure for programming an MX device usingSilicon Sculptor II is as follows:
1. Load the .AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Acteloffers device volume-programming services eitherthrough distribution partners or via In-HouseProgramming from the factory.
For more details on programming MX devices, pleaserefer to the Programming Antifuse Devices and theSilicon Sculptor II user's guides.
Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module)
Power SupplyAutomotive MX devices are designed to operate in 5.0V environments. Table 1-1 describes the voltage settings ofautomotive MX devices.
Power-Up/Down When powering up MX devices, VCCA must be greaterthan or equal to VCCI throughout the power-upsequence. If VCCI exceeds VCCA during power-up, eitherthe input protection junction on the I/Os will be forward-biased or the I/Os will be at logical High, and ICC rises tohigh levels. During power-down, VCCA must be smallerthan or equal to VCCI.
Test Circuitry and Silicon Explorer II ProbeMX devices contain probing circuitry that provides built-in access to every node in a design, via the use of SiliconExplorer II. Silicon Explorer II is an integrated hardwareand software solution that, in conjunction with theDesigner software, allow users to examine any of theinternal nodes of the device while it is operating in aprototyping or a production system. The user can probean MX device without changing the placement androuting of the design and without using any additionalresources. Silicon Explorer II's noninvasive method doesnot alter timing or loading effects, thus shortening thedebug cycle and providing a true representation of thedevice under actual functional situations.
Silicon Explorer II samples data at 100 MHz(asynchronous) or 66 MHz (synchronous). Silicon ExplorerII attaches to a PC's standard serial port, turning the PCinto a fully functional 18-channel logic analyzer. SiliconExplorer II allows designers to complete the designverification process at their desks and reducesverification time from several hours per cycle to a fewseconds.
Silicon Explorer II is used to control the MODE, DCLK, SDIand SDO pins in MX devices to select the desired nets fordebugging. The user simply assigns the selected internalnets in the Silicon Explorer II software to the PRA/PRBoutput pins for observation. Probing functionality isactivated when the MODE pin is held HIGH.
Figure 1-11 on page 1-7 illustrates the interconnectionbetween Silicon Explorer II and 40MX devices, whileFigure 1-12 on page 1-7 illustrates the interconnectionbetween Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses mustnot be programmed. (Refer to "User Security" section onpage 1-5 for the security fuses of 40MX and 42MXdevices). Table 1-2 on page 1-7 summarizes the possibledevice configurations for probing.
PRA and PRB pins are dual-purpose pins. When the"Reserve Probe Pin" is checked in theDesigner software, PRA and PRB pins are reserved asdedicated outputs for probing. If PRA and PRB pins arerequired as user I/Os to achieve successful layout and"Reserve Probe Pin" is checked, the layout tool willoverride the option and place user I/Os on PRA and PRBpins.
Table 1-1 • Voltage Support of Automotive-Grade MX Devices
Device VCC VCCA VCCI Maximum Input Tolerance Nominal Output Voltage
40MX 5.0V – – 5.25V 5.0V
42MX – 5.0V 5.0V 5.25V 5.0V
1-6 v3.1
40MX and 42MX Automotive FPGA Families
Figure 1-11 • Silicon Explorer II Setup with 40MX
Figure 1-12 • Silicon Explorer II Setup with 42MX
Table 1-2 • Device Configuration Options for Probe Capability
No HIGH Probe Circuit Outputs Probe Circuit Inputs
Yes – Probe Circuit Secured Probe Circuit Secured
Notes:
1. Avoid using SDI, SDO, DCLK, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, inputsignals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin Descriptions" section onpage 1-45 for information on unused I/O pins.
40MX
SiliconExplorer II
PRAPRB
SDO
DCLKSDI
MODESerial Connection
to Windows PC
16 Logic Analyzer Channels
42MX
SiliconExplorer II
PRAPRB
SDO
DCLKSDI
MODESerial Connectionto Windows PC
16 Logic Analyzer Channels
v3.1 1-7
40MX and 42MX Automotive FPGA Families
Design ConsiderationIt is recommended to use a series 70Ω terminationresistor on every probe connector (SDI, SDO, MODE,DCLK, PRA and PRB). The 70Ω series termination is usedto prevent data transmission corruption during probingand reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test (BST) CircuitryAutomotive-grade 42MX24 and 42MX36 devices arecompatible with IEEE Standard 1149.1 (informally knownas Joint Testing Action Group Standard or JTAG), whichdefines a set of hardware architecture and mechanismsfor cost-effective, board-level testing. The basic MXboundary-scan logic circuit is composed of the TAP (testaccess port), TAP controller, test data registers andinstruction register (Figure 1-13). This circuit supports allmandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and some optional instructions.Table 1-3 on page 1-9 describes the ports that controlJTAG testing, while Table 1-4 on page 1-9 describes thetest instructions supported by these MX devices.
Each test section is accessed through the TAP, which hasfour associated pins: TCK (test clock input), TDI and TDO(test data input and output), and TMS (test modeselector).
The TAP controller is a four-bit state machine. The '1'sand '0's represent the values that must be present at TMSat a rising edge of TCK for the given state transition tooccur. IR and DR indicate that the instruction register orthe data register is operating in that state.
The TAP controller receives two control inputs (TMS andTCK) and generates control and clock signals for the restof the test logic architecture. On power-up, the TAPcontroller enters the Test-Logic-Reset state. To guaranteea reset of the controller from any of the possible states,TMS must remain high for five TCK cycles.
Automotive-grade 42MX24 and 42MX36 devices supportthree types of test data registers: bypass, deviceidentification, and boundary scan. The bypass register isselected when no other register needs to be accessed in adevice. This speeds up test data transfer to other devicesin a test data path. The 32-bit device identificationregister is a shift register with four fields (lowestsignificant byte (LSB), ID number, part number andversion). The boundary-scan register observes andcontrols the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, eachwith a serial-in, serial-out, parallel-in, and parallel-outpin. The serial pins are used to serially connect all theboundary-scan register cells in a device into a boundary-scan register chain, which starts at the TDI pin and endsat the TDO pin. The parallel ports are connected to theinternal core logic tile and the input, output and controlports of an I/O buffer to capture and load data into theregister to control or observe the logic state of each I/O.
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK)
TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edgeof the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequencyfor TCK is 20 MHz
TDI (Test Data Input) Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock
TDO (Test DataOutput)
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (highimpedance) when data scanning is not in progress
Table 1-4 • Supported BST Public Instructions
Instruction IR Code [2:0] Instruction Type Description
EXTEST 000 Mandatory Allows the external circuitry and board-level interconnections tobe tested by forcing a test pattern at the output pins andcapturing test results at the input pins
SAMPLE/PRELOAD 001 Mandatory Allows a snapshot of the signals at the device pins to becaptured and examined during operation
HIGH Z 101 Optional Tristates all I/Os to allow external signals to drive pins. Pleaserefer to the IEEE Standard 1149.1 specification for details
CLAMP 110 Optional Allows state of signals driven from component pins to bedetermined from the Boundary-Scan Register. Please refer tothe IEEE Standard 1149.1 specification for details
BYPASS 111 Mandatory Enables the bypass register between the TDI and TDO pins. Thetest data passes through the selected device to adjacent devicesin the test chain
v3.1 1-9
40MX and 42MX Automotive FPGA Families
JTAG Mode ActivationThe JTAG test logic circuit is activated in the Designersoftware by selecting Tools and then Device Selection.This brings up the Device Selection dialog box as shownin Figure 1-14. The JTAG test logic circuit can be enabledby clicking the "Reserve JTAG Pins" check box. Table 1-5explains the pins' behavior in either mode.
TRST Pin and TAP Controller ResetAn active reset (TRST) pin is not supported; however, MXdevices contain power-on circuitry that resets theboundary-scan circuitry upon power-up. Also, the TMSpin is equipped with an internal pull-up resistor. Thisallows the TAP controller to remain in or return to theTest-Logic-Reset state when there is no input or when alogical 1 is on the TMS pin. To reset the controller, TMSmust be HIGH for at least five TCK cycles.
Boundary Scan Description Language (BSDL) FileConforming to the IEEE Standard 1149.1 requires thatthe operation of the various JTAG components bedocumented. The BSDL file provides the standard formatto describe the JTAG components that can be used byautomatic test equipment software. The file includes theinstructions that are supported, instruction-bit pattern,and the boundary-scan chain order. For an in-depthdiscussion on BSDL files, please refer to Actel BSDL FilesFormat Description application note.
Actel BSDL files are grouped into two categories—generic and device-specific. The generic files assign alluser I/Os as inouts. Device-specific files assign user I/Os asinputs, outputs, or inouts.
Generic files for MX devices are available on Actel's websiteat http://www.actel.com/techdocs/models/bsdl.html.
Figure 1-14 • Device Selection Wizard
Table 1-5 • Boundary Scan Pin Configuration and Functionality
Reserve JTAG Checked Unchecked
TCK BST input; must be terminated to logical HIGH or LOW to avoid floating User I/O
TDI, TMS BST input; may float or be tied to HIGH. TDI may be tied to TDO of another device User I/O
TDO BST output; may float or be connected to TDI of another device User I/O
Development Tool SupportThe automotive-grade MX family of FPGAs is fullysupported by both Actel's Libero™ Integrated DesignEnvironment (IDE) and Designer FPGA Developmentsoftware. Actel Libero IDE is a design managementenvironment, seamlessly integrating design tools whileguiding the user through the design flow, managing alldesign and log files, and passing necessary design dataamong tools. Libero IDE allows users to integrate bothschematic and HDL synthesis into a single flow and verifythe entire design in a single environment. Libero IDEincludes Synplify® for Actel from Synplicity®, ViewDrawfor Actel from Mentor Graphics, ModelSim™ HDLSimulator from Mentor Graphics®, WaveFormer Lite™from SynaptiCAD™, and Designer software from Actel.Refer to the Libero IDE flow (located on Actel’s website)diagram for more information.
Actel's Designer software is a place-and-route tool andprovides a comprehensive suite of backend support toolsfor FPGA development. The Designer software includestiming-driven place-and-route, and a world-classintegrated static timing analyzer and constraints editor.With the Designer software, a user can select and lockpackage pins while only minimally impacting the resultsof place-and-route. Additionally, the back-annotationflow is compatible with all the major simulators and thesimulation results can be cross-probed with SiliconExplorer II, Actel’s integrated verification and logicanalysis tool. Another tool included in the Designersoftware is the ACTgen macro builder, which easilycreates popular and commonly used logic functions forimplementation into your schematic or HDL design.Actel's Designer software is compatible with the mostpopular FPGA design entry and verification tools fromcompanies such as Mentor Graphics, Synplicity, Synopsys,and Cadence Design Systems. The Designer software isavailable for both the Windows and UNIX operatingsystems.
Related Documents
Application NotesActel BSDL Files Format Description
Note: *Stresses beyond those listed under “Absolute MaximumRatings” may cause permanent damage to the device.Exposure to absolute maximum rated conditions forextended periods may affect device reliability. Devicesshould not be operated outside the RecommendedOperating Conditions.
Parameter Automotive1 Units
Temperature Range2 -40 to +125 °C
VCCI 4.75 to 5.25 V
VCCA 4.75 to 5.25 V
VCC 4.75 to 5.25 V
Notes:
1. Automotive grade parts (A grade) devices are tested at roomtemperature to specifications that have been guard bandedbased on characterization across the recommendedoperating conditions. A-grade parts are not tested atextended temperatures. If testing to ensure guaranteedoperation at extended temperatures is required, pleasecontact your local Actel Sales office to discuss testingoptions available.
2. Ambient temperature (TA)
Symbol Parameter Conditions
AutomotiveUnits
Min. Max.
VOH1 Output High Voltage (IOH = –4 mA) 3.1 V
VOL1 Output Low Voltage (IOL = 4 mA) 0.4 V
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.1 V
IIL, IIH Input Leakage Current –20 20 µA
IOZ Tristate Output Leakage Current –20 20 µA
tR, tF Input Transition Time 250 ns
CIO I/O Capacitance 10 pF
ICC2 Standby Current 35 mA
IIO I/O source sink current Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
Notes:
1. Only one output tested at a time. VCC/VCCI = min.2. All outputs unloaded. All inputs = VCC/VCCI or GND.
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N + IOH * (VCCI – VOH) * M
where:
ICCstandby is the current flowing when no inputs oroutputs are changing.
ICCactive is the current flowing due to CMOSswitching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads toVOL.
M equals the number of outputs driving TTL loads toVOH.
Accurate values for N and M are difficult to determinebecause they depend on the family type, on designdetails, and on the system I/O. The power can be dividedinto two components: static and active.
Static Power ComponentActel FPGAs have small static power components thatresult in power dissipation lower than PALs or CPLDs. Byintegrating multiple PALs/CPLDs into one FPGA, an evengreater reduction in board-level power dissipation canbe achieved.
The power due to standby current is typically a smallcomponent of the overall power.
The static power dissipation by TTL loads depends on thenumber of outputs driving HIGH or LOW, and on the DCload current. Again, this number is typically small. Forinstance, a 32-bit bus sinking 4 mA at 0.33V will generate42 mW with all outputs driving LOW, and 140 mW withall outputs driving HIGH. The actual dissipation willaverage somewhere in between, as I/Os switch stateswith time.
Active Power ComponentPower dissipation in CMOS devices is usually dominatedby the active (dynamic) power dissipation. Thiscomponent is frequency-dependent and a function ofthe logic and the external I/O. Active power dissipationresults from charging internal chip capacitances of theinterconnect, unprogrammed antifuses, module inputs,and module outputs, plus external capacitance due to PCboard traces and load device inputs. An additionalcomponent of the active power dissipation is the totempole current in the CMOS transistor pairs. The net effectcan be associated with an equivalent capacitance thatcan be combined with frequency and voltage torepresent active power dissipation.
The power dissipated by a CMOS circuit can be expressedby the equation:
Power (µW) = CEQ * VCCA2 * F
EQ 1-1
where:
Equivalent CapacitanceEquivalent capacitance is calculated by measuringICCactive at a specified frequency and voltage for eachcircuit component of interest. Measurements have beenmade over a range of frequencies at a fixed value of VCC.Equivalent capacitance is frequency-independent, so theresults can be used over a wide range of operatingconditions. Equivalent capacitance values are shown onthe following page.
To calculate the active power dissipated from thecomplete design, the switching frequency of each part ofthe logic must be known. The equation below shows apiece-wise linear summation over all components.
Determining Average Switching FrequencyTo determine the switching frequency for a design, thedata input values to the circuit must be clearlyunderstood. The following guidelines represent worst-case scenarios; these can be used to generally predict theupper limits of power dissipation.
Modules (CEQM) 3.5
Input Buffers (CEQI) 6.9
Output Buffers (CEQO) 18.2
Routed Array Clock Buffer Loads (CEQCR) 1.4
m = Number of logic modules switching at frequency fm
n = Number of input buffers switching at frequency fn
p = Number of output buffers switching at frequency fp
q1 = Number of clock loads on the first routed arrayclock
q2 = Number of clock loads on the second routed arrayclock
r1 = Fixed capacitance due to first routed array clock
r2 = Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL = Output load capacitance in p
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
Device Typer1
routed_Clk1r2
routed_Clk2
A40MX02 41.4 N/A
A40MX04 68.6 N/A
A42MX09 118 118
A42MX16 165 165
A42MX24 185 185
A42MX36 220 220
Logic Modules (m) = 80% of CombinatorialModules
Inputs Switching (n) = # of Inputs/4
Outputs Switching (p) = # of Outputs/4
First Routed Array Clock Loads (q1) = 40% of SequentialModules
Second Routed Array Clock Loads(q2)
= 40% of SequentialModules
Load Capacitance (CL) = 35 pF
Average Logic Module SwitchingRate (fm)
= F/10
Average Input Switching Rate (fn) = F/5
Average Output Switching Rate (fp) = F/10
Average First Routed Array ClockRate (fq1)
= F
Average Second Routed Array ClockRate (fq2)
= F/2
1-14 v3.1
40MX and 42MX Automotive FPGA Families
Junction TemperatureThe temperature variable in the Designer software refersto the junction temperature, not the ambienttemperature. This is an important distinction because theheat generated from dynamic power consumption isusually hotter than the ambient temperature. EQ 1-3 canbe used to calculate junction temperature.
Junction Temperature = ∆T + Ta (1)
EQ 1-3
Where:
Ta = Ambient Temperature
∆T = Temperature gradient between junction (silicon)and ambient
∆T = θja * P
P = Power
θja = Junction to ambient of package. θja numbers arelocated in the "Package Thermal Characteristics" section.
Package Thermal CharacteristicsThe device junction-to-case thermal characteristic is θjc,and the junction-to-ambient air characteristic is θja. Thethermal characteristics for θja are shown with twodifferent air flow rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum powerdissipation allowed for a PQFP 160-pin package atautomotive temperature is as follows:
Predictable Performance: Tight Delay DistributionsPropagation delay between logic modules depends onthe resistive and capacitive loading of the routing tracks,the interconnect elements, and the module inputs beingdriven. Propagation delay increases as the length ofrouting tracks, the number of interconnect elements, orthe number of inputs increases.
From a design perspective, the propagation delay can bestatistically correlated or modeled by the fanout(number of loads) driven by a module. Higher fanoutusually requires some paths to have longer routingtracks.
The MX FPGAs deliver a tight fanout delay distribution,which is achieved in two ways: by decreasing the delay ofthe interconnect elements and by decreasing the numberof interconnect elements per path.
Actel’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses, fabricated in0.45 µ lithography, offer nominal levels of 100 Ωresistance and 7.0 femtofarad (fF) capacitance perantifuse.
MX fanout distribution is also tight due to the lownumber of antifuses required for each interconnect path.The proprietary architecture limits the number ofantifuses per path to a maximum of four, with90 percent of interconnects using only two antifuses.
Timing CharacteristicsDevice timing characteristics fall into three categories:family-dependent, device-dependent, and design-dependent. The input and output buffer characteristicsare common to all MX devices. Internal routing delaysare device-dependent. Design dependency means actualdelays are not determined until after place-and-route ofthe user’s design is complete. Delay values may then bedetermined by using the Timer tool in the Designersoftware or by performing simulation with post-layout delays.
Critical Nets and Typical NetsPropagation delays in this datasheet apply to typicalnets, which are used for initial design performanceevaluation. Critical net delays can then be applied to themost timing critical paths. Critical nets are determined bynet property assignment in Actel's Designer softwareprior to placement and routing. Up to 6% of the nets ina design may be designated as critical.
Long TracksSome nets in the design use long tracks, which arespecial routing resources that span multiple rows,columns, or modules. Long tracks employ three andsometimes four antifuse connections, which increasecapacitance and resistance, resulting in longer net delaysfor macros connected to long tracks. Typically, up to6 percent of nets in a fully utilized device require longtracks. Long tracks add approximately a 3 ns to a 6 nsdelay, which is represented statistically in higher fanout(FO=8) routing delays in the datasheet specificationssection beginning on page 1-16.
Timing Derating MX devices are manufactured with a CMOS process.Therefore, device performance varies according totemperature, voltage and process changes. Minimumtiming parameters reflect maximum operating voltage,minimum operating temperature and best-caseprocessing. Maximum timing parameters reflectminimum operating voltage, maximum operatingtemperature and worst-case processing.
v3.1 1-25
40MX and 42MX Automotive FPGA Families
Temperature and Voltage Derating Factors Table 1-7 • 42MX Temperature and Voltage Derating Factors (Normalized to TJ = 125°C, VCCA/VCCI = 4.75V)
42MX Voltage
Temperature
–55°C –40°C 0°C 25°C 70°C 85°C 125°C
4.75 0.66 0.67 0.74 0.78 0.89 0.91 1.00
5.00 0.64 0.65 0.72 0.75 0.87 0.89 0.97
5.25 0.62 0.64 0.70 0.73 0.84 0.86 0.94
Note: This derating factor applies to all routing and propagation delays.
Figure 1-32 • 42MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 125°C, VCCA/VCCI = 4.75V)
42MX Derating Factor (Normalized to T = 125°C, V /V =4.75V)
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
4.75 5.00 5.25
Dera
ting
Fact
or
-55°C
-40°C
0°C
25°C
70°C
85°C
125°C
J CCICCA
Voltage (V)
1-26 v3.1
40MX and 42MX Automotive FPGA Families
Table 1-8 • 40MX Temperature and Voltage Derating Factors (Normalized to TJ = 125°C, VCC = 4.75V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-33 • 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 125°C, VCC 4.75V)
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
4.75 5.00 5.25
Dera
ting
Fact
or
Voltage (V)
-55°C
-40°C
0°C
25°C
70°C
85°C
125°C
40MX Derating Factor (Normalized to T = 125°C, V = 4.75V)J CC
v3.1 1-27
40MX and 42MX Automotive FPGA Families
Timing CharacteristicsThe timing numbers in the datasheet represent sample timing characteristics of the devices. Refer to the Timer tool inthe Designer software for design-specific timing information.
tWCLKA Flip-Flop (Latch) Clock Active Pulse 5.8 ns
tWASYN Flip-Flop (Latch) 5.8 ns
tA Flip-Flop Clock Input Period 8.7 ns
fMAX Flip-Flop (Latch) Clock Frequency 116 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.3 ns
tINYL Pad-to-Y LOW 1.2 ns
Input Module Predicted Routing Delays1
tIRD1 FO=1 Routing Delay 3.7 ns
tIRD2 FO=2 Routing Delay 4.6 ns
tIRD3 FO=3 Routing Delay 5.6 ns
tIRD4 FO=4 Routing Delay 6.5 ns
tIRD8 FO=8 Routing Delay 10.2 ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating deviceperformance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating deviceperformance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
tWCLKA Flip-Flop (Latch) Clock Active Pulse 5.8 ns
tWASYN Flip-Flop (Latch) 5.8 ns
tA Flip-Flop Clock Input Period 8.7 ns
fMAX Flip-Flop (Latch) Clock Frequency 116 MHz
Input Module Propagation Delays
tINYH Pad-to-Y HIGH 1.3 ns
tINYL Pad-to-Y LOW 1.2 ns
Input Module Predicted Routing Delays1
tIRD1 FO=1 Routing Delay 3.7 ns
tIRD2 FO=2 Routing Delay 4.6 ns
tIRD3 FO=3 Routing Delay 5.6 ns
tIRD4 FO=4 Routing Delay 6.5 ns
tIRD8 FO=8 Routing Delay 10.2 ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimatingdevice performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimatingdevice performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever isappropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimatingdevice performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can beobtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever isappropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimatingdevice performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can beobtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever isappropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimatingdevice performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can beobtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v3.1 1-41
40MX and 42MX Automotive FPGA Families
tRENSU Read Enable Set-Up 1.0 ns
tRENH Read Enable Hold 5.7 ns
tWENSU Write Enable Set-Up 4.5 ns
tWENH Write Enable Hold 0.0 ns
tBENS Block Enable Set-Up 4.6 ns
tBENH Block Enable Hold 0.0 ns
Asynchronous SRAM Operations
tRPD Asynchronous Access Time 13.6 ns
tRDADV Read Address Valid 14.7 ns
tADSU Address/Data Set-Up Time 2.7 ns
tADH Address/Data Hold Time 0.0 ns
tRENSUA Read Enable Set-Up to Address Valid 1.0 ns
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-44 v3.1
40MX and 42MX Automotive FPGA Families
Pin DescriptionsCLK/A/B, I/O Global Clock
Clock inputs for clock distribution networks. CLK is for40MX while CLKA and CLKB are for 42MX devices. Theclock input is buffered prior to clocking the logicmodules. This pin can also be used as an I/O.
DCLK, I/O Diagnostic Clock
TTL clock input for diagnostic probe and deviceprogramming. DCLK is active when the MODE pin isHIGH. This pin functions as an I/O when the MODE pin isLOW.
GND Ground
Input LOW supply voltage.
I/O Input/Output
Input, output, tristate, or bidirectional buffer. Input andoutput levels are compatible with standard TTLspecifications. Unused I/O pins are configured by theDesigner software as shown in Table 1-15.
In all cases, it is recommended to tie all unused I/O pinsto LOW on the board. This applies to all dual-purposepins when configured as I/Os as well.
MODE Mode
Controls the use of multifunction pins (DCLK, PRA, PRB,SDI, TDO). To provide verification capability, the MODEpin should be held HIGH. To facilitate this, the MODE pinshould be tied to GND through a 10kΩ resistor so thatthe MODE pin can be pulled HIGH when required.
NC No Connection
This pin is not connected to circuitry within the device.These pins can be driven to any voltage or can be leftfloating with no effect on the operation of the device.
PRA/B, I/O Probe
The Probe pin is used to output data from any user-defined design node within the device. Each diagnosticpin can be used in conjunction with the other probe pinto allow real-time diagnostic output of any signal pathwithin the device. The Probe pin can be used as a user-defined I/O when verification has been completed. Thepin's probe capabilities can be permanently disabled toprotect programmed design confidentiality. The Probepin is accessible when the MODE pin is High. This pinfunctions as an I/O when the MODE pin is Low.
QCLKA,B,C,D, I/O Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When notused as a register control signal, these pins can functionas general-purpose I/Os.
SDI, I/O Serial Data Input
Serial data input for diagnostic probe and deviceprogramming. SDI is active when the MODE pin is High.This pin functions as an I/O when the MODE pin is Low.
SDO, TDO, I/O Serial Data Output
Serial data output for diagnostic probe and deviceprogramming. SDO is active when the MODE pin is High.This pin functions as an I/O when the MODE pin is Low.SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as anoutput while the "checksum" is run. It will return to userI/O when "checksum" is complete.
TCK, I/O Test Clock
Clock signal to shift the Boundary Scan Test (BST) datainto the device. This pin functions as an I/O when"Reserve JTAG" is not checked in the Designer software.BST pins are only available in the A42MX24 andA42MX36 devices.
TDI, I/O Test Data In
Serial data input for BST instructions and data. Data isshifted in on the rising edge of TCK. This pin functions asan I/O when "Reserve JTAG" is not checked in theDesigner software. BST pins are only available in theA42MX24 and A42MX36 devices.
Table 1-15 • Configuration of Unused I/Os
Device Configuration
A40MX02, A40MX04 Pulled LOW
A42MX09, A42MX16 Pulled LOW
A42MX24, A42MX36 Tristated
v3.1 1-45
40MX and 42MX Automotive FPGA Families
TDO, I/O Test Data Out
Serial data output for BST instructions and test data. Thispin functions as an I/O when "Reserve JTAG" is notchecked in the Designer software. BST pins are onlyavailable in the A42MX24 and A42MX36 devices.
TMS, I/O Test Mode Select
The TMS pin controls the use of the IEEE 1149.1Boundary Scan pins (TCK, TDI, TDO). In flexible modewhen the TMS pin is set LOW, the TCK, TDI and TDO pinsare boundary-scan pins. Once the boundary scan pins arein test mode, they will remain in that mode until theinternal boundary scan state machine reaches the "logicreset" state. At this point, the boundary scan pins will bereleased and will function as regular I/O pins. The "logicreset" state is reached five TCK cycles after the TMS pin isset High. In dedicated test mode, TMS functions asspecified in the IEEE 1149.1 specifications. IEEE JTAGspecification recommends a 10kΩ pull-up resistor on thepin. BST pins are only available in A42MX24 andA42MX36 devices.
VCC Supply Voltage
Supply voltage for 40MX devices.
VCCA Supply Voltage
Supply voltage for array in 42MX devices.
VCCI Supply Voltage
Supply voltage for I/Os in 42MX devices.
WD, I/O Wide Decode Output
When a wide decode module is used in a an A42MX24 orA42MX36 device, this pin can be used as a dedicatedoutput from the wide decode module. This directconnection eliminates additional interconnect delaysassociated with regular logic modules. To implement thedirect I/O connection, connect an output buffer of anytype to the output of the wide decode macro and placethis output on one of the reserved WD pins. When awide decode module is not used, this pin functions as aregular I/O pin.
1-46 v3.1
40MX and 42MX Automotive FPGA Families
Package Pin Assignments
68-Pin PLCC
NoteFor Package Manufacturing and Environmental information, visit Resource center athttp://www.actel.com/products/rescenter/package/index.html.
List of ChangesThe following table lists critical changes that were made in the current version of the document.
Datasheet CategoriesIn order to provide the latest information to designers, some datasheets are published before data has been fullycharacterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” Thedefinition of these categories are as follows:
Product BriefThe product brief is a summarized version of a advanced datasheet (advanced or production) containing generalproduct information. This brief gives an overview of specific device and family information.
AdvancedThis datasheet version contains initial estimated information based on simulation, other products, devices, or speedgrades. This information can be used as estimates, but not for production.
Datasheet SupplementThe datasheet supplement gives specific device information for a derivative family that differs from the general familydatasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information andfor specifications that do not differ between the two families.
Unmarked (production)This datasheet version contains information that is considered to be final.
Previous Version Changes in Current Version v3.1 Page
v3.0 A note was added to the "Ordering Information". ii
April 2004 Note 1 was added to "Recommended Operating Conditions". 1-12
v2.0 The "Speed Grade and Temperature Grade Matrix" table is new. page 1-ii
The "Clock Networks" section was updated. page 1-4
The "I/O Modules" section was updated. page 1-5
The "Other Architectural Features" section is new page 1-5
The "Development Tool Support" section was updated. page 1-11
The "Electrical Specifications" table was updated. page 1-12
The "Junction Temperature" section was updated. page 1-15
Table 1-6 was updated. page 1-15
Figure 1-15 and Figure 1-16 were updated. page 1-16
Figure 1-17 was updated. page 1-17
Figure 1-18 was updated. page 1-18
The "Critical Nets and Typical Nets" section was updated. page 1-25
The "Timing Derating" section is new. page 1-25
Table 1-7 and Figure 1-32 were updated. page 1-26
Table 1-8 and Figure 1-33 were updated. page 1-27
All timing numbers contained in Table 1-9 through Table 1-14 were updated. page 1-28 to page 1-41
The "Pin Descriptions" section was updated. page 1-45
v3.1 3-1
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