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Three-phase soft-switched PWM inverter for motordrive application

J. Shukla and B.G. Fernandes

Abstract: A novel soft-switched inverter topology in which three mutually coupled inductors at atime are involved in the resonance process is proposed. By the introduction of magnetic couplingbetween three resonant inductors, the zero-voltage instants for the inverter can be generated by oneauxiliary switch. Also, the resonant energy can be recycled, and the maximum voltage stress on theauxiliary circuit diode components is confined to the DC-link clamp voltage level. The DC link canbe clamped to 1.11.3 times the DC-source value. This is unlike the soft-switched inverter in whichtwo mutually coupled inductors are at a time are involved in a resonance process [14], wherein theclamping diode experiences voltage stress of the order of 11 per unit when clamping the DC-linkvoltage at 1.1 per unit. The proposed inverter also provides pulse-width modulated operation. Ananalysis of this novel quasi-resonant DC-link inverter topology is presented to reveal its soft-switching characteristics. Simulation and laboratory experiments are performed to validate theanalysis.

1 Introduction

Quasi-resonant inverters offer several advantages comparedwith resonant DC-link inverters [13] with regard toresonant link design and control, device rating requirementsand use of pulse width modulation ( PWM). Over the years,extensive research work has been carried out in the field ofquasi-resonant DC-Link (QRDCL) PWM inverters [417].The QRDCL inverter schemes generate zero-voltage (ZV)instants in the DC link at controllable instants that can besynchronised with any PWM transition command, thus

ensuring a ZV switching condition of inverter devices. As aresult, these inverters can be operated at high switchingfrequencies with high efficiency.

Among the different types of QRDCL inverter schemereported in the literature, the category of inverters in whichan inductor is connected between the DC link and the DCsource are particularly suited for high-frequency and high-power applications [1017]. This is owing to the fact thatthese inverters do not have a high-frequency resonantswitch in the main power path of the inverter. However,higher DC-link voltage stress [11], a high auxiliary switchingdevice count [13] and the requirement of a separate low-voltage DC source to clamp the DC link [1517] are themain limitations of these schemes.

One of the QRDCL inverter topology falling into thiscategory is the passively clamped QRDCL ( PCQRDCL)inverter reported in [14]. This topology (shown in Fig. 1a)can be considered to be a state-of-the-art QRDCL schemesatisfying most of the essential requirements, such as lowclamp factor, simple resonance control, guaranteed zero-link voltage condition, PWM capability, use of only oneauxiliary switch and recycling of resonant energy. It wasshown that, by the introduction of magnetic coupling

between two resonant inductors, the zero-voltage instantscan be generated by only one auxiliary switch. Also, the DClink can be clamped at 1.11.3 per unit, and resonant energycan be recycled. The only drawback of this scheme was thehigh reverse voltage requirement of the clamp diode. Thevoltage-blocking capability of this diode is of the order of 11per unit for a clamping factor of 1.1 per unit. This problemcan be solved by use of a separate, low-voltage DC source.However, realisation of this low-voltage DC source is itself aproblem. In the case of a battery-operated inverter, the clampdiode can be connected to a separate low-voltage battery

group. In the absence of a battery source, the realisation, of aseparate, low-voltage DC source becomes difficult.

Another possible solution could be to use a DCDCregulator or a simple R-C parallel circuit to maintain lowvoltage (refer to Fig. 1b). The use of a DCDC regulatorincreases the component count and control complexity.Also, if the DCDC regulator is not capable of feeding theprocesses resonant energy back to the DC source, then thisenergy is dissipated in resistor. This reduces overallefficiency of the inverter. An optimum strategy in whichDCDC regulator maintains a separate low voltage forclamping purposes and also feeds back the clamp energy tothe DC source has yet not been reported in the literature.

Hence, the objective of this paper is to design a QRDCLinverter circuit using one auxiliary switch, in which themaximum voltage stress in all semiconductor diodes isconfined to the DC-link clamp voltage level Vc. Also, theresonant energy associated with the clamping action isrecovered without the use of an extra switching circuit.Such a QRDCL inverter scheme is shown in Fig. 2, inwhich three mutually coupled inductors are used to achievethe above features. Only one auxiliary switch is used togenerate zero-voltage instants for the inverter switchingdevices.

2 Principle of operation

Through the introduction of magnetic coupling betweenthree resonant inductors (L1, L2 and L3), as shown inFig. 2, the zero-voltage instants for the inverter can beE-mail: [email protected], [email protected]

The authors are with the Electrical Engineering Department, Indian Institute ofTechnology Bombay, Powai, Mumbai-400076, India

r The Institution of Engineering and Technology 2007

doi:10.1049/iet-epa:20050539

Paper first received 31st August 2005 and in final revised form 25th May 2006

IET Electr. Power Appl., Vol. 1, No. 1, January 2007 93

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on November 29, 2008 at 01:46 from IEEE Xplore. Restrictions apply.

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generated by one auxiliary switch. Also, the current in the

auxiliary inductor L2 can now reverse during the resonantcycle. Thus switch S2 can be turned off under the ZVcondition. Clamping is provided by a large filter capacitorCF, which acts as a low-voltage DC source whose averagecurrent in steady state is zero. The entire resonant energyassociated with the clamping circuit is recycled. This can beeasily observed from the waveform of current iCF flowingthrough CF, as shown in Fig. 4. At steady state, the areaenclosed by its discharging current (area A1) is equal to thearea enclosed by its charging current (area A2). The voltageacross CFvCF attains a value equal to K 1Vs, where Kis the clamping factor and lies in the range of 1.11.3. ThisDC voltage across CF is analogous to a separate low-voltage DC source, as seen in a few QRDCL schemes

reported in the literature [1417]. Assuming that the inverteris feeding an inductive load (which can be represented by aconstant current source), the steady-state DC voltage across

CF depends on the values of L1, L2, L3 and CR and thecoupling coefficients of mutually coupled inductors k12, k23and k13.

i1

i2

i3

VC

IO

IM

ScSb

Sa Sb Sc

Sa

Vs+

+

L1

L3D3

C

L2

S2

D2

i2

VC

IO

+

i3

i1

IM

ScSb

Sa Sb Sc

Sa

Vs+

+

CS2

D2

L2

D3

L1

S

a b

Fig. 1 Invertersa Passively clamped QRDCL inverter with mutually coupled inductors proposed in [14]

b Quasi-resonant inverter using separate low-voltage DC source for clamping purpose [14]

Fig. 2 Proposed quasi-resonant DC-link inverter using threecoupled inductors

i1

VC RCR

i2

Vs+

i3

CF

VC F

+

D1

S2D2

L2

L1

D Io

+

D3

L3

Fig. 3 Simplified equivalent circuit of proposed QRDCL inverter

Fig. 4 Resonant link waveforms

94 IET Electr. Power Appl., Vol. 1, No. 1, January 2007


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3 Analysis and modes of operation

Operation of the proposed QRDCL inverter can beexplained by reference to Figs. 25. The various modes ofcircuit operation are described as follows.

3.1 Mode 0t0 t t1: pseudo steady-state mode (S2, D1, D2 and D3 off)During this mode, the inverter is said to be in pseudosteady-state mode. The resonant circuit formed by L1 andCR oscillates. The voltage vCR across capacitor CR alternatesbetween Vc KVs and 2 KVs. Also, the inductor currenti1 oscillates around the inverter input current (representedby a constant current source Io), and the magnitude of this

ripple is Vs Vc=o1 L1, where o1 1=ffiffiffiffiffiffiffiffiffiffiffiL1 CR

p. The DC-

link voltage vCR settles to Vs owing to the finite resistance ofthe resonant components. This mode of operation ends attime t1, when S2 is turned on under the ZV condition toreduce the DC-link voltage vCR to zero. If we neglect theresistance of the circuit, the state equations of this mode aregiven by

iL1 t t0 Vs Vc =R01 sin o1 t t0 Io 1vCR t

t0

Vs

Vs

Vc

cos o1 t

t0

2

where R01 ffiffiffiffiffiffiffiffiffiffiffiffiffiL1=CR

pand o1 1=

ffiffiffiffiffiffiffiffiffiffiffiL1 CRp . Initial condi-

tions for this mode are vCRt0 Vc and iL1t0 Io.

3.2 Mode 1 t1 t t2: link voltagereduces sinusoidally (S2 on; D1, D2 andD3 off)With S2 on, the resonance between L1, L2 andCR causes CRto discharge. Current flowing through L1 decreasessinusoidally, and that flowing through L2 increasessinusoidally. When voltage across CRvCR becomes equalto the sum of vCF and the voltage induced in L3, D3 turnson, and this mode of operation ends. The equations for

link voltage and currents during this mode can be derived

as follows:

vCR t t1 Vs

L1 L2 2M12

L2 M12 L1 M12 coso t t1 3

i1 t t1 Io Vso L1 L2 2M12

o t t1 L1 M12 L2 M12 L1 L2 M212

sino t t1 !

4

i2 t t1 Vso L1 L2 2M12

o t t1 L1 M12 2

L2 L2 M212sino t t1

" #

5where, o

1= ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiL12

CRp

, L12

L1

L2

M212

=

L1

L2 M12 and M12 k12 ffiffiffiffiffiffiffiffiffiffiffiffiffiL1 L2p . Initial conditions forthis mode are vCRt1 Vs, i1t1 Io, and i2t1 0. Theduration of this mode is given as

t2 t1 1o

cos1AB

6

where

A Vc M23 M13 L2 M12 VsL1 L2 2M12

B

VsM23L1 M212 M13L1 M12L2 M12L1 M12L1L2 M212

L1 L2 2M12L1L2 M2

12

Fig. 5 Equivalent circuits during various modes of operation



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3.3 Mode 2t2 t t3: link voltagecontinues to decrease sinusoidally (S2 andD3 on; D1 and D2 off)A resonant circuit consisting of mutually coupled inductorsL1, L2, L3 and CR is formed. Capacitor CR continues todischarge. This mode of operation ends when CR dischargesto zero. The equations governing this mode are

L1di1

dtM12 di2

dtM13 di3

dt 1

CR

Zt0

i1t

i3t

i2t

Io

dt

Vs

7

L2

di2

dtM21 di1

dtM23 di3

dt 1

CR

Zt0

i1t i3ti2t Iodt 0 8

L3di3

dtM31 di1

dtM32 di2

dt 1

CR

Zt0

i1t

i3t i2t Iodt vCF 9where M13 k13

ffiffiffiffiffiffiffiffiffiffiffiffiffiL1 L3

p, M23 k23

ffiffiffiffiffiffiffiffiffiffiffiffiffiL2 L3

p, M12 M21,

M23 M32, and M13 M31. Initial conditions for this modeare i1 i1t2, i2 i2t2, i3 0 and vCR vCRt2. It wasfound that this mode of operation occurs for a negligible

small interval of time. From Fig. 4, it can be observed thatthe duration of this mode is very small compared with thetime taken by the DC-link voltage to reduce to zero fromsource voltage value (which itself is small). Thus the changein currents i1, i2 and i3 during this mode is negligibly smalland can be neglected. Also, as the area enclosed by currentiCF during this mode is negligible, the contribution of thismode towards steady-state DC-voltage build-up across CFis neglected. A situation in which three mutually coupledinductors are involved in a resonance process with CRoccurs twice during the entire circuit operation. One suchsituation occurs during this mode, and another occursduring mode 4 of operation (discussed later). During mode4 of operation, such a situation lasts for a longer duration

and, hence, is not neglected.

3.4 Mode 3 t 3 t t4 : zero link voltagecondition (S2 on and D2 off; inverterfreewheeling diodes on; D3 on; D1 off)During this interval, the freewheeling diodes in the inverterlegs represented by D start conducting. Link voltage isclamped at 0 V, and the inverter devices can be turnedon/off under zero-voltage condition. A linearly increasingdischarge current iCF flows out of the positive electrode ofcapacitor CF. Current flowing through L1 increases linearly,and that flowing through L2 decreases linearly. Owing tomagnetic coupling between L1 and L2, current flowing

through freewheeling diodes across the PWM inverterswitches decreases linearly. This mode of operation endswhen current flowing through the freewheeling diodesreduces to zero. The equation for link voltage and currentscan be derived as

vCR t t3 0 10i1 t t3 i1 t2

t t3 L2 M13 M12 M23 vCF L2 L3 M223

Vs

D

11i2 t t3 i2 t2

t t3 L1 M23 M12M13 vCF M13M23 L3M12 Vs D

12

i3 t t3 i3 t2

t t3 L1 L2 M212

vCF L2 M13 M12M23 Vs

D

13where D L1 L2 L3 L3 M212 L2 M213 2M12M13M23L1 M

223. Initial conditions for this mode are i1 i1t2,

i2 i2t2, i3t2 0 and vCR 0. It should be noted thatthe initial conditions for currents i1; i2 and i3 are theirrespective values at the end of mode 1 (the effect of mode 2

is neglected), and that of vCR is zero.The duration of this mode is given as

TZero t4 t3 i2 t2 Io i1 t2 i3 t2 DvCF C Vs E

14

where C L2 M13 M12M23 M13M12 L1 M23 L1 L2M212, and E L2 L3 M223 L3M12 M13M23 L2M13M12M23.

The expression for the area enclosed by current iCF i3during this mode is given as

iCF;area;M3

t4 t23 L1L2vCF M212vCF L2M13Vs

M12M23Vs

2D 15

3.5 Mode 4 t 4 t t5 : capacitor CRcharges: stage 1 (S2 on then off; D2 off thenon; D3 on; D1 off)During this mode of operation, CR charges owing to theresonance caused between mutually coupled inductors L1,L2, L3 and CR. Capacitor CF continues to discharge. Thestate equations for this mode are the same as that ofmode 2, except for the initial conditions. If circuitparameters and initial conditions are used, the analyticalsolution of the mathematical equations governing this modebecomes difficult to solve manually. However, if thenumerical values of a few circuit parameters are known apriori, these equations can be solved with ease. Softwarepackages such as Mathematica can be used as an aid tosolve the equations. As an example, if numerical value ofcircuit parameters such as Vs 600, Io 50, L1 281mH,L2 29mH, L3 43:8mH, k12 0:9, k13 0:6, k23 0:5,CR 22 nF are used, with symbolic notations for vCF,i1t4, i2t4, i3t4, the state equations and the expressionfor area enclosed by iCF are given in Appendix 9.

Note that, when the above equations are solved, thecapacitor voltage vCF and initial conditions for currents atthe start of this mode i1t4; i2t4; i3t4 are kept assymbolic notations. This helps to solve the circuit from the

previous mode to the next mode of operation, and to provethe concept of steady-state DC-voltage build-up across CF,on which the entire circuit operation is based (discussed inthe following Section). If (29) is plotted with respect to time,there will be two zero-crossings or solutions (see Fig. 4).This implies that i2 reverses its direction, making the anti-parallel diode of switch S2 D2 conduct for a short interval.When D2 is conducting, S2 is turned off under zero-voltageand zero-current switching conditions. This mode ofoperation ends when D2 turns off.

3.6 Mode 5 t 5 t t6 : capacitor CRcharges: stage 2 (S2, D1 and D2 off; D3 on)During this mode of operation, a resonant circuit consisting

ofL1, L3 and CR is formed. Voltage across CR continues toincrease. This mode ends when the sinusoidally decreasingdischarge current iCF decreases to zero. At this instant,



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D3 turns off. The equations governing this mode are given as

L1di1

dtM13 di3

dt 1

CR

Zt0

i1t i3t Io dt Vs 16

L3di3

dtM13 di1

dt 1

CR

Zt0

i1t i3t Io dt vCF 17

The state equations during this mode are derived based onthe same arguments made in the previous mode of operation.

The initial conditions during this mode are: vCR vCRt5,i1 i1t5, i2 i2t5 and i3 i3t5. The state equationsand the expression for area enclosed by iCF during this modeare given in Appendix 9.

3.7 Mode 6 t 6 t t7 : capacitor CRcharges: stage 3 (S2, D1, D2 and D3 off)During this mode of operation, a resonance circuitconsisting of L1 and CR is formed. Voltage across CRcontinues to increase. Current flowing through L1 decreasessinusoidally. This mode ends when the voltage across CRreaches the clamp voltage level KVs Vs vCF. The linkcurrent and voltage equations are

iL1 t t6 Io i1 t6 Io cos o1 t t6 Vs vCR t6

R01sin o1 t t6 18

vCR t t6 i1 t6 Io R01 sin o1 t t6 Vs vCR t6 cos o1 t t6 Vs 19

The duration of this mode is given as

t7 t6 1o1

tan12ab

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffiffiffiffiffiffi2ab 24 b2 c2 a2 c2

q2 b2 c2

0@

1A

20where a Vs vCRt6, b i1t6 IoR01 and c vCF.

3.8 Mode 7 t 7 t t8 : clamping action(S2, D2 and D3 off; D1 on)During this mode of operation, the DC-link voltage vCR isclamped at Vs vCF KVs. Current flowing throughL1 i1 is fed to CF by diode D1. This current decreaseslinearly. This mode of operation ends when i1 becomesequal to inverter load current Io. After this mode ofoperation, the DC link returns to mode 0 of operation. Thelink current and voltage equations are

iL1 t t7 Vs

Vc

L1 t t7 iL1 t7 21vCR t t7 Vs vCF 22

The duration of this mode is given as

t8 t7 Io i1 t7 L1Vs Vs vCF

23

The expression for the area enclosed by current iCF duringthis mode is given as

iCF;area;M7 0:5 t8 t7 i1 t7 Io 24

4 Link design and control scheme

The design of QRDCL topology with three coupledinductors shown in Fig. 2 involves the selection ofparameters L1, L2, L3, CR, M12, M23 and M13 to the satisfythe desired link waveform specifications such as dv=dt,di=dt, value of K, peak currents in L1, L2, L3 and TZero. Thedesign process for the proposed QRDCL circuit topology isiterative in nature, wherein a simulation study or calcula-tions based on (1)(24) are required to adjust the linkparameters and to verify that the design specifications aremet. The following design guidelines are recommended forthe design of the topology.

Initially, suitable values for L1 and CR are chosen.Inductance L1 consists of the sum of DC-source inductance

and externally connected inductance between the DCsource and the DC link. It prevents a significant rise in

Fig. 6 Plot ofvCF against iCF;area;average, TZero and zero-voltage turn-off time available for S2



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source current above load current value Io when theDC-link voltage reduces below Vs. Hence, L1 in the rangeof 100500mH is selected. Capacitance CR consists of straycapacitance across the PWM inverter DC-busbar terminalsand externally connected resonant capacitor. Generally, CRin the range of 10100mH is selected.

Inductances L2 and L3 and coupling coefficients k12, k23and k13 are chosen in the following range: L2 0:1L1,L3 1:5L2, k12 maximum possible (usually k12 in therange of 0.850.95 can be obtained), k13 0:6k12 andk

23 minimum possible (usually k

23in the range of 0.40.5

can be obtained). Practical considerations limit the mini-mum value of k23 that can be obtained. Once all circuitparameter values are chosen based on the above-mentionedguidelines, the circuit equations for various modes ofoperation are executed to check whether essentially requiredspecifications are met (such as the steady-state DC-voltagebuild-up across CF, which decides the clamping factor Kofthe inverter DC-link voltage). Capacitor CF is chosen suchthat constant voltage with negligible ripple is maintainedacross it. As the average value of the charging anddischarging current flowing through CF is negligibly small(of the order of 0.250.5A), an empirical value in the range

of 5005000 times the value of CR is sufficient to givesatisfactory performance. Thus, under steady-state condi-tions, when steady DC voltage builds up across CF, thefollowing condition must be satisfied:

iCF;area;average iCF;area;M7 iCF;area;M3 iCF;area;M4 iCF;area;M5 0 25

where, iCF;area;M7 is the area enclosed by iCF during mode 7.When the average area enclosed by the current through

CF

iCF;area;average

is calculated, a suitable value for vC

F %0:1Vs is assumed, and (15), (32), (36), (24) and (25) areevaluated. This process is repeated by either the increasing(ifiCF;area;average40) or decreasing (if iCF;area:averageo0) of thevalue of vCF until the value of iCF;area;average becomes zero.The value ofvCF at which iCF;area:average becomes zero is thevalue of the steady-state voltage across CF. The proposedcircuit with the parameters given in mode 4 is solved usingMATLAB, and the plot of vCF against iCF;area;average isshown in Fig. 6. It can be observed that the steady-statevoltage attained across CF is 121 V. Figure 6 also showsthe plot of the zero DC-link voltage period and zero-voltageturn-off period available for S2.

a b

c d

Fig. 7 Simulation resultsa M12 is increased from 81.5mH to 85.5mH in steps of 2mH

b M13 is increased from 66.56 mH to 74.56mH in steps of 4 mH

c M23 is increased from 17.81mH to 21.81mH in steps of 2 mH

d CR is increased from 22 nF to 28 nF in steps of 3 nF



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For the same circuit, the effect of change in variouscircuit parameters (M12, M13, M23, CR, L1, L2 and L3) wasstudied using a SABER simulator. The simulated wave-forms for each individual parameter change are shown inFigs. 7 and 8, respectively. In this study, each circuitparameter was given an incremental change (while otherparameters were kept constant), and the results wereplotted. These results are enumerated in Table 1 and canhelp in fine-tuning the circuit parameters until the requiredspecifications are met. For example, if the zero-voltage turn-off switching property for S2 is not satisfied during mode 4of operation, then M12 should be given an incrementalchange until this property is satisfied.

It is found that average current stress on additionalswitching devices such as S2, D1 and D3 are negligibly small.From the simulation study on the proposed circuit with theparameters given in mode 4, the average values of currentflowing through S2, D1 and D3 are found to be 0.46 A, 0.3 Aand 0.26 A, respectively, and their peak values of currentsflowing are found to be 24 A, 2.5 A and 8 A, respectively(see Fig. 4). Thus S2, D1 and D3 are selected based on their

a b

c d

Fig. 8 Simulation resultsa L1 is increased from 281mH to 321mH in steps of 20mH

b L2 is increased from 29mH to 49mH in steps of 10mH

c L3 is increased from 43.8mH to 73.8mH in steps of 15mH

d During regeneration by taking Io 50 A

Table 1: Effect of parameter variation on circuit perfor-mance

Circuit

parameter

Zero-voltage

time period

Tzero

Clamp voltage

level Vs vCFAvailable

zero-voltage

turn-off

period for S2

k12 m decreases negligible

change

increases

k13 m negligible

change

decreases increases

k23 m negligible

change

increases negligible

change

CRm increases decreases decreases

L1 m increases decreases decreases

L2 m decreases marginal

increase

marginal

increase

L3 m negligible

change

increases negligible

change



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peak current rating and the maximum voltage they need toblock. The maximum voltage that S2 needs to block isduring mode 7 of operation and is given as

Vmax;blocking;S2 Vs vCF M12 di1

dt

mode 7

26

The value ofM12 di1=dt during mode 7 of operation isnegative and is of the order of 3040 V for the circuitparameters given in mode 4. It can be easily verified from

Fig. 4 that the value of di1=dtmode 7 % 357143 A s1

,which gives the product M12 di1=dtmode 7 29 V ( forM12 81:24mH). Thus the maximum voltage stress on S2is marginally higher than DC-link clamp voltage levelVC Vs vCF. This increased voltage stress on S2 beyond

the DC-link clamp voltage level can be considered negligiblysmall.

The maximum reverse voltage appearing across diode D3also occurs during mode 7 of operation and is given as

Vmax;reverse;D3 VsM13 di1

dt

mode 7

27

Thus the maximum reverse voltage across D3 alwaysremains marginally less than the DC-link clamp voltagelevel. It can be observed from Fig. 4 that the maximumreverse voltage across diode D1 occurs during mode 3 and isequal to the DC-link clamp voltage VC Vs vCF.

The block diagram of the control circuit for soft-switchedPWM inverter control is shown in Fig. 9. Depending uponthe PWM inverter modulation strategy, the PWM com-mand generator generates the switching signals for theinverter devices. The change in the conducting state of anyinverter switch is first detected by the edge detector, whichgenerates a turn-on signal to the auxiliary switch S2. Thisinitiates the resonant cycle. The pulse width of the signalapplied to the gate ofS2 is equal to sum of the time requiredfor the DC-link voltage to reach zero and TZero. Tosynchronise the change in the conducting state of the

inverter devices with the zero link voltage instant, three

CommandGenerator(Phase A)

PWM

CommandGenerator(Phase B)

PWM

CommandGenerator(Phase C)

PWM

Link

Detector

Edge

Detector

MonoShot

DFlip

Flop

DFlip

Flop

DFlip

Flop

Q

Q

Q

To Phase A

Switches

To Phase B

Switches

To Phase C

Switches

Switch S2To Auxiliary

V

D

D

D

CLK

CLK

CLK

Q

Q

Q

Sa

Sb

Sc

Sd

Se

Sf

Fig. 9 Control circuit for synchronising inverter switching withzero DC-link voltage instants Fig. 10 Simulated plots of vCF andiCF during starting

Table 2: List of SABER templates used for simulating various circuit components and power dissipated in them for differentvalues of inverter switching frequencies

Circuit component SABER

template

Template properties/

comments

Power dissipated

with SPWM, 5 kHz

Power dissipated

with SPWM, 6 kHz

Power dissipated

with SPWM, 7 kHz

L1 (281mH, air core) l r

220mO 9.1 W 9.81 W 10.9 W

L2 (29mH, air core) l r 80 mO 0.52 W 1.86 W 1.91 WL3 (43.8mH, air core) l r 120mO 0.18 W 0.45 W 0.55 WSwitch S2 irg4ph50u Inbuilt Saber Template

Analogy Inc.

4.5 W 9 W 10.5 W

Diode D1 mur10150e Inbuilt Saber Template

Analogy Inc.

0.21 W 0.33 W 0.6 W

Diode D3 mur10150e Inbuilt Saber Template

Analogy Inc.

0.84 W 2.59 W 4 W

Inverter switches irg4ph40u Inbuilt Saber Template

Analogy Inc.

48 W 52 W 60 W

Free-wheeling

diodes across

inverter switches

dp Inbuilt Saber Template

Analogy inc.

5.2 W 5.7 W 6.2 W

Total 68.55 W 81.74 W 94.66 W

Load and source parameters are: RL 19.68O, LL 63.94O, Vs 600V, Power factor 0.7, Output power 3.6kW



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D-type flip-flops are used. The switching signals generatedby the three-phase PWM command generator drive the

D-input pins of the flip-flops, and the output pins Q and Qdrive the corresponding top and bottom switches of the

PWM inverter. When the link voltage reaches zero, thezero-voltage detector outputs a signal that is used to clockthe D-type flip-flops. Thus it synchronises the change in theconducting state of the inverter devices with the zero linkvoltage instants, so that the conducting state is changedonly at zero-voltage condition.

5 Simulation results

A simulation study of the proposed circuit with parametersgiven in the mode 4 was performed to verify the analysisand to predict the performance under various loadconditions. Simulation results for Io 50 A are shown inFig. 4. It is observed that the fall time of the link voltage isabout 533 ns. The zero link voltage condition, which isutilised for soft-switching of the inverter poles, is maintained

Fig. 11 Experimental resultsa DC-link voltage vCR (top trace, 200 Vper division), S2 gate driver

input signal (middle trace, 10 V per division) and current through L2(bottom trace 16 A per division)

Time: 5ms per division

b DC-link voltage (top trace 300 V per division), current through L2(middle trace, 10 A per division), and current through L1 (bottom

trace, 10A per division)


Table 3: Inverter efficiency for three different switchingfrequencies

SPWM carrier

frequency, kHz

Average switching

frequency of S2, kHz

% efficiency

5 30 98.09

6 36 97.72

7 42 97.37

Fig. 12 Experimental resultsa Current through L2 (top trace, 10 A per division), current through L1(middle trace, 10 A per division) and current through CF (bottom

trace, 10 A per division)


b DC-link voltage (top trace, 300 V per division), current through L1(middle trace, 5 A per division) and current through CF (bottom trace,

5 A per division)




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fundamental frequency of 50 Hz and modulation index of 1.The per-phase load parameters, DC-source value andSABER templates used for the simulation study are givenin Table 2. As L1, L2 and L3 were chosen to be air coreinductors, a linear inductor template with finite resistancewas used for simulation. If actual SABER templates areused, the average power dissipated in each circuitcomponent can be determined from the simulation results.These results are given in Table 2.

Once the total power dissipation in the entire circuit hasbeen found, the efficiency can be calculated. The efficiencyof the inverter for three different switching frequencies isgiven in Table 3. It should be noted that the calculatedefficiencies of the proposed soft-switched inverter, as listedin Table 3, are based on simulation results.

6 Experimental results

So that the simulated results could be validated, alaboratory prototype was built and tested under variousload conditions. The circuit parameters used for theexperimental study are given in the mode 4 description ofcircuit operation. Other circuit parameters are: Vs

300 V,

CF 5 mF, and the on-time of S2 2.5ms. Figures 11a12bshow the recorded waveforms under no-load condition.Figure 11a shows vCR , the gate signal of S2, and the currentthrough L2, and Fig. 11b shows vCR and currents throughL2 and L1. The clamp factor Kachieved was 1.3. Figure 12ashows the currents through L1, L2 and L3, respectively, andFig. 12b shows vCR , L1 current and current through CF. Itcan be observed from Fig. 11a, that the fall time ofthe link voltage is approximately 800 ns. The zero linkvoltage condition, which is utilised for soft-switching ofinverter poles, is maintained approximately for 700ns.The DC-link voltage rises is three distinct steps to reachclamp voltage level after a brief zero-voltage period. Thetime taken for the DC-link voltage to reach clamp voltagelevel after a brief zero-voltage period is approximately5.5ms.

It can be observed that there is fairly good match ofsimulated waveforms (Fig. 4) and those obtained from theprototype. In the experimental set-up there are strayinductances and capacitances that cause deviation fromthe simulation results. To demonstrate the PWM capability,a three-phase sine-triangle PWM command generator wasimplemented to control the six inverter switches. The outputof the soft-switched inverter is directly connected to three-phase induction motor whose parameters are given inTable 4. The sine-triangle PWM (SPWM) technique is usedcontrol the output voltage of the inverter. The frequency of

the carrier wave is maintained at 6 kHz. The measuredwaveforms are shown in Figs. 13ac. Figure 13a shows thelink voltage vCR , inverter lineline voltage and currentthrough L1. Figure 13a clearly shows that the change inlineline voltage is synchronised with the zero-voltageinstants of the DC link. The load current is sinusoidal,and the performance of the link is found to be satisfactory.

7 Conclusions

In this paper, a new circuit topology for a QRDCL soft-switching PWM inverter is proposed. It is a simple soft-switching topology that is easy to implement and control.The proposed circuit uses one additional switch to create

zero-voltage instants in the DC link. The maximum voltagestress on auxiliary circuit diodes is confined to the DC-linkclamp voltage level. Also, the resonant energy associated

with clamping is recycled. The proposed inverter config-uration is a solution to the problem of maintaining aseparate low-voltage DC source using a low-power DC-to-DC converter for clamping the DC link. It is shown that theextra resonant energy can be recycled, while the voltagestress on the clamping diode is maintained equal to the DC-link clamp voltage level. The introduction of magneticcoupling between three resonant inductors can minimise thedevice count. Various modes of operation and link wave-forms were analysed to reveal the soft-switching character-istics. Simulation and experimental studies were carried outto verify the proposed concept.

8 References

1 Divan, D.M.: The resonant dc link inverter a new concept in staticpower conversion. IEEE-IAS Annual Conf. Rec., 1986, pp. 648656

2 Divan, D.M., and Skibinski, G.: Zero switching loss inverters for highpower applications. IEEE-IAS Annual Conf. Rec., 1987, pp. 627634

3 Merterns, A., and Divan, D.M.: A high frequency resonant dc linkinverter using IGBTs. IPEC Tokyo, Japan, 1990, pp. 152160

4 He, J., and Mohan, N.: Parallel resonant dc link circuit a novel zeroswitching loss topology with minimum voltage stresses, IEEE Trans.Power Electron., 1991, 6, pp. 687694

5 He, J., Mohan, N., and Wold, B.: Zero voltage switching PWMinverter for high frequency DC-AC power conversion, IEEE Trans.

Ind. Appl.., 1993, 29, pp. 9599686 Jung, and Cho, G.: Novel type soft switching PWM converter using a

new parallel resonant DC link. IEEE-IAS Conf., 1991, pp. 2412477 Malesani, L., Tenti, P., Tomasin, P., and Toigo, V.: High efficiency

quasiresonant dc link three-phase power inverter for full-range PWM,IEEE Trans. Ind. Appl., 1995, 31, pp. 141148

8 Choi, J.W., and Sul, S.K.: Resonant link bidirectional powerconversion Part-I: Resonant circuit, IEEE Trans. Power Electron.,1995, 10, pp. 479484

9 Wang, K., Jiang, Y., Dudovsky, S., Hau, G., Boroyevich, D., and Lee,F.C.: Novel dc-rail soft switching three-phase voltage source inverter,IEEE Trans Ind. Appl., 1997, 23, pp. 509516

10 Divan, D.M., Malesani, L., Tenti, P., and Toigo, V.: Asynchronisedresonant dc link converter for soft switched PWM, IEEE Trans. Ind.Appl., 1993, 29, pp. 940948

11 Lai, J.S., and Bose, B.K.: High frequency quasi-resonant DC voltagenotching inverter for AC motor drives. Proc. IEEE Conf., 1990,pp. 12021207

12 Vassilios, G., and Ziogas, P.D.: An optimum modulation strategy for

a novel notch commutated three phase PWM inverter, IEEE Trans.Ind. Appl., 1994, 30, pp. 5261

13 Hui, S.Y.R., Gogani, S., and Zhang, J.: Analysis of a quasi-resonantcircuit for soft-switched inverters, IEEE Trans. Power Electron., 1996,11, pp. 106114

14 Chen, S., and Lipo, T.A.: A novel soft switched PWM inverter forAC motor drives, IEEE Trans. Power Electron., 1996, 11, pp. 653659

15 Jafar, J.J., and Fernandes, B.G.: A new quasi-resonant DC-linkPWM inverter using single switch for soft switching, IEEE Trans.Power Electron., 2002, 17, p. 1010

16 Jafar, J.J., and Fernandes, B.G.: A quasi-resonant DC-link PWMinverter for induction motor drive. In IEEE-IAS Annual Conf. Rec.,1999, pp. 19972002

17 Jafar, J.J., and Fernandes, B.G.: A novel quasi-resonant DC-linkPWM inverter for induction motor drive. In IEEE-PESC Conf. Rec.,1999, pp. 482487

9 Appendix

9.1 State equations during mode 4 of circuitoperations

i1t t4 23:2556 0:534888i1t4 0:465112i2t4 1:08022i3t4 0:0078125t t42 cos373683t t411:363 0:22726i1t4 0:22726i2t4 1:21087i3t4 cos3:72354 106t t411:89260:237852i1t4

0:237852i2

t4

0:130654

t4

sin

373683

t

t4

3:54682 0:106768 vCF sin3:72354 106t t4 2:63439 0:00224885 vCF 41561:1t t4 vCF 28



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i2t t4 26:7444 0:534888i1t4 0:465112i2t4 1:08022i3t4 cos373683t t46:68997 0:133799i1t4 0:133799i2t4 0:712902i3t4 cos3:72354 106t t433:4344 0:668688i1t4 0:668688i2t4 0:367315i3t4 sin373683t t4 2:088190:0628597vCF sin3:72354 106t t4 7:406220:00632232vCF 41561:1t t4 vCF

29

i3t t4 cos373683t t48:50709 0:170142i1t4 0:170142i2t4 0:90654i3t4 cos3:72354 106t t48:50709 0:170142i1t4 0:170142i2t4 0:0934603i3t4 sin373683t t42:65539 0:0799336 vCF sin3:72354 106t t4 1:88445 0:00160866 vCF 30

vCRt t4 45:4545 1066:96892 109 459:557 13:8338 vCF 2:09814 109

1526:41 1:30302 vCF 45:4545 106 2:09814 1096890:76 137:815i1t4 i2t4 75:703i3t4 sin3:72354 106t t4 2:09814 109 cos3:72354 106t t4 1526:41 1:30302 vCF 6:96892 109 2:54897 107i1t4t t4 4:77932 108i2 t4t t4 373683t t43 459:557 cos373683t t4 1472:29 sin373683t t4 29:4457i1t4 sin373683t t4

29:4457i2t4 sin373683t t4 156:891i3t4sin373683tt413:8338 cos373683tt4vCF 31The expression for the area enclosed by current iCF i3during mode 4 is given as

iCF;area;M4 4:56936 10850 i1t4 i2t4 0:549308i3t4 sin3:72354 106t t4 4:55311 10715:6069 0:469806 vCF 4:56936 10811:0758 0:00945482vCF 1 cos3:72354 106t t4 4:55311 107

cos

373683

t

t4

15:6069

0:469806 vCF

sin373683t t450 i1t4 i2t4 5:32814i3t4 32

9.2 State equations during mode 5 of circuitoperations

i1t t5 12:0485 0:759029i1t5 0:240971i3t5 1:31032 106t t5 0:045118 vCRt t5 0:000976563t t52 2183:84t t5 vCF cos1:62534 106t t50:240971i1t5 0:240971i3t5 12:0485 sin1:62534

106

t

t5

1:24596

0:00861631 vCRt5

0:0065397 vCF 33

i3t t5 37:9515 0:759029i1t5 0:240971i3t5 1:31032 106t t5 0:045118 vCRt t5 0:000976563t t52 2183:84t t5 vCF cos1:62354 106t t50:759029i1t5 0:759029i3t5 37:9515 sin1:62534106t t5 3:92462 0:0271404vCRt5

0:0205993 vCF 34

vCRt t5 vCRt5 0:013655410589:3 73:2297 vCRt5 55:5806 vCF 45:4545 1060:00016276t t54:36557 1011 t t52 3:00418 1010102400 2048i1t5 2048i3t5 sin1:62543 106t t5 3:00418 1010 cos1:62534 106t t5

10589:3

73:2297 vCR

t5

55:5806 vCF

35

The expression for the area enclosed by current iCF i3during mode 4 is given as

iCF

;area;M5 3:00418 101077724:6 1554:49i1t5 1554:49i3t5 sin1:62534 106t t5 3:00418 10108037:62 55:5834 vCRt5 42:1837 vCF 1 cos1:62534 106t t5 0:0000813802t t5466347 9326:95i1t5 2961:05i3t5 8:05061 109t t5 277:205vCR t t5 2t t52 1:34175 107t t5 vCF 36


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