3D VLSI OVERVIEW, LETI COOLCUBE TM TECHNOLOGY M. Vinet P. Batude, C. Fenouillet-Beranger, O. Billoint, O. Rozeau, G. Cibrario, L. Brunet, S Kerdiles, JM Hartmann, H. Sarhan, I. Rayane, F. Deprat, A. Fustier, J-E. Michallet, O. Faynot, O. Turkyilmaz, J-F. Christmann, S. Thuries, F. Clermidy
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3D VLSI OVERVIEW, LETI COOLCUBE TECHNOLOGY · 3D ClockTree Full 3D Routing in one runwith Timing Closure Inter-TierPower Supply Distribution Tier-Specific ProcessCorner Specification
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3D VLSI OVERVIEW, LETI COOLCUBETM TECHNOLOGY
M. Vinet
P. Batude, C. Fenouillet-Beranger, O. Billoint, O. Rozeau,
G. Cibrario, L. Brunet, S Kerdiles, JM Hartmann, H.
Sarhan, I. Rayane, F. Deprat, A. Fustier, J-E. Michallet,
O. Faynot, O. Turkyilmaz, J-F. Christmann, S. Thuries, F.
Clermidy
| 2
Common human sense,
When we miss space
SST 2015 April 23rd| Maud Vinet
| 3
Common human sense,
…we pile up
SST 2015 April 23rd| Maud Vinet
| 4
Common human sense,
Traffic jam Need for short distance
communication pathsSST 2015 April 23rd| Maud Vinet
| 5
Context
0
5000
10000
15000
20000
0,35um 130nm 65nm 28nm 14nmProcess Node
Number of Design Rules(Extracted from PDKs)
0.00E+00
1.00E-13
2.00E-13
3.00E-13
4.00E-13
5.00E-13
6.00E-13
28nm 14nm 10nm 7nmProcess Node
Delay of a single wire of the same circuit (s)(extracted from internal DRMs)
Scaling is about to
be more and more
complex
Scaling is about to
be more and more
complex
Back End
performances are
decreasing
Back End
performances are
decreasing
TSV [1]
Size : 10x10um2
Pitch : 30um
HD-TSV [1]
Size : 0,85x0,85um2
Pitch : 1,75um
Cu-Cu [1]
Size : 1,7x1,7um2
Pitch : 2,4um
3D-VLSI (28nm) [2]
Size : 0,05x0,05um2
Pitch : 0,11umE
ne
rgy
Eff
icie
ncy
En
erg
yE
ffic
ien
cy
3D Interconnect Technology3D Interconnect Technology
[1] Patti B., « Implementing 2.5D and 3D Devices », In AIDA workshop in Roma, 2013.[2] Taken from internal Design Rules Manual
Today’s focus: fine grain 3D Physical implementationToday’s focus: fine grain 3D Physical implementation
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| 6
Agenda
CoolCubeTM
unique features
Opportunities
CoolCube TM
enablers
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| 7
Technological implementation of
3DVLSI
Bottom layer processing with
plugs down to the CMOS.
Bottom layer can be any
technology, for simplicity, in
these schematics, bulk (Finfet or
planar) technology has been
represented.
Fabrication of the inter level
metal line to ensure short
distance connexion with bottom
layer.
High quality top film transfer by
molecular bonding.
Lithographic alignment precision between tiers
P. Batude et al, VLSI 2011
CoolCubeTM technology
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CoolCubeTM contacts integration
scheme
3D contact pitch and dimensions close to planar
Δh ~ 100 nm
3D contact process similar to 2D planar W plug process
• Contact in an oxide with a slightly higher depth
• No keep out of zone
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Highest density of vias between tiers
0.01 0.1 1 10
0.01
0.1
1
10
Alig
nmen
t acc
urac
y (µ
m)
3D contact width (µm)
SOI TSV
BULK TSV
sequential
65nm node
14nm node
[C]
[A,B]
[D]
[E]
D=5.000.000/mm2
D=10.000/mm2
D=100.000/mm23D TSV
D> 100.000.000/mm 2
Sequential 3D
At 14nm node, available via density D>100 million vias/mm2
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Enablers
CoolCubeunique
features
Opportunities
CoolCube TM
enablers
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Advantages of 3D VLSI: reduction of
interconnect length
For n stacked layer the global interconnect path
may be reduced by √n
Reduction in interconnect length
• Faster circuit speed
• Reduced power consumption
Eventually lower cost
Smaller physical size
Source: H. Hua, IEEE 2006
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CMOS over CMOS
Power, performance, area, cost metric
Decreased delay and power due to shorter wirelengths
� reduced wire capacitance
� less signal buffering requirement
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3D FPGA: 14nm planar FDSOI versus
2 stacked 14 nm FDSOI levels
O. Turkylmaz et al., DATE 2014
Partitioning SRAM memory on bottom level, logic on top
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3D FPGA: 14nm planar FDSOI versus
2 stacked 14 nm FDSOI levels
1.5 node gain without scaling
O. Turkylmaz et al., DATE 2014
� Average gain benchmark
for 6 circuits/ planar
� Area gain=55%
� Perf gain = 23%
� Power gain = 12%
Energy-delay product of FPGA benchmark circuits
for 2D and 3D architectures
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| 15
CoolCube™ for high mobility channel
Opportunities
P. Batude et al., VLSI 2009
Independent process for high mobility materials
Source: T. Irisawa et al., VLSI 2013 (AIST)
EU initiative “COMPOSE3”
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CoolCube™ for heterogeneous co-
integration
Opportunities
Highly miniaturized pixels Gaz sensors (NEMS with CMOS)
� Independent optimization of each level
� Proximity between stacked functions (signal/noise ratio)
P. Coudrain et al., IEDM 2008
First step to high level of integration for interconnectivity