3D R G B LED Cube

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3D RGB LED Cube

Group 15 Luke Ausley BSEE

Joshua Moyerman BSPE Andrew Smith BSPE

Sponsored by Stellascapes

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Motivations and Goals

• Desire to discover innovative methods for improving LED cube design

• Project aligned with individual group member’s expertise and interest

• Diverse design aspects

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SpecificationsTitle QTY Units

Cube Resolution 10 x 10 x 10 Voxels

LED Lattice Dimensions 50 x 50 x 50 cm

Outer Dimensions 60 x 60 x 70 cm

Pitch 5 cm

Refresh Rate 100 hz

Animation Rate 25 fps

Color Space 24 bit

Operating Voltage 120 V

Operating Current 1 A

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High Level Diagram

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High Level Work Distribution

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Hardware Block Diagram

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Key Hardware Design Decisions• Multiplexing• Control Hardware Structure

o Joint FPGA/MCU

• LED Driver Board o TI LED Driverso MOSFETs

• PCB Layouto Three separate two-layer PCBs

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Driver Design

• Two identical driver boards will be used to reduce power dissipation and circuit board size and isolate faults.

• TLC5948A LED Drivers• SI4101DY-T1-GE3 P Channel Mosfet• Individually fused planes

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Driver Schematic

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Driver PCB Layout

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Control Design

• FPGA and MCU based control system• FPGA to handle interfacing to driver circuitry

due to timing constraints• MCU to handle user interfacing via ethernet• FPGA and MCU will work together to

complete the task of driving LEDs

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FPGA and MCU Choice• PIC24HJ265GP206A Microcontroller

o Low cost, 16 bit architectureo Stellascapes existing experience with Microchip line of

productso Readily available ethernet interface with TCP/IP Stack

• Xilinx XC3S200AVQ100 Spartan 3A FPGAo Team’s familiarity with Xilinx ISE from Digital Systems Lab

worko Stellascapes interest in integrating FPGA with PIC24

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Control Schematic

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Control PCB Layout

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PCBs Interfaced

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Firmware - MCU

• Developed using C (6000 lines of code)• Microchip MPLAB X IDE• Microchip XC C Compiler• Microchip’s freely available TCP/IP Stack

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Firmware - FPGA

• Written in Verilog (1600 lines of code)• Xilinx ISE 14.5 Development Environment• Simulated using ISim

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Firmware Update Cycle

• Updated FPGA code to be loaded via MCU Ethernet connection

• FPGA bitstream stored on 8Mb EEPROM• MCU to control loading of FPGA Device

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Power SupplyAblecom SP502-2S

Output Voltage 5 V

Max Current 30 A

Input Voltage 100-240 V

Input Frequency 50-60 Hz

Max Input Current 10 A

Dimensions 7x4x2 in

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Construction

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Construction

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Prototype

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Software

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Software Design Choices

• Developed in Microsoft Visual Studio Environment (3200 lines of code)

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Software Block Diagram

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Animation Class Diagrams

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LED Animation GUI• 12 distinct animations• 3 distinct color modes

• User Input• HSV Scroll• Random

• 24-bit color palette• Brightness scaling

Communication• E1.31 Streaming

Architecture for Control Networks (sACN)

• Up to 512 color channels/packet

• Animation data sent over 6 packets

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Simulators

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Hardware Simulator

Scrolling TextUser Input Color

Sine RippleRandom Color

Rotating Sine HSV Scroll Color

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Firmware Simulator

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BudgetItem Qty Total Cost

LEDs 1200 $350 - Sponsored

Construction Materials N/A $100

PCBs 3 $200 - Sponsored

LED Drivers/MOSFETs 20 ea $75

Power Supply 1 Group Owned

Wire 1200ft $100

Assorted Components N/A $100

Estimated Overall Total $925

Estimated Amount Spent (Non-sponsored) $375

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Challenges

• Production delays• FPGA/Microprocessor interfacing

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Successes

• All components operational in standalone• Mature black-box software• Timing specs met• Proof of concept with moderate confidence• Functional prototype

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Special Thanks

• Stellascapeso Sponsorship

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Questions?