3D Packaging May 2012 (No 23)

3DPackaging

Magazine on 3DIC, TSV, WLP & Embedded die Technologies

ISSUE N°23MAY 2012

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F r e e s u b s c r i p t i o n o n www.i-micronews.com

INDUSTRY REVIEW2.5D interposers look increasingly

like the near term, high performance

solution

ANALYST CORNERAre silicon

interposers “luxury” solutions?

WHAT’S INSIDE? Texas Instruments’

embeddeddie package

3D Packaging…in 3D!

The world of device manufacturing is in a rapid state of transformation—and 3D & wafer-level packaging is a game-changer of unprecedented scope. To meet the needs of cost, performance and size, multiple solutions are emerging for wafer-level packages encompassing several technology platforms.

The result? An entire global supply chain dedicated to 3D integration of IC chips is emerging, as the semiconductor IC community has grown to accept 3D integration as an alternative to scaling. The question is no longer why 3D? Today, the question is how, where, when 3D…and with whom? To become a part of the 3D development vanguard, it's imperative that you meet and engage the emerging innovators at Connect in 3D. Collaboration SummitsSM are unsurpassed in delivering hours of networking opportunities in a variety of pre-scheduled, formal and informal formats with a minimum of 'pre-packaged' content. Need proof? Look no further than our unprecedented 100% satisfaction ratings from previous attendees.

More Than 600 Meetings Over Two Days! The Connect in 3D Collaboration Summit, presented by Yole Développement, the world leader in technology information, provides the freedom to meet, learn, talk, and collaborate in a casual environment. Meet with the leaders from across the 3D packaging value chain for two full days. Your time will be fi lled with “speed-dating-like” sessions and more in-depth one-on-one meetings—meetings that you control.

Mark your calendar today!For information and to register, visit www.Connect-in-3D.com or contact Brian Perkins, [email protected], +1 207-799-1356.

Finally, a One-on-one Networking Event for 3D & Wafer-level Packaging

OCTOBER 31–NOVEMBER 1, 2012 WESTIN MISSION HILLS RESORT & SPA PALM SPRINGS, CA

E D I T O R I A L

Home insurance building

Every time I fl y over any metropolis, with roads and buildings neatly

laid out, I see a giant circuit board. I suspect you do too: CPU and

memory, switches and diodes, MOSFETs, heat syncs, capacitors,

resistors and nameless IC’s stretching as far as the eye can see…

In places like the western US, with less constraint on space, the city

“circuit board” expands without limit. More constrained urban centers

on the other hand, had to resort to the vertical dimension out of necessity.

These urban 3D stacks were at fi rst limited in their “Z” axis by cost and

technology: how to design and build them and how to transfer reliably

between levels. A critical piece came with the invention of effi cient and

reliable Through Building Vias (TBV’s) which unleashed the ability to

stack higher than ever before. Equipped with the TBV’s, fi lled of course

by Mr. Otis, the modern skyscraper was born. Skylines around the world

were forever changed.

To be sure, not just one element made it happen; new materials and

techniques had to be developed. And it took time. Elevators were

invented long before Otis made them trusted and mainstream (Louis XV

had one in Versailles some 150 years before the world’s fi rst skeleton

frame skyscraper appeared in Chicago). Lots of other things had to fall

in place. Building materials and methods changed dramatically, systems

and business models to support these had to be created. The motivators

and drivers varied, but in the end what was once thought to be exceptional,

became something of a norm.

While this may not be a perfect analogy, the fact is IC design has been

undergoing what may be among the most radical changes in its history.

Driven by several motivators and being enabled by key building blocks,

some of which fi rst appeared many years ago, 3D structures are changing

the IC skyline.

When Yole Développement analysts started using the term

“Mid-End” nearly 5 years ago to describe this evolution it was a

vision. Today the emergence of a semiconductor “Mid-End” is a

real business focus. Examples of this transformation can be seen across

the semiconductor world. New business models, new designs, processes,

equipment and materials have been developed and are being perfected.

TSV’s are proving their reliability and building trust. Interposers,

far from new in semiconductor design, are proving their value.

The RTI and IMAPS packaging conferences in December and March were

striking for their feeling of normalcy. Rather than a topic for debate,

wafer scale packaging and 3D integration were the mainstream topic: no

longer why and when; but where, how and with whom. The change is

born of necessity and is here to stay, our goal at Yole Développement is

to help you understand and Connect in 3D.

Jeff Perkins,President,Yole Inc.

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M A Y 2 0 1 2 I S S U E N ° 2 3

PLATINUM PARTNERS:

…3D structures are changing the

IC skyline...

• IEEE Workshop on Low Temperature Bonding for 3D IntegrationMay 22 to 23 – Tokyo, Japan • ECTCMay 29 to June 1 – San Diego, CA • Semi Forum JapanJune 13 to 14 – Tokyo, Japan

E V E N T S

M A Y 2 0 1 2 I S S U E N ° 2 3

GOLD PARTNERS:

INDUSTRY REVIEW 6 2.5D interposers look increasingly like the near term,high performance solution

YOLE ASKS 10• Sorin eyes at advanced semiconductor packaging solutions

for differentiation

• Packaging at TI: a closer look

• CEA-Leti launches Open 3D™ initiative

ANALYST CORNER 17Are silicon interposers “luxury” solutions?

WHAT’S INSIDE? 20Texas Instruments’ embedded die package

EVENTS REVIEW 23

C O N T E N T S

4 3 D P a c k a g i n g

FROM I-MICRONEWS.COM

Stay connected with your peers on i-Micronews.com

W i t h 2 0 , 0 0 0 m o n t h l y v i s i t o r s , i-Micronews.com provides for Advanced Packaging area: current news, market & technological analysis, key leader interviews, webcasts section, reverse engineering / costing, events calendar, latest reports …

Please visit our website to discover the last top stories in Advanced Packaging:

> TEL acquires NEXX and expands its activities in 3DIC and advanced packaging technologies

> Altera and TSMC develop heterogeneous 3DIC test vehicle with 2.5D Interposer

> Molding Technologies: a closer look

(Courtesyof www.fotolia.com)

Highlights41 sessions covering all aspects of packaging:

36 technical sessions covering 3D/TSV, sensors and MEMS, embedded devices, LEDs, co-design, RF packaging, microfluidics and inkjet, in addition to conventional packaging topics

4 Interactive Presentation sessions and 1 Student Poster session

16 CEU-approved professional development courses

Technology Corner Exhibits, featuring 75 industry-leading vendors

Special Invited Sessions:

Panel Discussion Power Electronics: A Booming Market

Plenary Session Photonics: The Next Frontier?

CPMT Seminar Advanced Coreless Package Substrate and Material Technologies

Special Tuesday Session Next Generation Packaging and Integration: The Transformed Role of the Packaging Foundry

More than 300 technical papers covering:

3D/TSVAdvanced Packaging

Modeling & SimulationOptoelectronicsInterconnections

Materials & ProcessingApplied Reliability

Assembly & Manufacturing TechnologyElectronic Components & RF

Emerging Technologies

Conference Sponsors: Supported by:

13x13 mm silicon interposer,top view (Courtesy of ASE Group)

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M A Y 2 0 1 2 I S S U E N ° 2 3

3 D P a c k a g i n g6

2.5D interposers look increasingly like the near term, high performance solution

It’s by no means a defi nitive consensus, but there seems to be a developing view that interposers will provide both system cost and performance advantages near term for some applications, that both foundry and OSAT models for backside fi nish and assembly of interposers seem workable, and that the interposers will remain a useful solution for some applications even after the maturity of full 3D. But plenty of issues remain to be worked out - from user needs and pathfi nding tools to manufacturing technology and the ecosystem of partnerships and vendor relationships-to enable this major change in the traditional semiconductor manufacturing business.

Compelling benefi ts drive adoption at the leading edge, create ongoing market for interposers

One initial reason companies aggressively pursuing the bleeding edge of high-end 28nm and 20nm platforms see the most immediate benefi t in

interposers, is that they can break up one large die with very low yields into several smaller die with signifi cantly higher yields connected on an interposer, suggests Ron Huemoeller, Amkor SVP Advanced 3D Interconnect Platform Development. That approach can reportedly improve yields from levels in the teens for large die at the most advanced CMOS process nodes, to up to 30%-40% for the multiple smaller die, for signifi cant savings in both cost and time to market, as well as providing some power management options. But even as yields at these advanced nodes improve, interposers also provide the additional benefi t of allowing designers to strip out technologies with wider geometries like cache memory or analog logic that take up space and add mask count. “This is what really turned our heads”, says Huemoeller, noting the potential to eliminate two to four mask levels for signifi cant savings in cost and improvement in yields. He sees main demand coming from large package body, side-by-side stacking for network, GPU and CPU applications, on large silicon interposers.

Lower costs and faster time to market are helping drive some early adoption of 2.5D interposers at advanced nodes, where splitting up big die into several smaller ones improves yields, and the ecosystem is ready to handle the technology with only evolutionary change.

2.5 D silicon interposer,cross section

(Courtesy of ASE Group)

Perhaps it’s signifi cant that the big industry leading IDMs Intel, IBM and Samsung, who were talking about this technology openly a while ago, now have little to say, though they clearly have a lot of inside activity going on. “It’s a good sign that everyone is going silent,” says Tarun Verma, Altera Corp. Senior Director of Packaging Engineering. “We’re moving beyond pre-competitive path fi nding, and everyone is now working on their own solutions.”

“We believe that perhaps the time for silicon interposers has come,” says Bill Chen, ASE Fellow and Senior Technical Advisor, noting that it is becoming the top topic at ongoing industry events. With growing consensus that wide I/O memory stack with TSV will become available, the technical debate increasingly centers on which applications are right for 3D and for 2.5D, rather than whether there is room for both. “The silicon interposer is now a concept that people think can be implemented – it won’t be easy, but it is doable,” he notes. “It’s suffi ciently similar to the old idea of multichip modules that it’s not such foreign a concept.” Historically, multichip modules were manufactured by one company, so the idea of combining different die from different makers was hard to accept, and to implement. However, this is no longer such a diffi cult concept today for the fabless-foundry-OSAT community. Back then, test and rework posed major challenges, and both remain key challenges for the 3D and 2.5D manufacturing community today. Cost also is a top consideration, and inevitably there are major challenges associated with that too. For high volume manufacturing, an accelerated learning curve and yield success will be key to driving down systems cost.

The most important advantage of interposers is the ability to mix and match capabilities on the interposer, to build the different functions (processor, memory, analog, RF, etc) each in their own optimum silicon technology and then combine them, instead of integrating them all in a SoC, argues Matt Nowak, Qualcomm Senior Director, Advanced Technology. “However, quantifi cation and optimization of the benefi ts require detailed ‘pathfi nding’ analysis of specifi c product architecture/technology combinations,” he notes. The highest tiers of performance will adopt the technology fi rst, where cost is not a factor if advantages in form factor, signal integrity and power savings are realized, he concurs, pointing to computer servers, network processors, FPGAs, and high

performance graphics. And interposers will remain the best ongoing solution for some high-end functions in computer and network processing, where the signal and power benefi ts cannot be achieved with other existing technology.

Huemoeller expects interposer technology to move down to the core mainstream chip markets for desktops, tablets and TVs, because the main high volume chip makers will fi nd the direct integration of logic and memory on wide I/O interposers will be the lowest cost solution at the system

level for the logic/memory interface to reduce latency and reduce the power usage of driving memory. The next generation above 8000 pin HBM JEDEC memory standard is targeted at the center of the market. Though the interposer will add cost, it will ultimately allow the opportunity to reduce both the size and the number of layers in the motherboard, as well as the number of mask layers at the wafer level, for potentially signifi cant saving at the systems level. Even as full 3D TSV technology develops, high end logic makers are likely to keep using interposers, as they are reluctant to put the big vias into their leading edge logic chips, leery of the potential issues associated with low-k delamination and reliability, he argues.

The main driver is heterogenous integration, concurs Verma, who notes that multiple chips on interposers provides lots of capability in bandwidth expansion for Altera’s long term roadmap, and those of its partner TSMC, with which it developed its recently announced 3D test vehicle. “With our focus on communications infrastructure and high speed networks, in my view the interposer will continue to have a role even after full 3D development, especially for high performance applications. Our next generation product portfolio will use interposers in both catalog and customer driven products.”

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73 D P a c k a g i n g

“Interposer technology will move downto the desktop, tablet & TV markets as integration of logic and Wide I/O memory is shown to be cost effective at the system level while reducingthe latency and power usage driving memory,”expects Ron Huemoeller, Amkor Technology

Altera CoWoS wafer developed with TSMC,and an image of the Altera 2.5D device using

the process (Courtesy of Altera)

« System partitioning » interposers

3D integrated passive devices

3D LED silicon submounts

COARSE INTERPOSERSFINE-PITCH INTERPOSERS

MEMS & sensor 3Dcapping inteposers

Interposers for CMOSimage sensors

Miscellaneous interposers

Two types of interposers

(3D Silicon & Glass Interposers report, July 2012, Yole Développement)

Cost and re-thinking interconnect ecosystem remain key challenges

Interposer cost of course still remains a key challenge in most people’s minds, but perhaps even more challenging is re-thinking the working of much of the traditional package interconnect sector. “My 10,000 foot view is four big areas of need,” says Verma. “We have to fi rst fi gure out what customers want. Then there is the design environment –how to partition the design very early on in product design, which is very different from what we’re used to. Then there’s the manufacturing environment. And fi nally there’s enabling the ecosystem, where people will have to work closely together with partners in new ways. We need early path fi nding for this infrastructure, for the technology and for the viable business models at the same time… It will be an exciting two to three years of change for the foundries and the OSATs.”

Biggest challenge of all, says Nowak, remains software partitioning. Cost remains a major challenge for many applications, as well as the related issues of yield, testing, and identifying known good interposers.

Progress on meetingsome challenges

Interposer packaging costs themselves have come down sharply from fi rst introduction some 18 months ago when there was only one manufacturer, and the technology is still only in development. “We looked at interposer manufacturing costs quite hard, and determined customers’ target pricing could be achieved, both at entry level volumes and at future high volume

manufacturing, and at everything from mid-end graphics applications to high-end routers,” says Huemoeller. Of course, increasing volumes will help, as will improvements in the less mature process steps, like throughput for wafer thinning and thin wafer handling, and the temporary adhesive cost. He says general reliability for multiple die on a 100μm thick interposer with 10μm wide TSVs at 210μm pitch, logic at 40μm pitch microbumps with 25μm diameter passed level 4MRT, TC-B 1000

cycles, HTS 1000 hours and HAST 110°C, 85% RH 500 hours.

Front end fabs will most likely make interposers for now, since they have the depreciated 65nm tool sets, and decades of experience doing 1-2μm features at very high yields. However, that doesn’t mean the interposers will necessarily need 65nm technology. Those assets are simply available at present with excess capacity in some cases. First generation of interposer products will require 10μm wide vias and 40-50μm μbumps. To be competitive and hit the pricing targets with decent margin, suppliers will need to leverage depreciated assets rather than new investment, Huemoeller fi gures, and says Amkor has no plans to do this internally from scratch.

But there will likely be room for a variety of interposers. “With heterogeneous integration, there will be a potential market for interposers where the requirements for pitch and L/S are less demanding, such as within the analog and RF mixed signal arena,” says Chen, noting ASE has developed its own interposer technology for such markets.

Still up in the air is who will do the rest of the process, and how. One option being pioneered

by TSMC with Altera in its 3D test vehicle is for the foundry to do the whole process, attaching the chip to the interposer wafer and then attaching the chip-interposer unit to the package substrate. This allows for bonding the die to a perfectly fl at interposer surface before processing, avoids shipping thinned wafers, and eliminates all the vendor interface issues. But it also necessitates putting known-good die on untested interposers, until someone can fi gure out how to test the passive interposers, although the mature process technology used for interposers does have very high yields. An alternative approach is to ship the IC wafers to the OSAT before thinning, and let the OSAT do the thinning and passivation, then attach the die to interposers already bonded to package substrates. This also avoids having to ship thinned wafers, uses the existing infrastructure of assembly equipment, and allows the assembler to manage with any warpage or other issues caused by backside processes, such as passivation, that can impact assembly. Huemoeller says Amkor customers so far are all endorsing this approach of having the OSAT do the backside fi nish, so all back process quality and assembly are clearly the responsibility of the assembler, after wafer mapping clearly identifi es any front side defects. Chen notes that there is currently no one single answer for how best to divide the work fl ow of backside fi nish and assembly with the interposers. “Our market is an effi cient market, which means the most effi cient solution will prevail,” he says.

M A Y 2 0 1 2 I S S U E N ° 2 3

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“Our next generation product portfolio will use interposers in both catalog and customer driven products”, says Tarun Verma, Altera Corp.

(Courtesy of Amkor Technology)

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Si InterpT + DDR3T + Logic

Apps ProcessorT + SDR

GPU, CPU (28nm)

Smart Phone / Table (28nm)Interposer Required for some platforms

Interposer Required

Interp. Req'd

ProductionSince 2010

2011 2012 2013 2014 2015

Memory (DDRT)

Si InterposerT + Logic

Logic - Backside Metal

Die with TSV indicated by = T

Power Amp.

ASIC, FPGA (28nm)

Server, Custom Mem.45 & 32nm

TSV production intercepts - Amkor Technology view

I S S U E N ° 2 3 M A Y 2 0 1 2

“Certainly, every case will be different, even with the same players involved. In every case, players all need to look at what each can bring to the table and decide on the most effi cient way to divide up the task.”

“There are advantages to each different process fl ow, and proponents of both approaches will likely fi nd a way to make them happen. Technically both will work, with collaboration of the right parties,” says Verma. “The data on which is better changes monthly—it’s a moving target.” He argues that methods for testing interposers are under development, and possibly some methods developed to test substrates back in the era of multichip modules that were never much used could be resurrected. Putting components on in sequence, starting with the cheapest fi rst and doing intermediate test before putting on the more expensive components can also help avoid wasting known-good die. He fi gures both foundries and OSATs will ultimately be involved in parts of the interposer business, leading to economies of scale and lower cost. And OSATs may fi gure out how to make relative coarser interposers using the existing packaging infrastructure of depreciated back end equipment, which could have a major impact on costs.

Most of the components of the technology are in place, argues Verma, noting that though the EDA infrastructure is still far behind what’s needed for true 3D design, current technology is good enough to enable fi rst generation product. Plenty of manufacturing technology issues remain to reduce costs, but at least the issues are fairly clear, with headroom for improvement in thin wafer handling throughput and adhesives, testing technology, assembly of bumps at 40μm pitch and below, and underfi ll materials. The trend is towards compression bonding, for its big advantage of less thermal cycling of the materials, which can particularly impact the low-k dielectric layers, says Huemoeller. But even thermal compression bonding is not good enough for the increasing number of bumps, argues Vermaa. There’s a lot of concentrated effort in developing alternatives, including direct copper to copper bonding. Copper-copper bonding has been proven by Ziptronix and Intel, and will be needed at <10 micron pitch, but production issues of fl atness and co-planarity remain. Underfi ll is another key area of development with no resolution yet. Currently all types of underfi ll are in use for different applications. Pre-applied dry fi lms would eliminate issues with dispense

accuracy and volume, but voiding and other issues mean there is still work to be done. “There’s a lot of engineering going on in that space,” says Huemoeller.

Not a solution for the mobile market

Handset makers, however, apparently will go to direct memory on TSV-equipped logic without interposers. All the major handset makers say they plan to go to 3D TSV in the fi rst part of 2014, says Huemoeller, as they really need the speed and power performance improvements from 3D stacking. The focus for these customers is at 40 micron pitch, with 8-10 micron vias.

Foundry- based interposers are too expensive for high volume cost critical applications such as cell phones, argues Nowak. Practical options for reducing interposer cost will probably need to avoid processing in silicon wafer fabs due to the high equipment cost, with panel processing an alternative worth exploring. Though still in R&D, panel-based

interposers seem a better alternative than glass, concurs Verma, as glass still has technical challenges despite a lot of recent progress.

Coarse geometry interposers on glass or organic substrates will likely be limited to markets that Amkor does not plan to focus on, as integration of standard memory devices will require fi ne interposers. “We’ve really tried to shoe horn the higher end devices in, but it just doesn’t work,” says Huemoeller. “To get the new standard JEDEC HBM spec routed out you need <3 micron lines and spaces. If you move away from standard pitch to custom memory, it could be done, but then you have custom memory.”

Paula Doe for Yole Développement

William T. Chen, Fellow and Senior Technical Advisor, ASE Group Prior to joining the ASE Group, Bill was Director of the Institute of Materials Research & Engineering (IMRE), located in the National University of Singapore. Previously, Bill worked for over thirty three years performing various R&D and management positions at IBM Corporation, where he was elected to the IBM Academy of Technology. He is currently the co-chair of the International Technology Roadmap for Semiconductors (ITRS) Assembly and Packaging

International Technical Working Group. Bill has been an associate editor of the IEEE/CPMT transactions, and ASME Journal of Electronic Packaging, and has published extensively in the fi elds of microelectronics packaging and mechanics of materials.

Ron Huemoeller, Senior Vice President, Adv. 3D Interconnect Platform Development,Amkor Technology, Inc.Ron is currently Sr. Vice President of Adv. 3D Interconnect Platform Development at Amkor Technology. Prior to Amkor, Ron was Director of Engineering at Cray Computer Corporation in Colorado Springs, developing motherboards for state of the art Super Computers. He has been granted 58 U.S. patents. Ron holds a BS in Chemistry from Augsburg College with highest

honors, a MBA from Arizona State University and a Master’s in Technology Management from the University of Phoenix

Tarun Verma, Senior Director of Packaging Engineering, AlteraTarun is currently the Senior Director of Package Engineering at Altera Corporation, where he is responsible for the worldwide packaging activities ranging from development, design and manufacturing. He has been with Altera since 1990, holding various engineering and management positions. Prior to Altera, Mr. Verma worked for National Semiconductor Corp. as a packaging engineer. He holds an M.S. from the UC Berkeley and a B.S. from the Indian

Institute of Technology, Kanpur. Mr. Verma holds multiple U.S. patents in the area of packaging.

Matt Nowak, Senior Director of Engineering, VLSI Technology Group,Qualcomm, Inc.Matt responsibilities include leadership of Advanced Technology Initiatives such as Through Silicon Stacking, Advanced Memory technology, Design for Silicon, Spintronics, and “More than Moore” initiatives. He manages a combination of internal advanced development teams, supplier JDPs, and consortia and university projects. Matt has over 30 years of semiconductor

industry experience in a variety of technical, management, and business roles including wafer fab processes and devices, CMOS ASIC technology, compound semiconductor RF devices, package design and assembly, IC design tools and methodologies, technology transfer, foundry interfacing, and advanced technology.

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SORIN eyes advanced semiconductor packaging solutions for differentiation

Yole Développement: Can you please explain for us Sorin’s implantable Cardiac Rhythm Management product lines?

Olivier Carbonaro: SORIN designs, manufactures and markets medical devices that treat cardiac rhythm disorders: pacemakers (for bradycardia), Implantable Cardioverter Defi brillators (ICD) (for tachycardia) and Cardiac Resynchronization Therapy (CRT) devices (for heart failure). SORIN also designs and manufactures pacing leads that detect intracardiac signals and send electrical impulses to the heart.

For example, The SonR™system, our latest innovation, uses a sensor embedded in the tip of a pacing lead that measures the cardiac contractility and uses the signal to determine the best CRT device settings to improve the pumping effi ciency of patient’s heart.

YD: What are your primary drivers for technology choice, especially concerning micropackaging and assembly? Are these changing with time?

OC: Key drivers in our business are small size requiring great integration, longevity (low electrical consumption, low leakage current) and high reliability (proven technologies).

Testability during manufacturing cycle is also crucial. More recently, as in many competitive industries, cost effectiveness has become a real concern: how can we continue to bring the best possible medical technologies to patients at an affordable price?

YD: Among the latest available packaging technologies developed around higher volume applications (fan-in WLCSP and fan-out WLP, fl ip chip, 3D stacking with wire bonds or with TSVs, silicon and glass interposers, IC embedding in substrate, integrated passive devices), which ones do you consider the most interesting for your future devices? For what reasons?

OC: Current products are made of wire-bonding, refl ow soldering for SMD and fl ip-chip when appropriate. Because device size will always be

a concern for patients – especially for ICDs - we will continue to downsize our devices without compromising on performance and reliability. 3D SiP based on Passive Integration Connecting Substrate (PICS) and copper pillar has already been investigated at SORIN with promising volume savings and performance. Some investigations on fan-out WLP brought options to stack chips of various technologies and form factor and with adapted number of I/O for our application. Development time can match SORIN needs. We pay particular attention to the forthcoming developments of this technology, in particular the 2 sides RDL and TPV (Through Package Via). In any case, those technologies will require adaptation of our design environment, test strategy and equipments. Investment should remain acceptable with regards to SORIN production volumes.SORIN has less interest in the silicon/glass interposer because it will not bring a clear benefi t when considering our ASIC sizes and I/O counts.Embedded die and passive (PCB) and wafer-to-wafer stacking (TSV) raise the questions of yields, logistic approach and test strategy.

YD: Are there any medical-specifi c or Sorin-specifi c technology developments in microelectronic assembly and packaging?

OC: Future innovations, like leadless pacing, will require reducing device size by a factor of 5. The challenge will then be to adapt existing technologies to meet this requirement and demonstrate the reliability of the packaging and assembly for life-support applications.SORIN is taking part in several projects that are heading into this direction with industrial and academic partners such as 3D+, LETI, IPDIA and NANIUM.

YD: What are your preferred solutions for interconnecting components in your products?

OC: Standard refl ow on ceramic (High Temperature Cofi red Circuit - HTCC) substrate has been used for many years in the pacemaker dealing with low voltage signals. This well-known technology brings expected reliability level. HTCC substrate has also been used for high voltage applications, but the trend

Olivier Carbonaro, manager of the Electronics Design and Development group in the CRM division of SORIN, shares with Yole Développement his vision of which, how and when advanced semiconductor packaging solutions can and shall be used in Sorin’s implantable medical devices

Olivier Carbonaro, Manager of the Electronics Design and Development group in the CRM division, SORIN

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“We will continue to downsize our devices without

compromising on performance and

reliability,” explains Olivier Carbonaro

is to replace it with High Density Integration PCB, or HDI PCB, (fl ex and rigid fl ex) mixing low voltage signals with high voltage/high current tracks.Flex and Rigid-Flex bring more options for volume optimization and low track resistance for high current, but extensive use of this technology is bound to achieving steady quality lots. We are working hard with suppliers to achieve this.

YD: Are we going to see more sensors and RF in implantable devices? What are the specifi c constraints of these devices for implantable medical devices?

OC: RF is today a standard for implantable defi brillators and will be extended to pacemakers in the future. The range of potential applications and connection with e-Health systems is infi nite and will boost developments in the coming years. From a packaging/assembly standpoint, efforts should be continued to decrease losses and consumption.

The numbers of Bio-Sensors will increase as implantable devices will include additional diagnostics capabilities. Implanting electronic sensors will bring new constraints:

biocompatibility of the packaging, small size to be embedded at the tip of the pacing lead, sensitivity (low level physiological signals) and power consumption. MEMS fast-growing technology is probably one of the solutions that will help us deal with the above mentioned constraints.

YD: What is your vision of implantable electronic devices in 2020? Are we likely to have more of them in our bodies? What are the limiting factors to wide adoption?

OC: Implantable active devices will be more communicating, will address a larger number of diseases and include more diagnostic features expanding beyond cardiovascular indications. They will be smaller, easier to implant and will drive the implant procedure costs down.Less invasive devices- patients will not accept having several implantable devices in their body - improved healthcare effi ciency and cost and device data integration with EMR are the keys for success.

YD: You recently changed over your industrial strategy, by insourcing back assembly and packaging operations. Can you please explain to our readers the reasons for doing so?

OC: SORIN aims at producing its devices in-house. High integration level in our devices and high reliability has been achieved through a strong relationship between design and process engineers. A good knowledge of the production process associated with a quality system to guaranty that any device leaving our warehouse is perfect is mandatory in our business.

Emerging technologies will somehow change the way added value is brought to the product. Responsibility sharing between suppliers and OEM will be renegotiated, but ultimately SORIN will continue to offer this high standard of service to patients and physicians.

www.sorin.com

I S S U E N ° 2 3 M A Y 2 0 1 2

Olivier Carbonaro, Manager of the Electronics Design and Development group in the CRM division, SORIN.In addition, he is project director of the new technical platform from which will come the future SORIN pacemakers and implantable defi brillators to be launched in 2015. He graduated as an engineer in micro-technologies specialized in automated systems.

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Y O L E A S K S

Packaging at TI: a closer look

Yole Développement: Devan, there are so many advanced packaging choices now a days, can you share with us how packaging decisions are made at TI?

Devan Iyer: At TI, we see packaging as an integral part of the design process and a strategic differentiator in our products. We have a very broad packaging portfolio to meet the requirements of our analog, embedded processing and wireless customers. These customers are designing for many applications ranging from medical and automotive to consumer electronics, communications infrastructure and many more. Some are looking for miniaturization, 3D integration and board level reliability. Others need high performance and high power. Cost is also a factor across all applications. As I have noted previously, each package has a “sweet spot” combination of cost, performance, form factor and reliability.Every organization in TI from packaging, assembly operations, manufacturing and our product design teams in our business units collaborate to defi ne the technology, cost and competitiveness for each packaging solution. This collaboration and decision-making occurs early in the process, which is really the key to how we make the right packaging decisions at TI.

YD: It appears that TI has been focusing on low power as a product driver. Can you expand on that for our readers?

DI: Delivering low power and effi ciency is a driver in all of our products, and that extends to semiconductor packaging. Our MicroSIP™ packaging technology is example of one of our

packaging innovations at work today in one of our latest DC-DC converters, the TPS6262. This product supports up to 600mA load current, and allows the use of low cost chip inductor and capacitors. MicroSIP technology gives designers the ability to embed silicon into the printed circuit board to maximize board space in their designs. YD: Copper pillar has certainly been a recent TI thrust. Can you share with us how that program started at TI and what we can expect in the future? What applications seem best suited for this technology?

DI: TI’s fi ne pitch copper pillar fl ip chip technology provides game-changing benefi ts for the industry by shrinking the bump pitch from 150um to 50um. The technology was jointly developed with Amkor Technology, and we qualifi ed and began production on the technology in 2010. It’s gained a tremendous amount of momentum and adoption, as we surpassed 100 million units shipped earlier this year. It’s ideal for handheld, high performance, low power applications, and is used in some of TI’s application processors, DSPs and power management products. YD: Many of our readers are closely following the emergence of 2.5D/3DIC TSV technology. While there has been public comment from TI that they are working internally on 3DIC, TI has chosen to remain under the radar on such programs. Is there anything you can tell us about what’s going on in 3D inside TI?

DI: We helped to pioneer 3D packaging technologies as one of the fi rst to market with stacked die and

Devan Iyer details the broad variety of Advanced Packaging available from TI.

Dr. Devan Iyer, Director of Worldwide Semiconductor Packaging operations, TI

Applications of Low Power Rf Packaging (Courtesy of Texas Instruments)

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package-on-package (PoP) devices, and we’ve experienced broad market acceptance of these technologies. Our efforts in 3D extend to the area of TSV, as the technology will continue to need more chip integration and performance, enabling our customers to integrate more functionality into their future products and essentially do more with less.

We continue to assess the viability of the technology, working internally and externally and we are collaborating with our TI business partners and customers to determine when and where it makes sense to integrate the technology into our roadmap. We believe that TSVs can improve IC integration and performance through high density, low inductance and low capacitance direct connections between chips in the stack. In addition, new memory-to-core bus architectures, high speed graphics links and analog integration in the stack will be possible at higher speeds, offering lower power dissipation.

YD: Can you share what issues remain to be resolved in 3DIC technology?

DI: There are still many challenges to resolve. These include thermal challenges which are

diffi cult to solve cost-effectively from the system perspective. Die stack and system design challenges to minimize reliability issues, and 3D modeling and design tool improvements are still needed. Co-design also becomes more critical in the TSV realm.

YD: Does TI see a use for silicon Interposers?

DI: Interposers provide a useful packaging solution when there is a need to reduce large die with more fl exible silicon node alternatives. This can help to address defect density challenges associated with these larger die solutions. In addition, full CMOS TSV integration may not allow the necessary time to market execution, and interposers can provide a transitional solution. TI continues to look at the wide range of device requirements where this type of solution may provide an advantage.

YD: Is TI considering Fan Out Wafer Level Packaging? What issues remain with fan-out packaging?

DI: There are a number of reasons to consider fan-out FOWLP. The fi rst applications for fan-out resulted from the need to create a FOWLP package and having insuffi cient space based on silicon area for the number of interconnects. This solution found traction in the industry for baseband devices and has expanded to additional devices. However, the infrastructure of producing a fan-out WLP on a wafer platform with wafer processing results in a relatively high cost and limits opportunities. As the infrastructure develops to both reduce

the cost/price and add capability such as multiple die and stacking, this technology becomes more interesting. TI and the industry are working on packaging solutions in the multi die/stacking arena to improve electrical performance, reduce package dimensions, manage warpage and cost – all while incorporating advanced silicon node CMOS devices, analog devices, discretes and MEMS. A few examples include packaging for processor top memory for the smart phone/tablet market; and SIP (system in package) to perform system-level functions such as power supply or integrating a sensor with logic. This space has competing technologies that include PoP, 3D IC, 2.5D interposers and embedding die technology.

YD: What do you see as the future of PoP versus TMV (through mold via) PoP?

DI: Package-on-package (PoP) was the fi rst generation of stackable package offerings that gave us the ability to stack a memory on top of a logic based device. TMV is an extension of PoP which enables us to address package warpage issues. Moving forward, end applications will drive the type of PoP solutions our customers need, but TI anticipates both will continue to be used.

YD: Your thoughts on chip embedded packaging? Will we be seeing more packages such as the MicroSiP package? What other applications can you tell us about?

DI: We are seeing broad acceptance of our MicroSIP™ products in the industry. The mobile market is where the technology was used fi rst, but we’re seeing interest in the technology for a wider range of applications, due to the size reduction, performance enhancements, and ease of use.

YD: Thank you Dr. Iyer for sharing your thoughts with us.

www.ti.com

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Attributes of fi ne pitch copper pillar bumping (Courtesy of Texas Instruments)

TI’s Embedded MicroSIP entering HVM (Courtesy of Texas Instruments)

Dr. Devan Iyer, Director of Worldwide Semiconductor Packaging operations, TIIyer is a twenty fi ve year veteran in semiconductor backend of line, packaging and test. He joined TI in 2008 and currently serves as Director of TI’s Worldwide Semiconductor Packaging operations.

High volume example: MicroSIPTM using Embedded PicoStarTM

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14

Y O L E A S K S

CEA-Leti launches Open 3D™ initiative

Yole Développement: Could you present to our readers the concept of Open 3D, its environment as well as the kind of service it proposes?

David Henry: Open 3D is a new platform started by CEA-LETI in order to propose 3D-proven/reliable/fully-developed technologies to our academic and industrial customers.The idea is to give our partners access to these technologies via a light R&D investment and short cycle time. Open 3D proposes a global offer, including 3D design, technology, electrical tests, and also packaging with a partner. Our current catalog includes a 3D design kit, Through Silicon Vias (TSV last), Redistribution layer (RDL), Under Bumps Metallurgy (UBM), interconnections - chips-to-chips (C2C) and chips-to-package (C2P), with micro-bumps & bumps, components stacking, and specifi c electrical test structures. These technologies are customizable and adaptable to the existing design of the customer’s device.Open 3D operates in CEA-LETI 200mm and 300mm clean rooms and facilities, and we are able to provide very small quantities of wafers for proof-of-concept approach, as well as larger production for prototyping or small-volume production.

YD: Could you provide technical details about the toolbox you have developed, and the typical end products or applications you’re targeting?

DH: The core of our offer is the TSV-last process fl ow. This TSV was initially developed at LETI a few years ago and transferred to industry for CIS application. Based on this mature technology, we

have developed a more aggressive TSV in terms of aspect ratios, and now we are able to provide 2:1 -- 3:1 TSV. The technology we developed for our TSV fl ow uses a copper liner with a polymer capping. The typical dimensions are between 40 and 80 μm diameter. Obviously, we also offer the complete toolbox in order to provide a complete 3D device, including RDL and interconnections.

In terms of targeted applications, the answer is: many! Actually, the Open 3D toolbox is comparable to a LEGO set: with the same bricks, you can build completely different toys. It’s exactly the same for Open 3D targets: we believe that we can serve very different markets, like imaging, bio/medical, aeronautics & space, defense & security, and probably a lot of other markets as well. We are planning to delve deeper into market identifi cation.

YD: Who are the typical customers (and their business models) you work with?

DH: We have a variety of customers: for example, we plan to work with niche markets customers, fabless, and academics/laboratories customers, as well as IDM and electronics components founders. One of our main targets are the innovative SME companies, because generally speaking they require advanced technologies for their products, but at times have diffi culties accessing those technologies through R&D projects. Thanks to our Open 3D platform, they can test these technologies on their products for moderate cost, and in a short time frame. With this in mind, our platform is open to any customer who would like to test our 3D technologies.

To illustrate the way we work, I’ll describe a project we recently executed for a customer, which involved a sensor for medical imagery. In the project’s preliminary phase, we had technical discussions in order to understand the customer’s requirements, and build the technical proposal. Next, and using our technical expertise, we prepared a proposal which included 3D design, technology achievement on functional wafers, and 3D technologies test. In the fi rst phase, we designed the 3D layers directly onto the customer-functional wafers by applying our design rules and using our 3D design kit. Next, we performed the 3D steps (TSV, RDL, UBM for instance) on the wafers, and tested them. Finally, we delivered the wafers to the customer for

New global offer includes design, layout, 3D technologies, testing and packaging on Leti platforms.

David Henry, Project Manager of the Open3D platform,CEA-LETI-MINATEC

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LETI technology platforms for 3D integration (Courtesy of CEA/Leti/G.Cottet)

the packaging part of the component. I should also note that we were able to provide the packaging of the 3D component through collaboration with our packaging partner. In the end, functional wafers were supplied in agreement with the initial schedule.

YD: Mid-end infrastructure is expected to change and evolve a lot this year, with several players leaving, and new entrants and business models emerging. What is your position in this complex ecosystem?

DH: Open 3D position in the supply chain is very clear: we are fully integrated into the R&D structure of LETI, and our goal is to fi ll the gap between R&D end-developments and mass production. Open 3D is a sort of “3D service” for mature 3D technologies -- the main idea is to decrease the time to market of our customers’ products, and to go from proof of concept to production with different models. The fi rst model is to produce a few hundred wafers at LETI. For a larger production, other models are possible: either production at a LETI partner/founder, or a technological transfer directly on the customer line.

YD: This issue of 3D Packaging magazine is dedicated to 2.5 interposer technology. Regarding numerous recent announcements in this fi eld, do you think this technology will be a long-term trend or just a solution to temporarily bridge the gap between 2D and 3D?

DH: My personal opinion is that I believe that 3D passive interposers are just a step before the real 3D stacking of active integrated circuits (ICs). Si interposers will be accepted by the industrial world if they solve performance issues (redistribution, stress, cost …) or if they propose new functionalities. The trend will be probably to add more functionality into the interposer like passive components, cooling systems, MEMS and maybe, CMOS components. In that case, we will join the 3D world with 2.5D modules made on 3D interposers migrating to true 3D stacks of ICs.

Nevertheless, other 3D experts have a different opinion, which is that 2.5D is not just a bridge to get us to 3D, but a legitimate stand-alone approach that will co-exist with 3D, sometimes even in the same package. For example, we can well imagine 3D stacked memories and a processor stacked on a passive interposer. The justifi cation for using an interposer to improve yield on large dies in advanced nodes will always exist. The newest nodes will always have yield challenges exacerbated by die size.

As of today, LETI sees a very high level of interest for 2.5D interposer technologies. It’s clearly a hot topic. But the open3D toolbox enables many more possibilities than just the design and manufacture of 2.5D interposer based solutions.

www.leti.fr

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David Henry, Project Manager of the Open 3D platform, CEA-LETI-MINATEC.Henry works for CEA-LETI-MINATEC at Grenoble in France. Leti is at the heart of the MINATEC innovation campus and is an applied research center for microelectronics, information and healthcare technologies. David Henry is currently project manager of the Open 3D platform which is an opening platform for 3D technologies towards academics & industrial customers.

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I S S U E N ° 2 3 M A Y 2 0 1 2

17

A N A L Y S T C O R N E R

Are silicon interposers “luxury” solutions?

A lot has been said and written about the performance improvements offered by Xilinx’s Virtex-7 2000 FPGA series, which is

built around the new "Stacked Silicon Interconnect Technology– SSIT". Detailed accounts of its unequaled FPGA computing bandwidth and low power consumption performance have been published by Xilinx over the past 18 months. As Xilinx is currently sampling these devices to its customers, we at Yole Développement thought this would be a good time to provide the readers of 3D Packaging with some cost insights concerning the very fi rst 2.5D package with silicon interposers for high-end digital applications. In this article, we’ll introduce the results of our manufacturing cost model of the Xilinx SSI solution, including not only the interposer itself, but also the assembly and packaging operations. The results are then compared with an alternative solution built with standard packages, after which we propose a “cost-down roadmap” of this type of solution over the next fi ve years. The vital question we are trying to answer is “how expensive is and will be this technology?” - a question we ask ourselves anytime we forecast emerging technologies. This analysis is an example of the kind of insights we deliver in our technology and market survey reports, and it, along with others, will be detailed in our new report on 3D silicon and glass interposers for 2.5D/3D integration.

Summary of the physical description of the Xilinx Virtex-7 2.5D module

The outside package is a 45x45mm² 1200-ball BGA package. A 3D silicon passive interposer conceived along the design rules of the CMOS 65nm is fl ip chip mounted on top of the BGA organic substrate, and attached to it by thermal solder refl ow. The 3D interposer counts four planarized metal layers (3 damascene copper layers and 1 aluminum layer) and is 100μm thick. The 10μm - 12μm diameter through vias are fully fi lled with copper, and we believe the size of the interposer nears 10cm². On top of the interposer are the CMOS 28nm so-called “slices” with alternated DSP, memory and programmable logic rows on some of them, as well as SerDes interface blocks. We estimate that each slide is roughly 200mm² in surface area. This is some form of heterogeneous integration: different ICs with various functions are assembled together on the same piece of substrate – in this case, a silicon substrate. The ICs are fl ip chip attached to the interposer by means of Cu-Sn alloy microbumps with a minimum pitch of 45μm between two consecutive bumps. The bonding process is high accuracy thermocompression. Of course, like any other large chip, the Virtex-7 2000T requires a heat spreader to be mounted on top of the package, although we decided to leave it out of the summary of the package parts for the cost model. Figure 1

Cost insights into the very fi rst 2.5D package with silicon interposers for high-end digital applications.

Jean-Marc Yannou,Senior Analyst,

Yole Développement

“The total manufacturing cost per interposer wafer in 2012 is $683, of which 61% pertains to the equipment amortization,” says Jean-Marc Yannou

Fig.1: Cross section picture and schematic of the Virtex-7 2000 T module(Courtesy of Amkor Technologies and Yole Développement)

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represents a cross-section picture and schematic of the module.

Some of the characteristics of this package are now well known, but we had to make a few assumptions concerning the missing ones. Table 1 summarizes them. We also made the industrial assumptions of 95% yield for the interposers and 99% subsequent assembly yield. Assembly yields are usually higher, but we took into account the complexity of this module which includes, among other things, fi ve high-accuracy fl ip chip bonding steps. We estimate that the foundry which manufactures the silicon interposers is a depreciated (older than 5 years) CMOS65nm foundry - in fact, we believe it is TSMC-7 in Taiwan.

Manufacturing cost of the interposer

Since we do not expect TSMC to produce more than 10,000 300mm diameter interposer wafers over the course of 2012, we made the assumption that the equipment specifi c to the manufacture

of through silicon vias (TSVs) is not amortized - whereas manufacturing of the redistribution layers is completed with depreciated equipment. TSV-specifi c equipment includes equipment for:- Deep Reactive Ion Etching – DRIE - for via etching- Cu plating for via fi lling- Wafer bonding and debonding - Wafer thinning for the TSV reveal operations

We used our TSV CoSiM + cost model to compute the manufacturing cost of the silicon interposer. The total manufacturing cost per interposer wafer in 2012 is $683, of which 61% pertains to the equipment amortization, 21% to materials, consumables (gas and chemicals), energy and water, 11% to the raw wafers (silicon wafer and bonding carrier), 5% to yield losses and only 2% for labor. It appears that TSV-related process steps

account for ¾ of the manufacturing cost. Of course, this cost contribution will be less in the future, as the related equipment begins depreciating.

We assume that TSMC initially applied a large margin (60%) on the delivered interposer wafers, leading to a wafer price of $1,700 by the end of 2012, i.e. a price up to $30 per interposer.

Assembly and packaging costs

The package substrate is a 4+2+4 fl ip chip BGA organic build-up substrate. We estimate it is sold for $17 a piece by the substrate manufacturer. Total assembly costs are just over $2, and are 60% accounted for by the 1% assembly yield loss. Indeed, the CMOS silicon estate in a Virtex-7 module reaches $125. We estimate that the Non-Conductive Paste (NCP) adhesive used as an underfi ll between the CMOS dies and the silicon interposer constitutes ¼ of the total assembly cost. Assuming a 30% margin for the assembly and packaging services of the OSAT (Amkor Technologies), we estimate that Xilinx pays close to $3 for the assembly of the substrate / interposer / CMOS dies stack, and an additional $3 for the Copper bumping of the so-called CMOS FPGA ‘slices’.

An equivalent solution to the Virtex-7 solution, at least by the number of FPGA programmable gates but with higher power consumption and lower processing bandwidth, would require two single-die packages. These dies would be about twice as big as the 200mm² FPGA ‘slices’ in the Virtex-7 SSIT solution, and everyone knows that large dies yield poorly. So, on one hand the new

“Xilinx’s SSIT silicon based

technology offers a large cost-down potential over the

next 5 years,”added Yannou

Substrate 45x45mm 4+2+4 layers Manufactured by Ibiden

FPGA 'slices' 3 FPGA slices of 200mm each 2 SERDES blocks of 100mm each Manufactured by TSMC in Taiwan CMOS 28nm

Silicon interposer31x31mm CMOS 65nm design rules 3 Cu damascene layers, 1 alu top layer via diameters: 12 m thickness: 100 m

Assembly Interposer to substrate:

C4 solder bumps, reflow soldering post bond capillary underfilling

CMOS slices to interposer: CuSn microbumps 45 m pitch thermocompression bonding non-conductive paste underfill

Table 1: Cost model assumptions (Yole Développement - March 2012)

Assembly 6%, $3

SoC ICbumping5%, $3

Packageorganic

substrate32%, $17

Bumped3D Interposer

57%, $30

Package cost structurefrom Xilinx's standpoint

2012 package cost structure (with manufacturingmargins included) of the SSI package(Yole Développement - March 2012)

SSIT solution uses a presumably costly silicon interposer, but on the other hand the equivalent gate count ‘standard’ solution requires the use of two packages instead of one, with poor front-end yields in the CMOS wafer fab. All in all, we estimate that by the end of the year, the costs of the two solutions will be about the same but with a clear performance advantage to the new SSIT solution provided by the Virtex-7 2000 T.

Cost decrease potential

We expect many more silicon interposer wafers than just Xilinx’s to be produced by TSMC in Taiwan in 2012, and even more in the following years. This will allow for considerable economies of scale and amortization concerning the TSV-specifi c equipment. We therefore sketched a price-down roadmap of the SSIT solution, based on reasonable ramp-up of silicon interposers at TSMC. Taking into account that TSMC’s competitors will likely step into the interposer business, we think that margins will concurrently erode. Figure 2 shows the compared price roadmaps of the two aforementioned solutions. We conclude that Xilinx’s SSIT silicon-based technology will offer a large cost-down potential over the next fi ve years, far exceeding that of the standard single-die package solution.

Xilinx’s SSIT silicon interposer-based module appears to be much more than a beautiful high performance demo. Our simulations appear to prove that it can be highly cost effective, and even cost-competitive with lower-performance solutions. It’s true that today’s solution is a high-

end one, sold by Xilinx for more than $500 a piece – in fact, we think it is $600 to $800/piece in volumes. But leaving aside diffi cult comparisons with alternative developments of the next CMOS nodes, it‘s apparent to us that silicon interposers for high-end digital applications not only provide superior performance, but are not even intrinsically expensive.

www.yole.fr

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Jean-Marc Yannou joined Yole Développement in 2009 as a market analyst and project manager for Advanced Semiconductor Packaging. Before, he occupied various positions in the semiconductor industry for 15 years. He worked for Texas Instruments in test and product engineering and for Philips (then NXP semiconductor) where he served as Innovation Manager for System-in-package technologies.

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Xilinx Virtex-7 3D package price

2-package solution price

Poly.(Xilinx Virtex-7 3D package price) 2 package “equal-gate-count” FPGA solution

Stacked Silicon FPGA

Fig. 2: Price (from Xilinx’s perspective) forecast comparison of the two high FPGA gate count alternatives (Yole Développement - March 2012)

Compared package price forecasts ($)

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Texas Instruments’ embedded die package

While fcCSP and WLCSP (fan-in and fan-out) are still showing impressive growth rates, embedded die packaging

could be an interesting option for miniaturization and integration, especially since this is a native 3D-compatible technology.Die embedding into PCB (Printed Circuit Board) laminated substrates has been developed by a wide range of companies for several years and in a variety of fl avors - but Texas Instruments (TI) is the fi rst to use this packaging technology in high-volume production.

Texas Instrument MicroSiP™

TI uses the MicroSiP™ designation for their modules which use embedded die packaging. The fi rst components to use this packaging are TI’s TPS8267x, high-frequency synchronous step-down dc-dc converters optimized for battery-powered portable applications. With dimensions of 2.9x2.3mm and an output current of 600mA, they provide a current density of 90mA/mm². Provided in an 8-pin, 1mm pitch bottom BGA interface, the modules include the DC-DC converter integrated circuit (IC), an inductor, and input/output capacitors.

TI Picostar™

The IC embedded in the MicroSiP™ module uses Texas Instruments’ PicoStar™ package technology. The PicoStar™ is TI’s die-sized package made by embedding the integrated circuit inside an HDI (High Density Interconnect) laminate substrate, and with a BGA balled surface area on the bottom face. The MicroSiP™ technology is just a superset of the

PicoStar™ package type. A MicroSiP™ module can be built by mounting discrete passive components on the top surface of a PicoStar™ packaged IC, as is done for the TPS8267x product family.

In this case, the IC is thinned down to 130μm and a copper redistribution layer (RDL) is patterned at the wafer level so as to distribute the pads over the die surface area, and prior to embedding the IC in the PCB laminate substrate.

AT&S ECP® process

TI’s PicoStar™ packages and MicroSiP™ modules use the Embedded Component Packaging (ECP®) process offered by AT&S, Europe’s largest PCB manufacturer, and one of the world’s top HDI PCB manufacturers. AT&S has invested years of R&D and specifi c equipment development in order to industrialize this technology. Most of the assembly operations are panel-scale operations—they are performed on AT&S’s PCB infrastructure. They include the embedding process steps which provide the IC with a fan-out area and with 3D paths to both the top and the bottom sides of the embedding substrate. This packaging technology extends the package size beyond the IC surface area, and allows for the mounting of additional components such as discrete passives on top of the laminate SiP module.

There continues to be strong demand for size reduction in mobile electronic products.

W H A T ’ S I N S I D E ?

TI MicroSiP™ Module (Courtesy of System Plus Consulting)

MicroSiP™ Module Delaminated(Courtesy of System Plus Consulting)

Via PCB prepreg(FR4)

IC PicostarTM

MicroSiP™ Module Cross-Section(Courtesy of System Plus Consulting)

Capacitor CapacitorInductor

ICPCB

Solder Ball

"Even if the total cost of ownership of this module is

low enough for cost-obsessed

consumer electronics

applications, we think that the main driver is

integration and miniaturization,"

explainsRomain Fraux

Romain Fraux,Electronics Cost Engineer,System Plus Consulting

Romain Fraux is Project Manager for Reverse Costing

analyses at System Plus Consulting. Since 2006, Romain is in charge of costing analyses of MEMS devices, Integrated Circuit and electronics boards. He has signifi cant experience in the modeling of the manufacturing costs of electronics components.Romain has a BEng from Heriot-Watt University of Edinburgh, Scotland and a master’s degree in Microelectronics from the University of Nantes, France.

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The process begins with the realization of fi ducials in a copper foil by laser drilling to defi ne registration marks for mechanical process steps. Next, adhesive is screen-printed on the copper foil, and sawed and tested "known good dice" are placed with pick and place equipment. The adhesive is cured to ensure solid attachment to the copper foil. The IC is then embedded with a lamination process which presses together an FR4 prepreg with cavities for IC dies and a second copper foil. Through holes vias between the 2-sided PCB of ~150μm diameter are performed with a mechanical drilling process, and microvias enabling access to the IC pad through the bottom laminate layer of the embedded package are realized by laser drilling. Vias are then cleaned and metalized with electroless copper plating. The process to defi ne the fi ne lines is realized with a semi-additive technology: photoresist is laminated on the copper foil, followed by the imaging process of the resist. The resist is developed and copper is electroplated in the non-covered areas of the resist. The semi-additive fl ow fi nishes with the stripping of the resist and the etching of the remaining exposed copper foil. The fi nal steps consist of the formation of the solder mask, the fi nishing (OSP), and inspections and tests.

Supply chain and cost structure

We believe that the manufacturing of the copper RDL on the device wafer and the mounting of the solder balls on the bottom surface of the package are realized by Texas Instruments themselves. The ECP packaging is currently done by AT&S on 18”x24” panels in Austria, allowing for assembly of more than 18,000 packages simultaneously. Specifi c steps of this packaging process fl ow (like placement of the ICs, laser drilling operations, and the semi-additive copper plating operations) require investments from AT&S, and they represent the bulk of the ECP packaging cost as of 2012. Even if the total cost of ownership of this module is low enough for cost-obsessed consumer electronics applications, we think that the main driver is

integration and miniaturization. By adopting this technology, TI spares its customers considerable development efforts, simplifi es logistics and inventories, and saves on the application board space through this module approach.

Romain Fraux, System Plus ConsultingJean-Marc Yannou, Yole Développement

IC Pad connection Cross-Section(Courtesy of System Plus Consulting)

Solder Mask

Copper foil

Electroplated copper

IC silicon substrateTi adhesion layerIC metal layers

Copper RDL

(Courtesy of AT&S)

(Courtesy of System Plus Consulting - March 2012)

IC Die Cost 50%

ECP Packaging Cost + AT&S Overheads

28%

Passives Components

Cost 11%

Passives Assembly Cost + EMS Overheads

8%

Final test + Yield losses cost

3%

MicroSiP module cost breakdown

ECP® simplifi ed process fl ow

Laser - Drillingof fi ducials + overlay

Printingof Adhesive

Assembly ofComponents

Components

Lay up &Pressing

Drilling of Vias

Mechanical - Drilling

Desmearing

Metallizing

Imaging

Copper plating

Stripping/Etching

100% AutomaticOptical INspection

3 D P a c k a g i n g

I S S U E N ° 2 3 M A Y 2 0 1 2

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E V E N T R E V I E W

Report from 2012 IMAPS Device Packaging Conference

My overall impression was that while in years past the topics of wafer scale packaging and 3D integration were

always the topic of some debate, this year the debate was gone and the focus was all about

the how and where. As I said in the editorial, there was a strange sense of normalcy to the topic – which is a good thing indeed.

One of the high points in terms of sessions was the panel run by Phil Garrou. He assembled a veritable who’s who in semiconductors and kept the conversation rolling with a series of challenging questions. We all know we are getting opinion, but the fact that the top industrial players are willing to sit up there and share their thoughts is a testament to their unselfi sh professionalism. And their opinions and comments were appreciated by those in attendance.

While the session was very much worthwhile, it was a long day made a bit longer as an unexpected deviation into a debate on panel scale packaging made the evening session run long. After the event, refl ecting on the fl ow of discussions in the past 5 years, I wondered if that deviation into panel packaging was in fact a harbinger of what might be a mainstream topic at IMAPS in 2018…

www.imaps.org/devicepackaging

MiNaPAD event review

As a Yole Développement analyst and the Editor-in-Chief of 3D Packaging Magazine, I am bound to treat all subjects related to semiconductor packaging in a fair way, regardless of a company’s size, its activities, and, of course, its geographical origin. However, fair does not mean “complacent”, and it is true that Europe’s semiconductor industry has not exactly fl ourished at the same pace as Asia’s or America’s. The 2nd annual MiNaPAD (Micro Nano Packaging And Design) forum took place April 24 – 26 in Grenoble. The question is: why was this relatively new event staged in Europe?

Aside from my functions at Yole Développement, I happen to be the elected president of IMAPS in France – so don’t expect me to speak negatively of this event. In the past, each national IMAPS chapter in Europe used to organize its own relatively busy workshops, with the local language designated as the offi cial one -- but this time is over. The globalization of our industry is such that not a single company can survive using local networks and technologies, whatever its targeted end-applications. When the national IMAPS workshops declined severely after 2005, we realized that a local need for global networking, as well

as for international technical and industrial conferences, remained unfulfi lled. Europe still hosts a number of active semiconductor-related companies serving national or regional industries such as aerospace, avionics, defense, oil drilling, industrial and automotive applications to cite just a few, and these companies need exposure to global technologies. However, they cannot afford to send their experts overseas too often to attend conferences.

I’m happy to report that during the second edition of MiNaPAD, this regional vitality was confi rmed. With right around 200 participants, the event attracted 30% more attendees than last year, including an international audience of over 30% - 50% of which participated via presentations and exhibition booths.

Not only did the European OEMs gain exposure to the most advanced technologies (3D, fan-out, embedding) from the most prominent worldwide players (ASE, StatsChipPac, Amkor, Intel, STMicroelectronics and others), but I was pleased to see European fi rms and research institutes like AT&S, Nanium, Fraunhofer IZM, and LETI stand out on the global semiconductor packaging stage as very active players.

From my position as Yole Développement analyst, I had the opportunity to confi rm some of 2012’s developing trends, like the ubiquity of fan-out WLP/eWLB, which has seemed to shift gears this year to more projects and higher volumes. I also saw some very interesting technology proposals on eWLB-PoP or 2.5D integration with fan-out redistribution before fl ip chip (by StatsChipPac), and an interesting combination of 3D interposers embedded side-by-side in a fan-out package with an IC to enable high density vertical routing through the fan-out package (by ASE).

Next year, IMAPS-France will host EMPC (European Microelectronics and Packaging Conference), the bi-yearly IMAPS-Europe conference, which alternates every other year with IEEE’s ESTC. EMPC is scheduled for September 2013 in Grenoble, with an even larger turnout expected. Too bad you’ll have to wait until 2014 to attend MiNaPAD’s 3rd edition!

www.france.imapseurope.org

Why would IMAPS’ France chapter organize a combined conference and exhibition event dedicated to advanced semiconductor packaging and package design? After all, most of the manufacturing facilities are now located in Asia, and the largest fabless semiconductor players are Americans. Feedback of Jean-Marc Yannou, Senior Analyst at Yole Développement and President of IMAPS France.

The annual trek to Ft McDowell each March has become a must for the advanced packaging community. This year was no exception. A quality crowd was there and we always have good discussions withattendees. Feedback Jeff Perkins, President, Yole Inc.

For the 3rd annual MiNaPAD event, we’re going to need more seats!

M A Y 2 0 1 2 I S S U E N ° 2 3

24 3 D P a c k a g i n g

Teardown of the world’s 1st embedded die package in high volume production

Texas Instruments MicroSiP™ Module using AT&S ECP® Process

Discover the NEW report oni-Micronews.com/reports

Editorial StaffManaging Editor: Jean-Christophe Eloy - Editor in chief: Jean-Marc Yannou - Editors: Jérôme Baron, Lionel Cadix, Paula Doe, Phil Garrou, Amandine Pizzagalli - Media & Communication Manager: Sandrine Leroy - Media & Communication Coordinator: Camille Favre - Production: atelier JBBOX

About Yole Développement

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Beginning in 1998 with Yole Développement, we have grown to become a group of companies providing market research, technology analysis, strategy consulting, media in addition to fi nance services. With a solid focus on emerging applications using silicon and/or micro manufacturing, Yole Développement group has expanded to include more than 50 associates worldwide covering MEMS, MedTech, Advanced Packaging, Compound Semiconductors, Power Electronics, LED, and Photovoltaics. The group supports companies, investors and R&D organizations worldwide to help them understand markets and follow technology trends to develop their business.

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