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Chapter 3(ii) BJT (DC analysis)
17

3b BJT DC Analysis

Jul 18, 2016

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Page 1: 3b BJT DC Analysis

Chapter 3(ii)

BJT (DC analysis)

Page 2: 3b BJT DC Analysis

definitions BiasingBiasing refers to the DC voltages applied to a transistor in order to turn it on so that it can amplify the AC signal. The DC input establishes an operating or quiescent point called the Q-pointQ-point.

• Active or Linear Region OperationActive or Linear Region OperationBase–Emitter junction is forward biased

Base–Collector junction is reverse biased

• Cutoff Region OperationCutoff Region OperationBase–Emitter junction is reverse biased

• Saturation Region OperationSaturation Region OperationBase–Emitter junction is forward biasedBase–Collector junction is forward biased

Page 3: 3b BJT DC Analysis

DC biasing circuits

• Fixed-bias circuit• Emitter-stabilized bias circuit• Voltage divider bias circuit• DC bias with voltage feedback

Page 4: 3b BJT DC Analysis

Fixed-bias circuit

Page 5: 3b BJT DC Analysis

Base-Emitter LoopBase-Emitter Loop

From Kirchhoff’s voltage law:

Solving for the base current:

+VCC – IBRB – VBE = 0

B

BECCB R

VVI

Collector-Emitter LoopCollector-Emitter Loop

The collector current is given by:

From Kirchhoff’s voltage law:

BIIC

CCCCCE RIVV

DC analysis

Page 6: 3b BJT DC Analysis

Load Line for Fixed-bias circuitLoad Line for Fixed-bias circuit

• where the value of RBB sets the value of IBB

• where IBB and the load line intersect • that sets the values of VCECE and ICC

The Q-point is the particular operating point:

The end points of the load line are:

C

CCC RVI

VVCE 0

CCCE VV

mAIC 0

ICsat

VCEcutoff

Page 7: 3b BJT DC Analysis

Circuit Values Affect the Q-PointCircuit Values Affect the Q-Point

Increasing level of IB

Increasing level of RC

Decreasing value of VCC

Page 8: 3b BJT DC Analysis

Emitter-Stabilized Bias CircuitEmitter-Stabilized Bias CircuitAdding a resistor (RE) to the emitter circuit stabilizes the bias circuit.

Page 9: 3b BJT DC Analysis

Base-Emitter LoopBase-Emitter Loop Collector-Emitter LoopCollector-Emitter LoopDC analysis

From Kirchhoff’s voltage law :

0R1)I(-RI-V EBBBCC

0 RI-V-RI-V EEBEEECC

EB

BECCB 1)R(R

V-VI

Since IE = (b + 1)IB:

Solving for IB:

From Kirchhoff’s voltage law :

0 VRI V RI CCCCCEEE

Since IE IC:

)R (RI– V V ECCCCCE

Also:

EBEBRCCB

CCCCECEC

EEE

V V RI– V VRI - V V V V

RI V

Page 10: 3b BJT DC Analysis

Improved Biased StabilityImproved Biased Stability

Adding RE to the emitter improves the stability of a transistor.

Stability refers to a bias circuit in which the currents and voltages will remain fairly constant for a wide range of temperatures and transistor Beta () values.

Page 11: 3b BJT DC Analysis

Load Line for Emitter-bias circuitLoad Line for Emitter-bias circuit

The end points of the load line are:

EC

CCC RR

VI

VVCE 0

CCCE VV

mAIC 0

ICsat

VCEcutoff

Page 12: 3b BJT DC Analysis

Voltage Divider BiasVoltage Divider Bias

This is a very stable bias circuit.

The currents and voltages are almost independent of variations in .

There are two ways of analyzing the voltage divider bias circuit :-1. Exact analysis2. Approximate

analysis

Page 13: 3b BJT DC Analysis

Exact Analysis

21

22 RR

VRVE CCRTh

21 RRRTh

ETh

BEThB RR

VEI1

ECCCCCE RRIVV

Page 14: 3b BJT DC Analysis

Approximate analysis

Where IB << I1 and I2 and I1 I2 :

Where RE > 10R2:

From Kirchhoff’s voltage law:

21

CC2B RR

VRV

E

EE R

VI

BEBE VVV

EECCCCCE RI - RI - V V

)R (R-IVVII

ECCCCCE

CE

Page 15: 3b BJT DC Analysis

DC Bias with Voltage Feedback

Another way to improve the stability of a bias circuit is to add a feedback path from collector to base.

In this bias circuit the Q-point is only slightly dependent on the transistor beta, .

Page 16: 3b BJT DC Analysis

Base-Emitter loop

)R(RRVV

IECB

BECCB

From Kirchhoff’s voltage law:

0RI–V–RI–RI– V EEBEBBCCCC

Where IB << IC:

CBCC IIII

Knowing IC = IB and IE IC, the loop equation becomes:

0RIVRIRI– V EBBEBBCBCC

Solving for IB:

Page 17: 3b BJT DC Analysis

Collector-emitter loop

Applying Kirchoff’s voltage law:IERE + VCE + ICRC – VCC = 0

Since IC IC and IC = IB:IC(RC + RE) + VCE – VCC =0

Solving for VCE:VCE = VCC – IC(RC + RE)