$3A7F

ANALOG CIRCUITS

1 . ( GATE 2013)

2.

(GATE 2013)

3. A low pass filter with a cutoff frequency as 30 Hz is cascadeded with a high pass filter

With a cutoff frequency of 20Hz. The resultant system of filters coil function as

(GATE-2011)

Sol:- (A) A” pass filter (B) An all-stop filter

(C) A band stop filter (D) A Band pass filter

Ans: -

The Cutoff freq of LPF is greater than that of HPF Band pas filter

Ans: (D)

4. For the circuit shown below, the correct transfer characteristics is (GATE-2011)

O 30 20 f

V0

R

-

+ -

+

R

R

R R

R

-12V

-12V

+12V

-12V

Vi

Vo HPF LPF

Vi

fc=30Hz fc = 20hz

Vo HPF HPF

Vi

20Hz 30Hz

Sol:- The first Stage of the given CKt represents subtractor. As than its output is

V01 = -Vi Then

V6R2

R12VUTP

Vo -

+

R

-12V

R

V=12V

Vi

VLPT = -6V

Vi +

-

(D)

Vi

+12V

-12V

6V - 6V

Vo

+6 -6

-12V

+12V

Vo

(C)

(A)

Vi -6V

-12V

+12V

6V

(B)

+6 -6

-12V

+12V

Vo

Vi Vi

-12V

2.2K 1K D

15K

Vz=5

V

VBE=0.7V

VBE(Sat)=0.2V D

V

As

The transfer characteristic curve is

Ans: [ C ]

5. The transistor is used in the circuit shown below has a of 30 and ICBO is negligible. If

the forward voltage drop of diode is 0.7V. Then the current through collector will be

(GATE-2011)

(A) 168 mA (B) 108 mA (C) 20.54 mA (D) 5.36 mA

Sol:- Assume that the transistor operated in active region then.

Apply KVL to base – emitter loop.

10V

+6V

6V

-10V

+12V

-12V

When Vi <6V Vo= +12 V

Vi >6V Vo= -12 V

When Vi >-6V Vo= -12 V

Vi <-6V Vo= +12 V

Vo

Vi -6V

-12V

12V

6V

5-103IB-0.7-0.7+12=0

IB=15.6mA

IC=0.468Amp

Apply KVL to Collector – emitter loop

0-2.2103IC – VCE+12=0

VCE = 2200IC-12

=1017.6Volts

As O<VCE<VCC Not Satisfying this Condition. Transistor Operating in Saturation

region; V+ (Sat)=0.2V

Apply KVL, 0-2.2IC-0.2+12=0

IC=5.36mA

Ans : (D)

6. A clipper Circuit is shown below (GATE-2011)

Assuming forward voltage drops of the diodes to be 0.7V, the input-output transfer

characteristics of the circuit is

-12V

2.2K 1K D

15K

Vz=5

V

VBE=0.7V

VBE(Sat)=0.2V

1k

10V

D

Vi

5V

Vo

Vi

4.3V

4.3V

(A)

Vo

-0.7V

5.7V

5.7V

(C)

0.7V

Vo

Vi

4.3V

4.3V

(B)

10V

10V

Vo

10V -5.7V

(D)

10V

-5.7V

+

10010%

9/100

Sol:- During positive half cycle of the i/p

For Vi 5.7V <, D-off and Zener not operated in breakdown region

Therefore Vo=Vi

For Vi>5.7V, D-ON, as it is on, Vo=5.7V

Zener never operated in break down region (Ies it always off state)

During negative half cycle of i/p

D-is reverse baised and Zener diode gets forward aided only Vi 0.7V

Then Vo = 0.7V

SOLUTION:

When Vi > 0.7V, D-off

Zener- off

Then Vo = Vi

7. As shown in the figure, a negative feedback system has an amplifier of gain 100 with

%10 tolerance in the forward path and an attenuator of value 9/100 in the feedback path.

The overall system gain is approximately. (GATE-2010)

(a) %110

(b) %210

(c) %510

(d) %1010

Solution: 100A,100/9%,10A

dA

A

dA

A1

1

A

dA

f

f

A1

AA f

%10100

91

1

10

%1

Ans: (a)

Vo

-0.7V

5.7V

5.7V

(C)

0.7V

V0

0 2V

V

2R

R If

f

R

a b I

Va=Vb=2V

V

10K

10K 10V V0 I

D1 D2

8. Given that the op-amp is ideal, the O/P voltage V0 is

(a) 4V

(b) 6V

(c) 7.5 V

(d) 12.12 V

GATE-2010

Solution: Given that Non inv Op-amp circuit

Apply KCL at ‘a’

fII

V6V

)2(3V3VR2

VV

R

VO

0

a00aa

)b(:Ans

9. Assuming that the diodes are ideal in the given circuit, the voltage V0 is

(GATE-2010)

(a) 4V

(b) 5V

(c) 7.5V

(d) 12.12V

Solution: The diodes, )off(B.RD

&)ON(B.FD

2

1

mA5.01020

10I

3

I1010V3

0

V5V0

Ans: (b)

10. The transistor circuit shown uses a ‘Si’ transistor with ECBE II,V7.0V and a DC

current gain of 100. The value of 0V is (GATE-2010)

(a) 4.65 V

(b) 5V

(c) 6.3V

(d) 7.23V

R0

AVi Ri

2K

Vi +

+ +

V0

1K

Solution: Apply KVL from 10V to Ground through B–E terminals

0I100VI1010 EBEB

4

CB

4I100I107.010

C

C4I100

I10

mA5.46200

3.9II100I1003.9 CCC

C0 I100V

Volts65.4V0

Ans: (a)

11. The nature of feedback in the op-amp circuit shown is (GATE-2009)

(A) Current-current feedback

(B) Voltage-Voltage feedback

(C) Current- Voltage feedback

(D) Voltage-Current feedback

Sol:- The equivalent circuit of the given amplifier is

The feedback network samples the o/p voltage and given to the inverterting terminal of

the op-amp is shunt mixing (or) voltage mixing

The feedback is voltage-shunt (or) voltage-voltage

ANS : (b)

a

b

Vb=Va=VS

12. The following CKT has a voltage source Vs as shown in the graph. The current through

the circuit is also shown (GATE-2009)

The element connected between ‘a’ and ‘b’ could be

Sol:- During the positive cycle, D-gets F.B then V0=Vi

During negative cycle ‘D’ gets R.B then V0=0

Ans:- (A)

13. The following circuit has R=10k , C=10 F. The input voltage is a sinusoid at 50HZ

with an RMS values of 10V. Under ideal conditions, the current IS from the source is

(A) 10 mA leading by 90o (GATE-2009)

(B) 20mA leading by 90o

(C) 20mA lagging by 90o

(D) 10 mA lagging by 90o

Sol:- Apply KCL at ‘b’

0

R

VV

CS/1

0V 0o0

V0.SCR+Vb–V0=0 Apply KCL at ‘a’

SCR1

VV o

b IS = R

SCRVVV

R

VV bbb0a

Sbb

S VCjVCjR

SCR.VI

+6V

‘Is’ lags behind the applied voltage

|Is| = |C| |Vs|

= 2 |Vs|Cf

= 2 101010506

= 103

10

= 10mA lagging by 900

Ans:- (d)

14. An ideal op-amp circuit and its input waveform are shown in the figures. The o/p w/f of

this circuit will be (GATE-2009)

Sol:- Given that Vsat=6V, – Vsat = –3V

Where V0 = +6V, the potential at non-inverting terminal is,

VUTP = + Vsat V23

16

RR

R

21

2

At instantaneous value of Vi = 2V, V0 = +6V

If VUTP > Vi V0 = +6V

VUTP < Vi V0 = –3V

When V0 = –3V, the potential at noninverting terminal is VLTP = –3(1/3) = –1V

At t < t4, Vo = – 3V i.e., VLTP < Vi Vo = –3V

When VLTP > Vi Vo = +6V

Ans : (d)

90o

IS

VS

10k 0.7V Rf

D

15. The equivalent circuits of a diode, during forward and reverse biased conditions are

shown in figure. (GATE-2008)

If such diodes are used in the clipper circuit of figure given above, the output voltage (Vo)

of the circuit will be

Sol:- Diode branch and 10k resistor are connected in parallel and voltage across them must

be same. So that the value of o/p voltage from potential divider network is

Vo = Vi wtsin5V2

Vi

1010

10o

Therefore voltage across diode must always less than O V OVD i.e., D-Reverse biased

for the given i/p. Vo = 5 sinwt

Ans: (a)

16. Two perfectly matched silicon transistors are connected as shown in the figure. Assuming

the of the transistors to be very high and forward voltage drop to be 0.7V, the value of

current I is (GATE-2008)

(A) 0 mA

(B) 3.6 mA

(C) 4.3 mA

(D) 5.7 mA

Sol:- This is a current mirror circuit, since is very large,

IC1 = IC2 = IC = IE1 = IE2 = IE

& IB1 = IB2 = IB

+

Vi

C1

+

Vi

VC1 +

+

C2

The potential at base of the transistor

VB – 0.7+5=0 VB= –4.3V

D is Forward biased

Current passing through diode is

I = mA3.4k1

V0 B

Ans: (C)

17. In the voltage doubler circuit shown in figure, the switch ‘S’ is closed at t =0. Assuming

diodes D1 & D2 to be ideal, load resistance to be infinite and initial capacitor voltages to

be zero, the steady state voltage across capacitors C1 & C2 will be (GATE-2008)

(A) VC1 = 10V, VC2 = 5V

(B) VC1 = 10V, CC2 = –5V

(C) VC1 = 5V, VC2 = 10V

(D) VC1 = 5V, VC2 = –10V

Sol:- At t=0, S-Closed and During the +ve cycle of i/p,

D1 Forward biased

D2 Reverse biased

‘C’, Charges towards the more value

and ‘C’, will charge upto +5V

V5V 1C

During the –Ve half cycle of i/p voltage

D1–off

D2–ON

Apply KOL

Vi + VC2 + VC1 =0

VC2 = –Vi – VC1

= –5 –5

= –10V

C2 will charge upto –10V

Ans: (d)

18. The block diagram of two types of half wave rectifiers are shown in figure. The transfer

characteristics of the rectifiers are also shown within the block (GATE-2008)

It is desired to mark full wave rectifier using two halfwave rectifiers. The resultant circuit

will be

V0

P

V0 Q

V0 Q P

Sol:- From the transfer characteristic of the rectifier P is

Vo = – Vi for Vi >0

Vo = 0 for Vi <0

From the transfer characteristic of the rectifier Q is

Vo = 0 for Vi >0

Vo = – Vi for Vi <0

The Full Wave rectifier o/p is

So the HWR ‘P’ must be connected to

inverting and ‘Q’ must be connected to

non- inverting terminal of the op-amp.

Ans: (b)

19.A general filter circuit is shown in figure (GATE-2008)

(I) If R1=R2=RA and R3=R4=RB, the circuit acts as a

(a) All pass filter (b) Band pass

(c) High pass filter (d) Low pass

(II) The output of the filter in above is given to the circuit shown in figure

The gain VS frequency characteristic of the 0/p (Vo) will be

V0 Vi

R1

R3 R4

I2

I1 I a

Z I

+

Vd0 Vb Va

Sol:- (i) Assume Z = R2// 1/Sc

=

2

2

2

2

SCR1

R

SC/1R

SC/1R

Z = A

A

SCR1

R

Apply KCL at ‘b’ Apply KCL at ‘a’, I = If

I1=I2 z

VoVa

R

VaVi

A

2

ViV

R

V

R

VVib

4

b

3

b

AA

a0R

zVi

R

z1VV

=

AA

bSCR1

1Vi

SCR1

11V

=

AA

A

SCR1

1Vi

SCR1

SCR2

2

Vi

=

1

2

SCR1

SCR1

Vi A

A

=

A

A

SCR1

SCR

2

Vi

Vo =

CR/1S

S

2

Vi

A

High pass filter

Ans: (c)

(II)

CR/1S

S

2

ViV

A

1

o As input to LPF

then Vo =

SC

1

2

RSC

1

VA

1

i

=

A

1

SCR2

2Vi

=

CR

2SCR

2

CR/1S

S

2

Vi

AA

A

=

CR

2S

CR2

CR1S

S

2

Vi

A

A

A

Transfer function of BPF

Ans: (d)

20.The common emitter forward current gain of the transistor shown is 100F . The

transistor (GATE-2007)

(a) Saturation region

(b) Cut-off region

(c) Reverse active region

(d) Forward active region

Ans: (d)

Sol: Apply KVL from 10V to Ground through B-E terminals

0I102707.0I1010 B

3

E

3

3.9I10270I110 B

3

B

3

A06.2510101270

3.9I

3B

mA506.2IC

mA5318.2IE

Apply KVL from 10V to ground through C-E terminals

0I10VI1010 C

3

CEE

3

0II1010V EC

3

CE

33100378.51010

= 4.962 volts

21.The three terminal linear voltage regulator is connected to a 10 load resistor as shown

dissipated in the transistor? (GATE-2007)

(a) 0.6 W

(b) 4.2 W (c) 2.4 W (d) 5.4 W

IC IE E

IL

10 6.6V

1K I1

IB x

Vin

0.7V

+

+

R

1 R

2

V V

1

V

1

I

L 0

+

r

i

Sol:

06.67.0VE

EV = 5.9 Volts then 10

VI E

L =0.59 Amp

Apply KVL, 0VVV ECEin

1.49.510VCE Volt

mA7.010

9.56.6

10

VVI

33

Ex1

1LE1EL IIIIII

= 3107.059.0

= 0.5893 Amp

Assume that 5893.0II cE

Therefore the power dissipated in the transistor is

CCED IVP

= 4.1 0.5893

= 2.416 W

Ans: (c)

22. The circuit shown in figure is (GATE-2007)

(a) A voltage source with voltage 21 R//R

rV

(b) A voltage source with voltage VR

R//r

1

2

(c) A current source with current r

V.

RR

R//r

21

2

(d) A current source with current r

V.

RR

R

21

2

Sol:

0Vd

0VV

VV

Assume that 1VV

21

21

RR

RVV Therefore 1VV

Then

r

V.

RR

R

r

Vi

21

21

Current entering into the op-amp is zero

21

2L

RR

R

r

ViI

This is voltage to current converter.

Ans: (d)

23. The input signal inV shown in the figure is a 1 kHz square wave voltage that alternates

between +7V and -7V with a 50% duty cycle. Both transistors have the same current

gain, which is large. The circuit delivers power to the load resistor LR . What is the

efficiency of this circuit for the given input? Choose the closest answer. (GATE-2007)

(a) 46%

(b) 55%

(c) 63%

(d) 92%

Sol: The given circuit is class-B amplifier whose efficiency,

cc

p

V

V

4

voltageSupplyV

voltagePV

cc

eakp

10

7

4

= 54.98%

%55

Ans: (b)

24. The switch ‘S’ is the circuit of the figure is initially closed. It is opened at time t = 0. You

may neglect the zener diode forward voltage drops. What is the behaviour of OUTV for

t > 0 (GATE-2007)

(a) It makes a transition from 5V to +5V at .sec98.12t

(b) It makes a transition from 5V to +5V at .sec57.2t

(c) It makes a transition from +5V to -5V at t =12.98 sec

(d) It makes a transition from +5V to 5V at t=2.57 sec

Sol: Initially 0VC

When the switch ‘S’ is opened, the capacitor charges towards the max value of 20V and

is given by )1(e120Vt

c

This is at inv. terminal of the op-amp. But the voltage at Non-inv. Terminal is

00x V11

10

110

100VV

When o/p changes from -5V to 5V, the capacitor changes and

511

10e120

t

22

17

22

51e

22

5e1

tt

RC 17

22e

t

631001.010

17

22ln

t

= 10 sec

17

22lnt

292578.0105

=2.578 sec

Ans: (B)

25. IC 555 in the adjacent figure is configured as an Astable multivibrator. It is enabled to

oscillator at t = 0 by applying a high input to pin 4. The pin description is 1and 8 –

supply; 2-vigger; 4-reset; 6-threshold; 7-discharge. The wave form appearing across the

capacitor starting from t = 0 observed on the storage CRO is (GATE-2007)

Sol: Let ‘C’ is initially relaxed then,

When the ‘C’ charges, D-ON and charging time (ON) is

CR69.0T AH Ck10

k10RR BA

‘C’ discharges through B.RD&C&RB

CR69.0T BL

CRR69.0TTT BALH

D = 50%

charging Time = Discharging time

Ans: (b)

RA

RB

+5

+10V

4.5V

4.5V 5

10V

5A 1k 10V

1K

1K

D1

D2

-0.7V

26. What are the states of the three ideal diodes of the circuit shown in figure? (GATE-2006)

(a) 1D - ON, 2D - OFF, 3D - OFF

(b) 1D - OFF, 2D - ON, 3D - OFF

(c) 1D - ON, 2D - OFF 3D - ON

(d) 1D - OFF, 2D - ON, 3D - ON

Sol: From the given Ckt, we can analyse that the diodes

1D - ON

2D - ON &

3D - OFF then

But no current flows through 2D because current always select the low resistance path

(through short ckt path 1D ) Therefore 2D also OFF

Ans: (a)

27. For given sinusoidal input voltage, the voltage waveform at point P of the clamper circuit

shown in figure will be (GATE-2006)

RL P

D

C Vi

+

Vi

C

V0 +

P 0.7V

RL

+12V

12V

Vi

Vp +

Sol:

During the –ve half cycle of input, Diode D will be forward biased and its equivalent

circuit is

The op-amp has high open loop gain so it goes into the saturation and V7.0Vp

During the +ve cycle of input , D-R.B and no Feedback to the op-amp then VP= 12V

Ans : (d)

28. Assuming the diodes 1D and 2D of the circuit shown in the figure to be ideal ones, the

transfer characteristics of the circuit coil be (GATE-2006)

5

2

10V 5V

D2 RL= Vi

+

Sol: When iV =0, 1D -OFF and 2D also OFF

2D - Reverse biased

Current passing through 2 resistor is 0.

Volts10V,V10VForV10V 0i0

To become 1D -ON, V10Vi 1D - ON and 2D -OFF

Ans: (a)

29. Consider the circuit shown in figure. If the of the transistor is 30 and CBOI is 20 nA and

the input voltage is 5V then the transistor would be operating in (GATE-2006)

(a) Saturation region

(b) Active region

(a) Break down region

(a) Cut-off region

Sol: Assume that the transistor in the active region. To calculate base current

V0 Vi

+

2

10V

+

V0 Vi

+

2

10V

+

10V

10V Vi

V0

12V

2.2 K

Vth

Rth

0.7 +

5V

15K

100K

12V

Vth

x

310115

125x

115

10015R th

012x10100V

3

th

k043.13R th

115

1710012Vth

= 2.783 volts

mA1597.0R

7.0VI

th

thB

Bc II = 4.79 mA

Then apply KVL in C-E loop

12-2.2(4.79)- CEV =0

B.FJv12Vv2.0So

B.RJVolts46.1V

ECE

CCE

Transistor operated in Active region

30. A relaxation oscillator is made using op-amp as shown in figure. The supply Voltage of

the op-amp are 12 the voltage waveform at point ‘p’ will be (GATE-2006)

12V

+6V

10V

12V

1mA

2V

2

2K

2K

Sol: Given circuit is Astable multivibrator whose output is square wave and waveform

across capacitor is exponential waveform. There fore potential across ‘C’ and ‘P’ are

same.

When o/p voltage is + 12V, the ‘C’ changes towards maximum value through 1R . And

max voltage is given by

OND20

10VV 10p

= + 6v

When o/p voltage is -12V, ‘C’ discharges towards -12V through 2R . To calculate this,

consider the circuit at non inverting terminal. At this

D2 – ON then V1012

10VV 0P

Ans: (c)

31. Assume that 1D and 2D in figure are ideal diodes the value of current sI is (GATE-2005)

(a) 0 mA (b) 0.5 mA (c) 1 mA (d) 2 mA

Solution: The current always selects the low resistance path. 1D -ON and 2D -OFF.

The I directed from N type to P-type ( 2D -R.B) As 2D -R.B replaced by O.C

I = 0 Ans: (A)

32. Assume that N-channel MOSFET shown in figure is ideal and its threshold voltage is 1V,

the voltage Vab between nodes ‘a’ and ‘b’is (GATE-2005)

(a) 5V (b) 2V (c) 1V (d) 0V

Solution:

V0V

V2VV2V

S

G

GS

V1Vth

V1VV)sat(V thGSDS

Due to 10V source )sat(VV DSDS N-channel MOSFET operated in saturation, high

current flows through drain and source so that it acts as a SHORT CIRCUIT,

abV = 0V

Ans: (d)

33. The common Emitter amplifier shown in the figure is biased using a 1mA ideal current

source. The approximate base current value is – (GATE-2005)

(a) 0A

(b) 10A

(c) 100A

(d) 1000 A

Solution: Given that IE = 1 mA

mA99.0I1

I EC

A909.9I

I CB

A10IB

Ans: (b)

a

b

Vab

34. Consider the inverting amplifier using an ideal operational amplifier shown in figure.

The designer wishes to realize the i/p resistance seen by the small signal source to be as

large as possible, while keeping the voltage gain between -10 and -25. The upper limit

on FR is 1M . The Value of 1R should be (GATE-2005)

(a) Infinity

(b) 1M

(c) 100 k

(d) 40 k

Solution: Gain of the inverting Amp is 1

F

R

RA

given that FR = 1M , A -10 & -25

then 5

6

1 1010

10R

=100 k when A=-10

k40

25

10R

6

1 when A=-25

The designer wishes the input resistance should be as large as possible

1R =100 k

Ans: (c)

35. The typical frequency response of a two – stage direct coupled voltage amplifier is as

shown in figure (GATE-2005)

Sol: The direct coupled (or) DC coupled amplifier provides a gain at low frequency and for a

two-stage direct coupled voltage amplifier provides a gain at zero frequency

Ans: (b)

36. In the given figure, if the input is a sinusoidal signal, the output-will appear as shown

(GATE-2005)

Sol: The op-amp is in the open-circuited mode i.e. no feedback is given. The op-amp has

high open loop gain and is forced to operate in saturation region, for the given input

waveform of the op-amp

iOL0 VOAV

During the positive half cycle of input 0Vi the op-amp saturated to VV0

During the negative half cycle of i/p 0Vi the op-amp saturated to VV0

Ans: (c)

10K rd

IL

Id

gmVgs Vgs

G

S

Vi V0

+ +

VGS=4V

VGS=3V

VGS=2V

VGS=1V

37. Assume that the threshold voltage of the N-channel MOSFET shown in figure is 0.75 V

the output characteristics of the MOSFET are also shown (GATE-2005)

(i) The Transconductance of the MOSFET is

(a) 0.75 mS (b) 1 mS (c) 2 mS (d) 10 mS

Sol:

ttanconsVGS

Dm

DS

V

Ig

12

10123

1mS

mS1gm

(ii) The voltage gain of the amplifier is

(a) +5 (b) -7.5 (c) +10 (d) -10

Sol: The small signal model of the given amp is

Current through 10k gsmdL VgII

L

3

0 I1010V

= d

4I10

gsm

4Vg10

i

34

0 V1010V

10AV

VV

i

0

Ans: (d)

38. The current through the zener diode in the given circuit is (GATE-2004)

(a) 33 mA

(b) 3.3 mA

(c) 2 mA

(d) 0 mA

Solution: Given that V5.3V0

V3.3Vz

Then zener offers k1.0R z of dynamic resistance.

So 5.3RIV zzz

mA2R

3.35.3I

z

z

Ans: (c)

39. Two perfectly matched ‘Si’ transistors are connected as shown in figure. The value of the

current I is (GATE-2004)

(a) 0 mA

(b) 4.3 mA

(c) 2.3 mA

(d) 7.3 mA

Solution:

This is a current mirror circuit BBBCC III&II2121

BCR I2II

=

CC

I2I

21II CR

Apply KVL from ground to -5V

057.0I100 R

3

mA3.4IR

mA2914.4002.1

10x3.4

21

II

3

RC

mA3.4IIC

Ans : (c)

1 k

=1000 =1000

I

3V

5V Fig.

1 k

IC1

=1000

I

3V

5V Fig.

IR

IB1 IB2

I

3.5V

+

2.2 K

10V RL

VZ = 3.3V

RZ = 100

40. The feedback used in the circuit shown figure can be described as (GATE-2004)

(a) Shunt – Series feedback

(b) Shunt-Shunt feedback

(c) Series-Shunt feedback

(d) Series-Series feedback

Solution: Ans : (b)

As one terminal of feedback element connected to o/p voltage, so it is voltage

sampling (or) shunt sampling and another terminal of feedback element connect

connected to base of the transistor, it is shunt mixing hence it is Shunt-Shunt feedback

amplifier

41. A bipolar junction transistor (BJT) is used as a power control switch by biasing it in the

cutoff region (OFF) or in the saturation region (ON’state). In the ON state, for the BJT

(a) both Base-Emitter and Base-collector junction are reverse biased (GATE-2004)

(b) The B-E junction is R.B and Base-collector junction F.B

(c) The B-E junction is F.B and Base-collector junction R.B

(d) both B-E & B-C junctions are F.B

Solution:

EJ CJ

R.B R.B cutoff (OFF)

R.B F.B Inverse Active Attenuator

F.B R.B Active Amplifier

F.B F.B Saturation ON

Ans : (d)

42. Assuming that the diodes are ideal in figure the current in the diode 1D is (GATE-2004)

(a) 8 mA

(b) 5 mA

(c) 0 mA

(d) 3 mA

Fig.

RS RB RC Ce

RL

V0

C = RC

VCC

RF

C

Fig.

5V D1 D2

8V

1K 1K

Sol: From the Ckt 2D must be in Forward bias where 1D -first replace by O.C

Apply Nodal analysis at 010

8V

10

5V3

1

3

1

08V5V 11

3V2 1

V5.1V1

1D is Reverse biased

0I1D

Ans: (c)

43. The transconductance mg of the transistor shown in figure is 10 mS. The value of input

resistance inR is (GATE-2004)

(a) 10 k

(b) 8.3 k

(c) 5 k

(d) 2.5 k

Sol: Given that gm =10 mS

gm k5

10x10

50r50r

3

k5.2//RR Bin

Ans: (d)

44. The input resistance xxIN IVR of the circuit in the figure is (GATE-2004)

(a) 100 k

(b) 100 k

(c) 1 M

(d) 1 M

Fig.

5V

V1

8V

1K 1K

10K 1K C =

= 50

C = V0

RC

VCC

10K

VS C =

VS RB r V gmV RC

V0

Rin RB = R1//R2 = 5K

+

V0

100K 10K

Vx

Ix 1M Fig.

+

V0

Q2 Vi=0 Q1

R2

Solution: The gain of the op-amp Ckt is

10

1001

V

V

x

0

11V

V

x

0

11

VV 0

x

Apply KCL at Non inverting terminal,

6

xx

6

0xx

10

V11V

10

VVI

k100I

V

10

10xVI

x

x

6

xx

k100R in

Ans: (b)

45. In the Schmitt trigger circuit shown in figure, if CEV (sat) = 0.1V, the output logic low

level (VOL) is (GATE-2004)

(a) 1.25V

(b) 1.35 V

(c) 2.5V

(d) 5.0 V

Solution: When ,0Vi

1Q (cutoff) – off and )sat(ONQ2

CEV (sat) = 0.1V

Then Apply KVL from 5V to Ground through transistor 2Q C-E terminals

0C V200xI5 and

010x10x25.1)sat(V200xI533

CEC

025.11.0V0

0V =1.35 volts Ans: (b)

46. In the active filter circuit shown in figure if Q =1, a pair of poles will be realized with

equal to (GATE-2004)

(a) 10000 rad/sec

(b) 100 rad/sec

(c) 10 rad/sec

(d) 1 rad/sec

Solution: The transfer function of the bridged T-network is

T(S) =

2121122111

2

2121121

2

RRCC

1

RC

1

RC

1

RC

1SS

RRCC

1

R

1

C

1

C

1SS

The pole polynomial of the active filter circuit will be equal to the numerator

polynomial of the bridged T-network

1221121

22

002

RRCC

1

R

1.

C

1

C

1SS

Q.SS

Then 2121

0RRCC

1 and

1

211

2121

C

1

C

1

R

RRCCQ

Given that nF1CC,1Q 21 and 1R = 200 k

993

2

399

10

1

10

1

10x200

R10x200x10x10

Q

1

9

5

13

2 10x210x2

10x2xR

Q

11

110x472.4xR3

2

22 606.223R

k50R 2

3399

2121

0

10x50x10x200x10x10

1

RRCC

1

sec/rad000,100

Ans: (a)

47. In the circuit of figure shown, assume that the transistor has feh = 99 and V7.0VBE .

The value of collector current CI of the transistor is approximately (GATE-2003)

(a) [3.3/3.3] mA

(b) [3.3/(3.3+0.33)] mA

(c) [3.3/33] mA

(d) [3.3/(33+33)] mA

4V

33K

3.3 K

IC

3.3 K

12V

Fig.

Solution:

Apply KVL to Base-emitter loop

0I10x3.37.0I10x334 E

3

B

3

B

3

B

3I)1(10x3.3I10x333.3

99x10x33033

3.3II

10x33033

3.3I

3BC3B

= mA

99

33033

3.3

mA33.033.3

3.3Ic

Ans: B

48. For the circuit shown in figure with an ideal op-amp,

the maximum phase shift of the output Vo with reference to the input vin is

(GATE-2003)

(a) 00

(b) 090

(c) 090

(d) 0180

Sol: Apply KCL at ‘b’ SC.VR

VVb

bi

SCR.VVV bbi

SCR1

VV i

b

Apply KCL at ‘a’, fII

ia00aai VV2V

R

VV

R

VV

= ib VV2

=

SCR1

SCR1Vi

CRj1

CRj1

V

V

i

0

4V

33K

3.3 K

Fig.

3.3 K

12V

IC IB

Fig.

R

R

R C

Vin V0

+

Fig.

R

R

R C

Vin V0

+ I

a

b

If

I2

I1

CRtan2

V

V 1

i

0

For ,909000

0180

Ans: (D)

49. For the n-channel enhancement MOSFET shown in figure, the threshold voltage

Vth = 2V. The drain current DI of the MOSFET is 4 mA when the drain resistance is

1k . If the value of DR is increased to 4k , the drain current DI will become

(a) 2.8 mA (GATE-2003)

(b) 2.0 mA

(c) 1.4 mA

(d) 1.0 mA

Sol: Given that V2Vth ,

GD VV , 0VS

GSDS VV

We know k1R,mA4I DD

0VRI10 DDD

V6410VD

GSD VV6V

then 2)th(GSGSD VVkI

4 = 226xk

2vmA

4

1k

But when DR changed to k4 then

mAmII410VV DDDSGS

Then

2nGSGSD tVVkI

2DD 2I104

1I

2DI484

1

2DD I24I

ID

10V

RD

Fig.

ID

10V

RD

Fig.

VD

D

2

DD I44I4I

04I25.4I D

2

D

2

1625.425.4ID

2

436.125.4ID

= 2.843 mA (or) 1.407 mA

mA407.1)or(84.2ID

For N-channel E-MOSFET thGS VV

)84.2(410VGS & )407.1(410VGS

= -1.372 volts = 4.372 volts

DI =1.407 mA

Ans: (C)

50. Assuming the operational amplifier to be ideal the gain

i0 VV for the circuit shown in figure

(GATE-2003)

(a) -1

(b) 20

(c) -100

(d) -120

Solution:

Apply KVL at ‘a’

3

x

3

i1

10x10

V

10

VII

ix V10V

Apply KVL at ‘b’

3

0x

3

x

3

x321

10x10

VV

10

V

10x10

VIII

0xxx VVV10V

ix0 V120V12V

120V

VGain

i

0

Ans: (d)

Fig.

1K Vi

V0

+

1K

1K 1K

1K Vi

+

1K

1K 1K

I a

b

I3

I2

I1

x

V0

Fig.

51. A voltage signal 10 tsin is applied to the circuit with ideal diodes as shown in figure.

The max and minimum values of the output waveform of the circuit are respectively

(GATE-2003)

(a) +10V and 10V

(b) +4V and 4V

(c) +7V and 4V

(d) +4V and 7V

Solution: For positive half cycle

(i) (When V4Vi ) 2D ON, 1D = off then

(ii) When V4Vi , 1D & 2D -OFF i0 VV

(iii) For negative half cycle, 1D -ON, & 2D -OFF

iV - 10I+4-10I = 0

I= mA20

4Vi

When iV = -10V (max.value)

I = 20

6mA

0I104V0

4I10V0

= 420

610

= -3-4 V7V0

Ans: (d)

52. The circuit of fig shows a 555 timer IC connected as an Astable multivibrator. The value

of capacitor ‘C’ is 10 nF. The value of the resistors AR and BR for a frequency of

10 kHz and a duty cycle of 0.75 for the output waveform are (GATE-2003)

(a) AR = 3.62 k , BR = 3.62 k

(b) AR = 3.62k , BR = 7.25 k

(c) AR = 7.25 k , BR = 3.62 k

(d) AR =7.25 k , BR = 7.25 k

Vi

10 K

D1 D2

4V 4V

10 K

V0

+

Fig.

Vi

10 K

4V

10 K

V0 +

Fig.

I

Fig.

555

Th

Tr

Vout

Vvcc

RA

RB

C

Vi

10 K

4V

10 K

V0=4V

+

Fig.

4V

Solution:

Given that f = 10 kHz, D = 0.75, C = 10 nF

The frequency of Oscillations from 555 Astable timer is C)R2R(69.0

1f

BA

94BA

10x10x10x69.0

1

fC69.0

1R2R

AR +2 BR =14.492 k

and 75.0R2R

RRD

BA

BA

AR + BR = 0.75 ( AR +2 BR )

= 10.869 k

BR = ( AR +2 BR ) – ( AR + BR )

= 14.492-10869

= 3.623 k

AR = 10.869-3.623 = 7.246 k

Ans: (c)

53. In the circuit shown, the current gain '' of the ideal transistor is 10. The operating point

of the transistor CCE I,V is (GATE-2003)

(a) (40V, 4A) (b) (0 V, 4A)

(c) (40V, 5A) (d) (15V, 4A)

Solution:

Given that BI =0.5 amp

Assume transistor – in Active, BC II =5 Amp

then CEV =40-10 x 5 = -10v

As CEV is negative, Q operated is saturation

CEV =0 V then 40-10 0VI CEc

cI =4 amp

Ans: (b)

54. The cutin voltage of both zener diode Dz and D shown in Figure is 0.7 V, while

breakdown voltage of the zener is 3.3 V and reverse break down of D is 50 V. The other

parameters can be assumed to be the same as those of an ideal diode. The values of the

peak output voltage (V0) are (GATE-2002)

15V

0.5A IC

10

40V

Fig.

1K

1K

0.7

33V Vi V0 = 4V

+

1K

1K

Vi V0

+

Vi

I

(a) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle.

(b) 4 V in the positive half cycle and 5 V in the negative half cycle.

(c) 3.3 V in the both positive and negative half cycle.

(d) 4 V in the both positive and negative half cycle.

Sol: During the positive half cycle, when Vi > 4 V zener replaced by Vz (ON) & D replaced

by 0.7 V

During the negative half cycle

Zener diode becomes forward biased and PN junction diode becomes reverse biased,

then

2

VV i

0

tSin5

Vomax = 5V

Ans: (B)

55. The forward resistance of the diode shown in figure is 5 and the remaining parameters

are same as those of ideal diode. The DC component of the source current is

(GATE-2002)

(a) 50

Vm (b) 250

Vm

(c)

2100

Vm

(d)

50

V2 m

tSinVV mi

sec/rad314

Sol: During positive half cycle

D – F.B replaced by 5

1k

1k

I V0

10sin t

= 314rad/sec

Vi 45

D

Vi 45

5

A B

R

V

D

50

V)t(i i

tsin50

V)t(i m

DC component is Idc =

50

V

50

V mm

During negative half cycle, D – R.B – replaced by O.C

I = 0

Ans: (a)

56. The output voltage (V0) of the Schmitt trigger shown in figure swings between + 15V and

15V. Assume that the operational amplifier is ideal. The output will change from +15V

to 15V when the instantaneous value of the input sine wave is (GATE-2002)

(a) 5 V in the positive slope only

(b) 5 V in the negative slope only

(c) 5 V in the positive and negative slopes

(d) 3 V in the positive and negative slopes

Sol: When V0 = + 15 V,

The potential at non – inverting terminal is UTP,

VUTP =

21

2ref0ref

RR

R)VV(V

VUTP =

13

32152 When VUTP > Vi V0 = + 15 V

= 5V. VUTP < Vi V0 = 15 V

When V0 = 15 V, the potential at non – inverting terminal is LTP

VLTP = Vref + ( V0 Vref)

13

3

=

13

3172

VLTP = 1.923 V

The output will change from + 15 V to 15 V when the instantaneous value of the

input sine wave is 5 V in the positive slope only.

Ans: (a)

57. In the single phase diode bridge rectifier shown in figure, the load resistor is R = 50 .

The source voltage is V = 200 sin t, where = 2 x 50 rad/sec. The power dissipated in

the load resistor R is (GATE-2002)

(a)

W3200

(b) 400 W

t –10V

10 V

5V

–1.923V

+15V

O

15V

10k

3k

100 + – Vi

2V

Vi= 10sint

A

B

D C

D1

D2 D3

D4

R

R

V(t) i(t)

V(t) R

i(t)

IC

IB

17K 1K

RF

V0

IE

1K(IC+I)

I B

R1 IE

15V

I1

VB

(c)

W400

(d) 800 W

Sol: The given circuit can be redrawn as

During the positive half cycle of the i/p then

D1 & D3 – ON, S.C

D2 & D4 – Off – O.C

50

tsin200

R

)t(v)t(i

= 4 sin t. Amp

During the negative half cycle of the input, D1 & D3 – off O.C

D2 & D4 – ON S.C

tsin4R

)t(v)t(i

Full Wave Rectifier – power dissipated in the load resistor R is

2

)t(ix

2

)t(vP

2

4x

2

200

P = 400 W

Ans: (b)

58. For the circuit shown in Figure, IE = 1 mA, = 99 and VBE = 0.7 V determine

(a) Current through R1 and RC (GATE-2002)

(b) The output voltage V0

(c) The value of RF

Sol: Given that IE = 1 mA

mA99.0I1

IC

A10I

I CB

Potential at Base is

VB – VBE – IE x 103 = 0

VB = 0.7 + I = 1.7 Volts

15V

RC=1K

IC IB

17K 1K

RF V0

R1

VX C

R C

V0 R I1

I2

1/SC

1/SC

VX C

R C

VY R

Figure 1

Then I1 = A100K17

VB

Then I = I1 + IB

= 110 A

(a) Current passing then through R1 is 100 A

Current passing through RC is IC + I

= 0.99 mA + 110 A

= 1.1 mA

(b) The O/P voltage V0 = 15 103(IC + I)

= 15 103(1.1 x 103)

= 13.9 Volts

(c)

K91.110

10x110

7.19.13

I

VVR

6

B0F

59. Determine the transfer function

x

y

V

V for the RC network shown in figure (1). The

network is used as a feedback ckt in an oscillator ckt shown in figure (2) to generate

sinusoidal oscillations. Assuming that the operational amplifier is ideal, determine the value

of RF for generating these oscillations. Also determine the oscillation frequency if R = 10 K

and C = 100 PF (GATE-2002)

Sol:

Apply KVL to loop (1)

Vx(S) = I1(S)

SC

1R I2(S).

SC

1 -------- (1)

Apply KVL to loop (2)

0SC

2R)S(I

SC

1)S(I 21

SC

SCR2)S(I

SC

1.)S(I 21

I1(S) = I2(S) [2 + SCR] --------------------- (2)

Substitute equation (2) in (1) then

SC

1).S(I

SC

SCR1)SCR2()S(I)S(V 22x

Figure 2

1)SCR2()SCR1(SC

)S(I2 But Vy(S) = I2(S).R

1RCSSCR32(SCR

)S(V222y I2(S) =

R

)S(VY

1SCR3RCS

SCR

)s(V

)S(V222

x

Y

SCR

13SCR

1

)S(V

)S(V

x

y

If this is connected as feedback in the op – amp ckt then

Then feedback factor 0

f

V

V

SCR

13SCR

1

CR

1CRj3

1

To get the undamped oscillations the imaginary part of the feedback factor is zero.

0CR

1CR

RC

1

RC

122

2

The frequency of oscillations is given by

RC2

1f0

= 123

10x100x10x10x2

1

= 159.12 KHz

Then 3

1

To get sustained oscillation | AB| =1

A = 31

310

R1A

3

F

210

R3

F

RF = 2 K

Vf

V0

V0

+5

V

5

V

1mA

1K

a

Va=0

+

VS +

100

10

1K 90

V0 +

90

10

Vf V0

I

60. The circuit shown in figure uses an ideal op-amp working with +5V and 5V power

supplies. The output voltage Vo is equal to (GATE-2000)

(a) +5V

(b) 5V

(c) +1V

(d) 1V

Ans : (d)

Sol:

Apply KCL at inverting terminal

1VV10

VV10 oa3

0a3

Volt1V0

61. The type of the power amplifier which exhibits crossover distortion in its output is

(GATE-2000) (a) class A (b) Class B (c) Class AB (d) Class C

Sol:

Ans : (b)

62. The feedback factor for the circuit shown in fig. is (GATE-2000)

(a) 100

9 (b)

10

9

(c) 9

1 (d)

10

1

Ans : (d)

Sol :

The feed back network is

10IVf

10100

V0

10

1

V

V

0

f

6.3K

5K

5V

IB 0.7V

=80

10V

+

RE

IS RS

Vi Ri

Ii

10 AI Ii

R0=10K V0

IL

RL

+

+

63. A diode whose terminal characteristics are related as TV

V

SD eIi , where IS is the reverse

saturation current and VT is thermal voltage (=25 mV) is biased at iD= 2 mA. Its dynamic

resistance is _______ (GATE-2000)

(a) 25 (b) 12.5 (c) 50 (d) 100

Ans : (b)

Sol :

D

acdI

dv

diodethroughCurrentinChange

diodeacrossvoltageinChangeR

Diff. eq w.r.t V

T

D

T

V

V

S

V

D

V

I

V

1.e.I

d

DIT

5.12102

1025

I

VR

3

3

D

Tac

64. In the circuit of figure, the value of the base current IB will be (GATE-2000)

(a) 0 A

(b) 18.2 A

(c) 26.7 A

(d) 40 A

Ans : (b)

Sol : Apply KVL in the base loop

010RI7.00 EE

3EEE

103.6

3.9I3.9RI

mA4762.1IE

A22.181

II E

B

65. A current amplifier has an input resistance of 10, an o/p resistance of 10K and a

Current gain of 1000. It is feed by a current source having a source resistance of 10K

and its output connected to a 10 load resistance. Find the voltage gain and the power

gain (GATE-2000)

Sol:

Ii Rs

Ri Vs

K10RS

L0

0iIL

RR

RIAI

10RL

1010

10I1000

4

4

i

1000AI iL I999I

Voltage gain S

0

V

V

)RR(I

RI

iSi

LL

S

i

i

L

S

LIS

I

I

I

I

I

IA

)1010(

109994

iS

SSi

RR

RII

= 0.998

iS

S

S

i

RR

R

I

I

Power gain = Current gain Voltage gain

iS

SIIS

RR

RAA

= 999 0.998

= 997

10010

1000010

3

= 999

66. The mobility of an electron in a conductor expressed in terms of (GATE-1999)

(a) secV/Cm2

(b) secV/Cm

(c) V/Cm2 (d) sec/Cm

2

Ans : (a)

67. The enhancement type n-channel MOSFET is represented by the symbol

(GATE-1999)

`

(a) (b)

(c) (d)

(A)

Ans : (a)

68. As temperature is increased, the voltage across a diode carrying a constant current.

(a) Increases (b) Decreases (GATE-1999)

(c) Remains Constant

(d) May increase or decrease depending upon the doping levels in the junction

Ans : (b)

Sol : When temperature increases the current passing through the diode increases. But to

maintain the carrying current as constant, voltage across the diode must be decreased.

69. One of the applications of current mirror is (GATE-1998)

(a) Output current limiting

(b) Obtaining a very high current gain

(c) Current feedback

(d) Temperature Stabilized biasing

Ans : (d)

70. Match the following (GATE-1998)

Circuit Functions

(P) High-pass filter

(Q) Amplifier

(R) Comparator

V o Vi

+

VCC

Vi +

V o

(C)

Vi +

V o

(B)

1 V

+

1 K

1 K

1 K 2 V

(S) Low-Pass Filter

Ans : (A) – Comparator

(B) – LPF

(C) – HPF (2nd order)

)P()C(),S()B(),R()A(

71. A NPN Si transistor is meant for low-current audio amplification. Match its following

characteristics against their values. (GATE-1998)

Characteristics Values (A). VEB max (P) 0.7 V

(B) VCB max (Q) 0.2 V

(C) VCE max (R) 6 V

(S) 50 V

Sol : A P

B R

C Q

72. A major advantage of active filters is that they can be realized without using

(GATE-1997) (a) OP-amps (b) Inductors

(c) Resistors (d) Capacitors

Ans : (b)

73. The circuit shown in figure acts as a _________ and for given inputs, its output voltage is

___________ V (GATE-1997)

Sol: The given circuit is

Since 0Vd

0VV ab 1 V

+

1 K

1 K

1 K

2 V

I3

I1

I2

a

b

0VV ab

Apply KCL at ‘a’

3

0a

3

a

3

a

10

VV

10

V2

10

V1

0V3V3V aa0

V3V0

The O/P voltage is sum of inputs and phase shift between them is 180o.

The ckt is inverting summing amplifier.

74. The depletion region (or) space charge region (or) transition region in a semiconductor

p – n junction diode has (GATE-1996)

(a) Electrons and holes (b) positive ions and electrons

(c) positive and negative ions (d) negative ions and holes

(d) no ions, electrons or holes

Sol: Due to concentration gradient exist either P or N side, diffusion of majority carriers takes

place due to this recombination of e - hole takes place on both sides of the junction.

Therefore depletion region formed. In their region there is no exist of mobility of charge

carriers ( e & hole) and exist only immobile ions (positive & Negative)

Ans: (c)

75. A non inverting op – amp amplifier is shown in figure. The o/p voltage is (GATE-1996)

(a) 2

3 sin 100t

(b) 3 sin 100t

(c) 2 sin 100t

(d) None of these

Sol:

Apply KCL at ‘b’ I1 + I2 = 0

0R

Vt100sin2

R

V2 bb

sin 100t = 2 Vb

Vb = 2

1 sin 100t

Apply KCL at ‘a’

I = If

a00aa V3V

R2

VV

R

V0

V0 = 2

3 sin 100t

Ans: (a)

R

R

R

2R

+

−

2

2+sin100t

R

R

R

2R

+

−

If

V0 a I

I1

I2

−2 b

2 + sin 100t

76. In the transistor amplifier shown in figure, the ratio of small signal voltage gain when the

emitter resistor is bypassed by the capacitor ‘Ce’ to when it is not bypassed. (Assuming of

simplified approximate h – parameter model for transistor) is (GATE-1996)

(a) 1

(b) hfe

(c) ieh

Re)h1( fe

(d) ieh

Re)h1(1 fe

Ans: The small signal model with Re & Ce

Voltage gain = ib

CL

i

0

ZI

RI

V

V

ieh

Rh Cfe

The small signal model with Re only

i

CC

i

0V

V

R.I

V

VA

But Vi = [h ie + (1 + hfe) Re] Ib

AV = e

C

R)hfe1(ieh

Rhfe

Ratio =

ieh

R)feh1(ieh

R)hfe1(ieh

Rhfe

ieh

Rhfe

A

A e

e

C

C

1

V

V

ieh

R)hfe1(1 e

Ans: (d)

77. Let the magnitude of the gain in the inverting op – amp amplifier circuit shown be x with

switch S1 open. When the switch is closed, the magnitude of gain becomes.

(GATE-1996) (a) x/2

(b) – x

(c) 2 x

(d) – 2 x

hie

Vi Vo RB E RC

hfeIb IL

Ib IC

1+ (hfe ) Ib

Vi

+

Vo

R R R

S1

B

Vi Vo

E

RB E RC

hfe Ib IL Ib

Zi

IC

hie

RC

R1

R2 Re

VCC

Vo C1 Cc

Vi

Ce

Sol: (i) when switch is open gain = 2xV

V

i

0

(ii) When switch is closed

1V

V

i

0

A’ = (−2)

2

1

= 2

x

Ans: (a)

78. The common mode voltage of a unity gain (voltage follower) op – amp buffer in terms of

its output voltage V0 is ___________ (GATE-1995)

Sol:

For a voltage follower, Va = Vb (or) V0 = Vi

i/p

The common mode voltage = 2

1(Va+ Vb)

= 2

1(2 V0)

= V0 or Vi

Vi

+

Vo

2 R R

Vi

+

Vo

R R

Vo

+

V

a

b Vi

10 k

47 K

20 V

+ 10 V

79. In the transistor circuit shown in figure. Collector to ground voltage is +20V. Which of

the following is the probable cause of error? (GATE-1994)

(a) Collector Emitter terminals shorted

(b) Emitter to ground connection open

(c) 10 K resistor open

(d) Collector base terminals shorted

Sol: Given that collector to ground voltage is 20 V i.e, collector to ground is nothing but

collector to emitter voltage = 20 V. So no current passing through 10 K. So collector

directly connected to 20 V supply.

From their we conclude that IE = IC = 0, IB = 0.

Emitter to ground is open circuited.

Ans: (b)

80. A practical R.C sinusoidal oscillator is built using a positive feedback amplifier with a

closed loop gain slightly less than unity. (TRUE/FALSE) (GATE-1994)

Sol: A sinusoidal oscillator is built using a positive feedback amplifier and its closed loop

gain is slightly greater than unity.

Ans: (FALSE)

81. An analog comparator is a high gain amplifier whose output is always either in positive or

in negative saturation. (TRUE/FALSE) (GATE-1994)

Sol: An analog comparator is the open loop application of op – amp whose gain is very high.

In open – loop mode the op – amp is forced to operate in either positive or negative

saturation.

Ans: (TRUE)

82. Given figure shows a two stage small signal transistor feedback amplifier. Match the

defective component (listed on the left hand side below) with its probable effect on the

circuit (listed on the right hand side) (GATE-1994)

RF

RS

VS

VC

C

Vo

C4

C3

C2 C1

R2

R1

RC

1

Re1

e11

Re2

RC

2 R1

R2

C5

TR1 TR2

List – I List – II

A. Capacitor C1is open P. All dc voltages normal V0 increases marginally

B. Capacitor C3 is open Q. Collector of TR2 at VCC, V0 = 0

C. Capacitor C4 is open R. All dc voltages normal gain of 2nd stage decrease V0

decrease

D. RC2 is shorted S. All dc voltage normal V0 = 0

T. All dc voltages normal, overall gain of the amplifier

Increases, V0 increase

U. No change

Sol:

If capacitor C1 is open, no i/p is connected to the circuit then V0 = 0 and the DC

voltages are unaffected. A S

If C3 is open, the gain of the 2nd stage decreases and hence V0 decrease B R

If C4 is open – No negative feedback. So that overall gain of the amp. Increase and V0

increase C T

If R2 is shorted – collector is at VCC and AC voltage V0 becomes zero. D Q

Ans: A S, B R, C T and D Q.

83. Given figure, shows a non – inverting op – amp summer with V1 = 2 V and V2 = − 1V the

output voltage V0 = ___________. (GATE-1994)

Sol: Since Vd 0

Vb Va

Apply KCL at ‘b’

R

V

R

V1

R

V2 bbb

1 = 3 Vb Vb = 1/3 Volts

Apply KCL at ‘a’

R2

VV

R

Vo 0aa

− 2 Va = Va – V0 V0 = 3 Va

= 3 Vb

=

3

13

= 1 Volts. V0 = 1 Volts

+

2 R

R

R

R R

a

b 2 V

1V

V0

-