366605_634850313970487500

VHDL and Verilog HDL Lab Manual

Prepared By:

Parag Parandkar Asst. Prof. & Head, ECE Dept., Oriental University, Indore (M.P.)

[email protected]

FPGA DESIGN FLOW

Programmable Logic Design Flow

Gate level Model

Libraries (Simprims

and

Unisims)

Design Specifications

Design Entry

RTL Model

Functional

Simulation

(Zero Delay)

T

E

S

T

B

E

N

C

H

Synthesis

Gate level

description using

target library cells

Gate level

Simulation

Mapping +

Translation

Gate level model to

device architecture

Place and Route

Placing the design in

device while optimizing

it for speed and area

Programming file

generation

Bit Stream

Download onto

FPGA/ CPLD

Timing

Simulation

(Gate +

Interconnect

Delays)

Target Device

Libraries (Vender

Specific)

Design Constraints

Area / Speed

Target Device

Libraries (Vender

Specific)

Design Constraints

Area / Speed


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FPGA Design Flow for Xilinx The Design flow followed by Xilinx devices is as shown as under:

Xilinx FPGAs are reprogrammable and when combined with an HDL design flow can greatly reduce the design and verification cycle.


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Broadly the stages can be categorized as:

1. Design Entry may have two alternatives:

a) Performing HDL coding for synthesis as the target.( Xilinx HDL Editor).

b) Using Cores(Xilinx Core Generator).

2. Functional Simulation of synthesizable HDL code (MTI ModelSim).

3. Design Synthesis ( Xilinx project navigator).

4. Design Implementation (Xilinx Design Manager).

The stages are linked as follows:

Design Entry

The first stage of Xilinx design flow is a design entry process. A design must be

specified by using either a schematic editor or HDL text-based tool.

Functional Simulation Upon the finish of the design entry stage, the functional simulation of the design

is being performed, which is used to verify functionality of the design assuming no

delays, whatsoever. This assumes no target technology selection at this stage and hence

assumes zero delay in simulation.

Timing Simulation

Program onto FPGA

VERILOG HDL/Verilog

Code Design Entry

Functional Simulation

Synthesis

Post Synthesis Simulation

Implementation


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Complex designs must be intensively simulated, at different simulation points,

during the design flow. Simulation verifies the operation of the design before it is

actually implemented as hardware. One of the most prevalent methods for simulation is

testbenching. Testbenches (VERILOG HDL) or text fixtures (Verilog) are used to specify

circuit stimuli and responses.

Roughly, simulation can be divided as functional and timing simulation. Primarily, the

functional simulation verifies that the designs specifications are correctly understood and coded. Timing information, produced during the device implementation stage, is not

available during the functional simulation. Functional simulation can be used after

synthesis, too.

Comparison between the pre- and post-synthesis simulations results checks the results of the HDL compilers work and the HDL codes correctness. Timing simulation operates with the real delays (results of device implementation) and is

used for verification of implemented design. Timing data are given in an .sdf file

(Standard Delay Format).

Xilinx supports functional and timing simulations at different points of the design flow:

Register Transfer Level (RTL) simulation. Post-synthesis functional simulation (Pre-NGDBuild). Post-implementation back-annotated timing simulation.

Design Synthesis After this process, the synthesis is performed. Here for the first time in the design

flow the target technology (choice of a particular FPGA device family) is being

performed. This target technology selection will remain the same, henceforth in the

design flow, upto the final implementation stage, where finally generated Bit stream file

gets downloaded onto that FPGA.

The output of the synthesis process is creation of gate level netlist. This refers to

the EDIF implementation netlist of the FPGA design. Besides the EDIF implementation

netlist, the XNF (Xilinx netlist format) netlist can be used as well.

Although the XNF is now becoming rather obsolete. The EDIF netlist is used as

an input file to the Xilinx Implementation tool and specifies how the core will be

implemented.

The Electronic Design Interchange Format (EDIF) is a format used to exchange design

data between different CAD systems. In the world of FPGA design, it is used for

interchange of data between different EDA (Electronic Design Automation) software

tools. EDIF files are used for FPGA implementation only. They are the result of design

synthesis and can be generated from different design entry EDA tools: schematic or HDL

design tools. EDIF files are inputs to the Xilinx implementation tools during the

translation step (NGDBuild).

Design Implementation Design Implementation includes the following steps:

i) Translate

ii) Map

iii) Place and Route


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In the Translate step, which is the first step in the implementation process, EDIF

netlist must be further converted into Native Generic Database file (NGD), by means of a

program called NGDBuild. The NGD file resulting from an NGDBuild run contains the

logical description of the design that can be mapped into a targeted Xilinx FPGA device

family. It is important to stress that NGDBuild merges all available EDIF netlists from

the working directory. This is actually the step where the black-box netlist becomes

merged with the rest of FPGA design.

In the next stage, the Map stage, the NGD file is an input into a MAP program

that maps logical design to a Xilinx FPGA. The output of the MAP program is an NCD

(Native Circuit Description) file. The NCD is a physical representation of the design

mapped to the components of internal FPGA architecture.

The mapped design is ready to be placed and routed. The PAR program does this

job. The input to PAR is a mapped (not routed) NCD file, while the output is a fully

routed NCD file.

Review reports are generated by the Implement Design process, such as the Map

Report or Place & Route Report, and change any of the following to improve your

design:

Process properties Constraints Source files

Synthesis and again implementation of the design is being made until design

requirements are met.

Timing verification of the design can be made at different points in the design

flow as follows:

i) Run static timing analysis at the following points in the design flow:

After Map. After Place and Route.

ii) Running Timing Simulations at the following points in the design flow:

After Map (for a partial timing analysis of CLB and IOB delays). After Place and Route (for full timing analysis of block and net

delays).

Program onto FPGA Programming on the Xilinx device can be made as follows:

Creation of a programming file (BIT) to program FPGA. Generate a PROM, ACE, JTAG file for debugging or to download to

the device.

Use iMPACT to program the device through programming cable. Xilinx FPGA, as an SRAM-based programmable PLD, must be configured with

the configuration bitstream. The configuration bitstream is generated from the fully

routed NCD file, by means of a BitGen program. The output of BitGen is a binary file

with the .BIT extension that can be formatted for different PROM devices.


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EXPERIEMENT NO. 1

Simulation using all the modeling styles and Synthesis of all the

logic gates using VHDL

AIM:

Perform Zero Delay Simulation of all the logic gates

written in behavioral, dataflow and structural modeling style in VHDL using a

Test bench. Then, Synthesize each one of them on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used: i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from

Simulation to Implementation to download onto FPGA).

Block Diagram:

Truth table:

And Gate: Or Gate:

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

Nand Gate: Nor Gate:

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

And, Nand,

Or, Nor,

Xor, Xnor

A

B

C

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

A B Y

0 0 1

0 1 1

1 0 1

1 1 0


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Xor Gate: Xnor Gate:

A B Y

0 0 1

0 1 0

1 0 0

1 1 1

Boolean Equation:

And Gate: Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B) Nor Gate: Y = (A+B) Xor Gate: Y = A.B + A.B Xnor Gate: Y = A.B + A.B

VHDL Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):

library ieee;

use ieee.std_logic_1164.all;

entity andg is

port (a,b : in std_logic;

c : out std_logic

);

end andg;

architecture andg_df of andg is -- simple dataflow modeling

begin

c


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);

end org;

architecture org_df of org is -- dataflow modeling using when . else begin

c


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architecture nandg_beh of nandg is -- behavioral modeling using case end case begin

process(a,b)

variable v : std_logic_vector(1 downto 0);

begin

v := a & b;

case v is

when "00" => c c c c c


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end case;

end process;

end norg_beh;

Xor gate(Dataflow, behavioral modeling):

library ieee;


entity xorg is


c : out std_logic

);

end xorg;

architecture xorg_df of xorg is -- simple dataflow modeling

begin

c


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c : out std_logic

);

end Xnorg;

architecture Xnorg_df of Xnorg is -- dataflow modeling using with select signal sel : std_logic_vector(1 downto 0);

begin

sel


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nandg_i : nandg port map ( a => a_i,

b => b_i,

c => c_i

);

process

begin

a_i


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EXPERIEMENT NO. 2

Simulation using all the modeling styles and Synthesis of 1-bit half

adder and 1-bit Full adder using VHDL

AIM:

Perform Zero Delay Simulation of 1-bit half adder and 1-bit Full adder written in

behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,

Synthesize each one of them on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from


Block Diagram:

1-bit Half Adder:

1-bit Full Adder:

Truth table: Half Adder:

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Half Adder

(1-bit) A

B

Sum

Carry

Full Adder

(1-bit)

Sum

Cout

A

B

Cin


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Full Adder:

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Boolean Equation:

Half Adder:

Sum = A B

Carry = A.B

Full Adder:

Sum = A B Cin

Cout = A.B + A.Cin + B.Cin

VHDL Code:

Half Adder (Using dataflow, Behavioral Modeling):

library ieee;


entity ha_1b is

port ( a, b : in std_logic;

sum, carry : out std_logic

);

end ha_1b;

architecture ha_1b_df of ha_1b is -- dataflow modeling using with select

signal s : std_logic_vector(1 downto 0);

begin

s


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'0' when "10",

'1' when "11",

'0' when others;

end ha_1b_df;

architecture ha_1b_df1 of ha_1b is -- simple dataflow modeling using Boolean equation

begin

sum


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process (a,b)

variable v : std_logic_vector(2 downto 0);

begin

v := a & b & cin;

case v is

when "000" =>

sum


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begin

ha_1b_i1 : ha_1b port map ( a => a ,

b => b ,

sum => s1 ,

carry => s2

);

ha_1b_i2 : ha_1b port map ( a => s1 ,

b => cin ,

sum => sum ,

carry => s3

);

Org_i : org port map ( a => s3,

b => s2,

c => cout

);

end fa_1b_str;

architecture fa_1b_mixed of fa_1b is

component ha_1b


sum, carry: out std_logic

);

end component;

signal s1,s2,s3 : std_logic;

begin

ha_1b_i : ha_1b port map ( a => a , --structural modeling

b => b ,

sum => s1 ,

carry => s2

);

process (s1,cin) -- behavioral modeling

begin

sum


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entity ha_1b_tst is -- test bench for a 1-bit Half adder.

end ha_1b_tst;

architecture ha_1b_tst_a of ha_1b_tst is

component ha_1b

port (a, b : in std_logic;

sum, carry : out std_logic

);

end component;

signal a_i ,b_i, sum_i,carry_i : std_logic;

begin

nandg_i : ha_1b port map ( a => a_i,

b => b_i,

sum => sum_i,

carry => carry_i

);

process

begin

a_i


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signal a_i ,b_i, cin_i, sum_i,carry_i : std_logic;

begin

fa_1b_i : fa_1b port map ( a => a_i,

b => b_i,

cin => cin_i,

sum => sum_i,

cout => carry_i

);

process

begin

a_i


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Simulation Waveform:

Half Adder:

Full Adder:

Synthesis:

Half Adder:

EDA Tool Name: Xilinx Project Navigator 8.1

Full Adder:

EDA Tool Name: Fpga Advantage 3.1 Leonardo spectrum


Synthesis Report (Xilinx Project Navigator):

Full Adder:


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EXPERIEMENT NO. 3

Simulation using all the modeling styles and Synthesis of 2:1

Multiplexer and 4:1 Multiplexer using VHDL

Aim:

Perform Zero Delay Simulation of 2:1 Multiplexer and 4:1 Multiplexer written in

behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,

Synthesize each one of them on Xilinx 8.1 Project Navigator.




Block Diagram:

2:1 Multiplexer:

4:1 Multiplexer:

2:1

Multiplexer

A

B Y

S

Y

4:1

Multiplexer

A

B

C

D

S1 S0

D


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Truth table:

2:1 Multiplexer:

S A B Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

4:1 Multiplexer:

A B Y

0 0 A

0 1 B

1 0 C

1 1 D

Boolean Equation: 2:1 Multiplexer:

Y = A.S + B.S 4:1 Multiplexer:

Y = A.S1.S0 + B.S1.S0 + C.S1.S0 + D.S1.S0

VHDL Code:

2:1 Multiplexer ( in dataflow and behavioral modeling style) :

library ieee;


entity mux21 is

port ( a,b,s : in std_logic;

y : out std_logic

);

end mux21;

architecture mux21_df of mux21 is -- simple dataflow modeling using Boolean

equation


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begin

y

y

y

y


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y


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architecture mux41_str of mux41 is

component mux21

port ( a,b,s : in std_logic;

y : out std_logic

);

end component;

signal con1, con2 : std_logic;

begin

mux21_i1 : mux21 port map ( a => a ,

b => b ,

s => s1 ,

y => con1

);

mux21_i2 : mux21 port map ( a => c ,

b => d ,

s => s1 ,

y => con2

);

mux21_i3 : mux21 port map ( a => con1 ,

b => con2 ,

s => s0 ,

y => y

);

end mux41_str;

VHDL Test Bench:

2:1 Multiplexer:

library ieee;


entity mux21_tst is

end mux21_tst;

architecture mux21_tst_a of mux21_tst is

component mux21

port (a,b,s : in std_logic;

y : out std_logic

);

End component;

signal a,b,s,y : std_logic;

begin


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mux21_i : mux21 port map ( a => a,

b => b,

s => s,

y => y

);

process

begin

a


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s1


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EXPERIEMENT NO. 4

Simulation and Synthesis of 1:4 Demultiplexer using VHDL

Aim:

Perform Zero Delay Simulation 1:4 Demultiplexer in VHDL using a Test bench. Then,

Synthesize on Xilinx 8.1 Project Navigator.




Block Diagram:

Truth Table:

Input Select Output

A 00 Y(0)

B 01 Y(1)

C 10 Y(2)

D 11 Y(3)

Boolean Equation:

Y(3) = A.S.(1).S(0) Y(2) = B.S.(1).S(0) Y(1) = C.S.(1).S(0) Y(0) = D.S.(1).S(0)

A

1:4

Demultiplexer Y

S


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VHDL Code:

library ieee;


entity demux14 is

port ( a : in std_logic;

s : in std_logic_vector(1 downto 0);

y : out std_logic_vector(3 downto 0)

);

end demux14;

architecture demux14_df of demux14 is -- dataflow modeling using when . else begin

y y y y y y


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);

end component;

signal a : std_logic;

signal s : std_logic_vector(1 downto 0);

signal y : std_logic_vector(3 downto 0);

begin

demux14_tst_i : demux14 port map (a,s,y); -- positional association

process

begin

a


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EXPERIEMENT NO. 5

Simulation and Synthesis of 2:4 Decoder using VHDL

Aim:

Perform Zero Delay Simulation 2:4 Decoder in VHDL using a Test bench. Then,





Block Diagram:

Truth Table:

A Y

00 0001

01 0010

10 0100

11 1000

Boolean Equation:

Y(0) = A(1). A(0) Y(1) = A(1).A(0) Y(2) = A(1).A(0) Y(3) = A(1). A(0)

VHDL Code:

A

2:4

Decoder Y


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library ieee;


entity decod24 is

port ( a : in std_logic_vector(1 downto 0);


);

end decod24;

architecture decod24_beh of decod24 is -- behavioral modeling using case end case begin

process(a)

begin

case a is

when "00" => y y y y y


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a1


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EXPERIEMENT NO. 6

Simulation and Synthesis of 4:2 Encoder using VHDL

Aim:

Perform Zero Delay Simulation 4:2 Encoder in VHDL using a Test bench. Then,





Block Diagram:

Truth Table:

A Y

1000 00

0100 01

0010 10

0001 11

Boolean Equation: Y(1) = A(1) + A(0)

Y(0) = A(2) + A(0)

VHDL Code: library ieee;


entity encod42 is

port (a : in std_logic_vector(3 downto 0);


A

4:2

Encoder

Y


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);

end encod42;

architecture encod42_df of encod42 is

begin

with a select

y


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Synthesis:


Synthesis Report (Xilinx project Navigator):


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EXPERIEMENT NO. 7

Simulation and Synthesis of 4:2 Priority Encoder using VHDL

Aim:

Perform Zero Delay Simulation 4:2 Priority Encoder in VHDL using a Test bench.

Then, Synthesize on Xilinx 8.1 Project Navigator.




Block Diagram:

Truth Table:

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0

0 0 1 X 0 1

0 1 X X 1 0

1 X X X 1 1

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0

0 0 1 0 0 1

0 0 1 1 0 1

0 1 0 0 1 0

0 1 0 1 1 0

0 1 1 0 1 0

0 1 1 1 1 0

1 0 0 0 1 0

1 0 0 1 1 1

1 0 1 0 1 1

A

4:2

Priority

Encoder

Y


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1 0 1 1 1 1

1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 1 1

1 1 1 1 1 1

Boolean Equation: Y(1) = A(3) + A(2) Y (0) = A(2).A(1) + A(3).A(2) + A(3).A(0)



entity pri_encod42 is


y : out std_logic_vector(1 downto 0);

valid : out std_logic

);

end pri_encod42;

architecture pri_encod42_beh of pri_encod42 is

begin

process(a)

begin

if (a(3) = '1') then

y


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library ieee;


entity pri_encod42_tst is

end pri_encod42_tst;

architecture pri_encod42_tst_a of pri_encod42 is

component pri_encod42



);

end component;

signal a : std_logic_vector(3 downto 0);

signal y : std_logic_vector3 downto 0);

begin

pri_encod42_i : pri_encod42 port map (a,y);

process

begin

a


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a


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EXPERIEMENT NO. 8

Simulation and Synthesis of magnitude comparator 1-bit using

VHDL

Aim:

Perform Zero Delay Simulation of magnitude comparator 1-bit in VHDL using a Test

bench. Then, Synthesize on Xilinx 8.1 Project Navigator.




Block Diagram:

Truth Table:

A B AgtB AltB AeqB

0 0 0 0 1

0 1 0 1 0

1 0 1 0 0

1 1 0 0 1

Boolean Equation: AgtB = A.B AltB = A.B AeqB = A.B + A.B



use ieee.std_logic_arith.all;

A

Magnitude

Comparator

1-bit B

AltB

AgtB

AeqB


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use ieee.std_logic_unsigned.all;

entity magcomp1 is


agtb, aeqb, altb : out boolean

);

end magcomp1;

architecture magcomp1_df of magcomp1 is

begin

agtb b;

altb


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end process;

end magcomp1_tst_a;


Synthesis:




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EXPERIEMENT NO. 9

Simulation and Synthesis of D latch and D flip flop using VHDL

Aim:

Perform Zero Delay Simulation of d latch and d flip flop in VHDL using a Test bench.

Then, Synthesize on Xilinx 8.1 Project Navigator.




VHDL Code: D-latch:

library ieee;


entity dlatch is

port (d,en,reset : in std_logic;

q : out std_logic

);

end dlatch;

architecture dlatch_beh of dlatch is

signal s : std_logic;

begin

process(d,en,reset)

begin

if (reset = 1) then s


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process(d,en,reset)

variable s : std_logic;

begin

if (reset = 1) then s :=0; elsif (en = 1) then s := d;

else

s := s;

end if;

q


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end process;

end dff_asyncrst_a;

architecture dff_syncrst_a of dff is

begin

process(clk)

begin

if( clk'event and clk = '1') then

if (reset = '1') then

q


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d


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EXPERIEMENT NO. 10

Simulation and Synthesis of JK, T Flip Flop using VHDL

Aim:

Perform Zero Delay Simulation of JK, T, Flip flop in VHDL using a Test bench. Then,





VHDL Code:

JK-flip flop:

library ieee;


entity JKff is

port (j,k,clk,reset : in std_logic;

q : out std_logic

);

end JKff;

architecture JKff_beh of JKff is


begin

process(clk,reset)

begin


s


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end if;

end process;

end JKff_beh;

T-flip flop:

library ieee;


entity tff is

port (t,clk,reset : in std_logic;

q : out std_logic

);

end tff;

architecture tff_beh of tff is


begin

process(clk,reset)

begin


s


Prepared By:


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q : out std_logic

);

end component;

signal j,k,reset,q : std_logic;

signal clk : std_logic := '1';

begin

JKff_i : JKff port map (j,k,clk,reset,q);

clk


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tff_i : tff port map ( t,clk,reset,q);

clk


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EXPERIEMENT NO. 11

Simulation using all the modeling styles and Synthesis of all the

logic gates using Verilog HDL

AIM:

Perform Zero Delay Simulation of all the logic gates

written in behavioral, dataflow and structural modeling style in Verilog using a

Test bench. then, Synthesize each one of them on two different EDA tools.



Block Diagram:

Truth table:

And Gate: Or Gate:

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

Nand Gate: Nor Gate:

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

And, Nand,

Or, Nor,

Xor, Xnor

A

B

C

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

A B Y

0 0 1

0 1 1

1 0 1

1 1 0


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Xor Gate: Xnor Gate:

A B Y

0 0 1

0 1 0

1 0 0

1 1 1

Boolean Equation:

And Gate: Y = (A.B) Or Gate: Y = (A + B) Nand Gate: Y = (A.B) Nor Gate: Y = (A+B) Xor Gate: Y = A.B + A.B Xnor Gate: Y = A.B + A.B

Verilog Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):

Module andg(a,b,c);

input a,b;

output c;

assign c = a & b;

endmodule

Module andg1(a,b,c);

input a,b;

always(a,b)

begin

if (a==1b0 or b == 1b0) c = 1b0; else if (a==1b0 or b == 1b1) c = 1b0; else if (a==1b1 or b == 1b0) c = 1b0; else if (a==1b1 or b == 1b1) c = 1b1; end

endmodule

Or gate(Dataflow, behavioral modeling):

Module org (a,b,c);

input a,b;

output c;

assign c = a | b;

A B Y

0 0 0

0 1 1

1 0 1

1 1 0


Prepared By:


[email protected]

endmodule

Nand Gate (In Dataflow modeling):

Module nandg (a,b,c);

input a,b;

output c;

assign c = ~(a & b);

endmodule

Nor Gate (In Dataflow modeling):

Module norg (a,b,c);

input a,b;

output c;

assign c = ~(a | b);

endmodule

Xor gate(In Dataflow modeling):

Module xorg (a,b,c);

input a,b;

output c;

assign c = a ^ b;

endmodule

Module xorg2 (a,b,c);

input a,b;

output c;

assign c = (~a & b) | (a & ~b);

endmodule

Xnor Gate (In Dataflow modeling):

Module xnorg (a,b,c);

input a,b;

output c;

assign c = ~(a ^ b);

endmodule

Test Bench (Applicable to all the logic gates): module nandg_tst_v;

reg a;


Prepared By:


[email protected]

reg b;

wire c;

nandg uut (

.a(a),

.b(b),

.c(c)

);

initial

begin

a = 0;

b = 0;

#100 a = 0;

b = 1;

#100 a = 1;

b = 0;

#100 a = 1;

b = 1;

end

endmodule

Simulation Waveform: Nand Gate:


Prepared By:


[email protected]

Synthesis (Xor gate):



===============================================================

* Synthesis Options Summary *

===============================================================

---- Source Parameters

Input File Name : "xorg.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "xorg"

Output Format : NGC

Target Device : xc3s50-5-pq208

* Final Report *

===============================================================

Final Results


Prepared By:


[email protected]

RTL Top Level Output File Name : xorg.ngr

Top Level Output File Name : xorg

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : NO

Design Statistics

# IOs : 3

Cell Usage :

# BELS : 1

# LUT2 : 1

# IO Buffers : 3

# IBUF : 2

# OBUF : 1

===============================================================

==========

Device utilization summary:

---------------------------

Selected Device : 3s50pq208-5

Number of Slices: 1 out of 768 0%

Number of 4 input LUTs: 1 out of 1536 0%

Number of IOs: 3

Number of bonded IOBs: 3 out of 124 2%

Timing Summary:

---------------

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 7.760ns


Prepared By:


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EXPERIEMENT NO. 12

Simulation using all the modeling styles and Synthesis of 1-bit half

adder and 1-bit Full adder using verilog HDL

AIM:

Perform Zero Delay Simulation of 1-bit half adder and 1-bit Full adder written in

behavioral, dataflow and structural modeling style in VERILOG HDL using a Test

bench. Then, Synthesize each one of them on two different EDA tools.



Block Diagram:

1-bit Half Adder:

1-bit Full Adder:

Truth table: Half Adder:

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1 Full Adder:

Half Adder

(1-bit) A

B

Sum

Carry

Full Adder

(1-bit)

Sum

Cout

A

B

Cin


Prepared By:


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A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Boolean Equation:

Half Adder:

Sum = A B

Carry = A.B

Full Adder:

Sum = A B Cin

Cout = A.B + A.Cin + B.Cin

VERILOG HDL Code:

Half Adder (Using dataflow, Behavioral Modeling):

module ha(a, b, s, co);

input a;

input b;

output s;

output co;

assign s = a ^ b;

assign co = a &b;

endmodule

module ha1(a, b, s, co);

input a;

input b;

output s;

output co;

reg s,co;

always @(a or b)

begin

s = a ^ b;

co = a &b;

end


Prepared By:


[email protected]

endmodule

Full Adder (Using dataflow, Behavioral Modeling, Structural Modeling):

module fa(a, b, cin, sum, cout);

input a;

input b;

input cin;

output sum;

output cout;

assign sum = a ^ b ^ cin;

assign cout = (a& b) |(b & cin) |(a & cin);

endmodule

module fa1(a, b, cin, sum, cout);

input a;

input b;

input cin;

output sum;

output cout;

reg sum,cout;

always @(a or b or cin)

begin

case ({a,b,cin})

3'b000: begin

sum = 1'b0;

cout = 1'b0;

end

3'b001: begin

sum = 1'b1;

cout = 1'b0;

end

3'b010: begin

sum = 1'b1;

cout = 1'b0;

end

3'b011: begin

sum = 1'b0;

cout = 1'b1;

end

3'b100: begin

sum = 1'b1;

cout = 1'b0;

end

3'b101: begin

sum = 1'b0;


Prepared By:


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cout = 1'b1;

end

3'b110: begin

sum = 1'b0;

cout = 1'b1;

end

3'b111: begin

sum = 1'b1;

cout = 1'b1;

end

default: begin

sum = 1'b0;

cout = 1'b0;

end

endcase

end

endmodule

module fa2(a, b, cin, sum, cout);

input a;

input b;

input cin;

output sum;

output cout;

wire w1, w2, w3;

ha ha_i1 (.a(a),

.b(b),

.s(w1),

.co(w3)

);

ha ha_i2 (.a(w1),

.b(cin),

.s(sum),

.co(w2)

);

org org_i (.a(w2),

.b(w3),

.c(cout)

);

endmodule

VERILOG HDL Test Bench:

Half Adder:


Prepared By:


[email protected]

module ha_tst_v;

reg a;

reg b;

wire s;

wire co;

ha1 uut (

.a(a),

.b(b),

.s(s),

.co(co)

);

initial

begin

a = 0;

b = 0;

#100 a = 0;

b = 1;

#100 a = 1;

b = 0;

#100 a = 1;

b = 1;

end

endmodule;

Full Adder:

module fa_tst_v;

reg a;

reg b;

reg cin;

wire sum;

wire cout;

fa uut (

.a(a),

.b(b),

.cin(cin),

.sum(sum),

.cout(cout)

);

initial

begin

a = 0;

b = 0;

cin = 0;


Prepared By:


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#100 a = 0;

b = 0;

cin = 1;

#100 a = 0;

b = 1;

cin = 0;

#100 a = 0;

b = 1;

cin = 1;

#100 a = 1;

b = 0;

cin = 0;

#100 a = 1;

b = 0;

cin = 1;

#100 a = 1;

b = 1;

cin = 0;

#100 a = 1;

b = 1;

cin = 1;

end

endmodule


Half Adder:


Prepared By:


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Full Adder:

Synthesis:

Half Adder:



Prepared By:


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Full Adder:



Prepared By:


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Synthesis Report (Xilinx Project Navigator):

Full Adder:

======================================================*

Synthesis Options Summary *

---- Source Parameters

Input File Name : "fa2.prj"




Output File Name : "fa2"

Output Format : NGC


===============================================================

* HDL Analysis *

===============================================================

Analyzing top module .

Module is correct for synthesis.

Analyzing module in library .


Analyzing module in library .


===============================================================

* HDL Synthesis *

===============================================================

Performing bidirectional port resolution...

Synthesizing Unit .

Related source file is "ha.v".

Found 1-bit xor2 for signal .

Unit synthesized.

Synthesizing Unit .

Related source file is "org.v".

Unit synthesized.

Synthesizing Unit .

Related source file is "fa.v".

Unit synthesized.

===============================================================

HDL Synthesis Report


Prepared By:


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Macro Statistics

# Xors : 2

1-bit xor2 : 2

======================================================

* Advanced HDL Synthesis *

======================================================

Loading device for application Rf_Device from file '3s50.nph' in environment C:\Xilinx.

======================================================

Advanced HDL Synthesis Report

Macro Statistics

# Xors : 2

1-bit xor2 : 2

====================================================== * Final Report *

=====================================================================

Final Results

RTL Top Level Output File Name : fa2.ngr

Top Level Output File Name : fa2

Output Format : NGC


Keep Hierarchy : NO

Design Statistics

# IOs : 5

Cell Usage :

# BELS : 2

# LUT3 : 2

# IO Buffers : 5

# IBUF : 3

# OBUF : 2

=====================================================================


---------------------------


Number of Slices: : 1 out of 768 0%

Number of 4 input LUTs : 2 out of 1536 0%

Number of IOs: : 5

Number of bonded IOBs: : 5 out of 124 4%


Prepared By:


[email protected]

EXPERIEMENT NO. 13

Simulation using all the modeling styles and Synthesis of 2:1

Multiplexer and 4:1 Multiplexer using VERILOG HDL

Aim:

Perform Zero Delay Simulation of 2:1 Multiplexer and 4:1 Multiplexer written in

behavioral, dataflow and structural modeling style in VERILOG HDL using a Test

bench. Then, Synthesize each one of them on two different EDA tools.




Block Diagram:

2:1 Multiplexer:

4:1 Multiplexer:

2:1

Multiplexer

A

B Y

S

Y

4:1

Multiplexer

A

B

C

D

S1 S0

D


Prepared By:


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Truth table:

2:1 Multiplexer:

S A B Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

4:1 Multiplexer:

A B Y

0 0 A

0 1 B

1 0 C

1 1 D

Boolean Equation: 2:1 Multiplexer:

Y = A.S + B.S 4:1 Multiplexer:

Y = A.S1.S0 + B.S1.S0 + C.S1.S0 + D.S1.S0

VERILOG HDL Code:

2:1 Multiplexer ( in dataflow and behavioral modeling style) :

module mux21(a, b, s, c);

input a;

input b;

input s;

output c;

assign c = s ? a : b;

endmodule

module mux21a(a, b, s, c);

input a;


Prepared By:


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input b;

input s;

output c;

reg c;

always @(a or b or s)

begin

if (s)

c = a;

else

c = b;

end

endmodule

4:1 Multiplexer( in behavioral, dataflow and structural modeling styles):

module mux41(a, s,c);

input [3:0] a;

input [1:0] s;

output c;

assign c = (!s[0] & !s[1] & a[0]) | (s[0] & !s[1] & a[1]) | (!s[0] & s[1] & a[2]) | (s[0] &

s[1] & a[3]);

endmodule

module mux41a (a,s,c);

input [3:0] a;

input [1:0] s;

output c;

reg c;

always @(a or s)

begin

case(s)

2'b00: c = a[0];

2'b01: c = a[1];

2'b10: c = a[2];

2'b11: c = a[3];

default: c = a[0];

endcase

end

endmodule

module mux41b (a,s,c);

input [3:0] a;


Prepared By:


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input [1:0] s;

output c;

wire w1,w2;

mux21 mux21_i1 (.a(a[0]),

.b(a[1]),

.s(s[1]),

.c(w1)

);

mux21 mux21_i2 (.a(a[2]),

.b(a[3]),

.s(s[1]),

.c(w2)

);

mux21 mux21_i3 (.a(w1),

.b(w2),

.s(s[0]),

.c(c)

);

endmodule

VERILOG HDL Test Bench: 2:1 Multiplexer:

module mux21_tst_v;

reg a;

reg b;

reg s;

wire c;

mux21 uut (

.a(a),

.b(b),

.s(s),

.c(c) );

initial

begin

a = 0;

b = 1;

s = 0;

#100

s = 1;

end

endmodule


Prepared By:


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4: 1 Multiplexer:

module mux41_tst_v;

reg [3:0] a;

reg [1:0] s;

wire c;

mux41 uut (

.a(a),

.s(s),

.c(c)

);

initial

begin

a = 4'b0101;

s = 2'b00;

#100 s = 2'b00;

#100 s = 2'b01;

#100 s = 2'b10;

#100 s = 2'b11;

end

endmodule

Simulation Waveform: Mux41:


Prepared By:


[email protected]

Synthesis:

2 :1 Multiplexer:



Prepared By:


[email protected]

4 :1 Multiplexer:



Prepared By:


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Synthesis Report:

===============================================================

* Synthesis Options Summary *

===============================================================-

--- Source Parameters

Input File Name : "mux41.prj"


Prepared By:


[email protected]




Output File Name : "mux41"

Output Format : NGC


===============================================================

* HDL Compilation *

===============================================================

Compiling verilog file "mux21.v" in library work

Module compiled

Compiling verilog file "mux41.v" in library work

Module compiled

Module compiled

Module compiled

Module compiled

No errors in compilation

Analysis of file succeeded.

===============================================================

* Final Report *

===============================================================

Final Results

RTL Top Level Output File Name : mux41.ngr

Top Level Output File Name : mux41

Output Format : NGC


Keep Hierarchy : NO

Design Statistics

# IOs : 7

Cell Usage :

# BELS : 3

# LUT3 : 2

# MUXF5 : 1

# IO Buffers : 7

# IBUF : 6

# OBUF : 1

===============================================================


---------------------------


Prepared By:


[email protected]


Number of Slices: 1 out of 768 0%

Number of 4 input LUTs: 2 out of 1536 0%

Number of IOs: 7

Number of bonded IOBs: 7 out of 124 5%


Prepared By:


[email protected]

EXPERIEMENT NO. 14

Simulation and Synthesis of 1:4 Demultiplexer using VERILOG

HDL

Aim:

Perform Zero Delay Simulation 1:4 Demultiplexer in VERILOG HDL using a Test

bench. Then, Synthesize on two different EDA tools.



Block Diagram:

Truth Table:

Input Select Output

A 00 Y(0)

B 01 Y(1)

C 10 Y(2)

D 11 Y(3)

Boolean Equation:

Y(3) = A.S.(1).S(0) Y(2) = B.S.(1).S(0) Y(1) = C.S.(1).S(0) Y(0) = D.S.(1).S(0)

VERILOG HDL Code:

A

1:4

Demultiplexer Y

S


Prepared By:


[email protected]

module demux12(a, s, c);

input a;

input s;

output [1:0] c;

assign c[1] = a & ~ s;

assign c[0] = a & s;

endmodule

module demux12a(a, s, c);

input a;

input s;

output [1:0] c;

reg c;

always @(a or s)

begin

if (s)

c = (a & ~s);

else

c = (a & s);

end

endmodule

VERILOG HDL test bench:

module demux12_tst_v;

reg a;

reg s;

wire [1:0] c;

demux12 uut (

.a(a),

.s(s),

.c(c) );

initial

begin

a = 0;

s = 0;

#10; s = 1;

end

endmodule


Prepared By:


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Synthesis:



Prepared By:


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EXPERIEMENT NO. 15

Simulation and Synthesis of 2:4 Decoder using VERILOG HDL

Aim:

Perform Zero Delay Simulation 2:4 Decoder in VERILOG HDL using a Test bench.

Then, Synthesize on two different EDA tools.




Block Diagram:

Truth Table:

A Y

00 0001

01 0010

10 0100

11 1000

Boolean Equation:

Y(0) = A(1). A(0) Y(1) = A(1).A(0) Y(2) = A(1).A(0) Y(3) = A(1). A(0)

VERILOG HDL Code:

A

2:4

Decoder Y


Prepared By:


[email protected]

module decoder24 (a,b);

input [1:0] a;

output [3:0]b;

reg [3:0] b;

always @(a)

begin

b[3] = a[1] & a[0];

b[2] = !a[1] & a[0];

b[1] = a[1] & !a[0];

b[0] = !a[1] & !a[0];

end

endmodule


module decoder_tst_v;

reg [1:0] a;

wire [3:0] b;

decoder24 uut (

.a(a),

.b(b)

);

initial

begin

a = 2'b00;

#100 a = 2'b01;

#100 a = 2'b10;

#100 a = 2'b11;

end

endmodule


Prepared By:


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Synthesis:



Prepared By:


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Prepared By:


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EXPERIEMENT NO. 16

Simulation and Synthesis of 4:2 Encoder using VERILOG HDL

Aim:

Perform Zero Delay Simulation 4:2 Encoder in VERILOG HDL using a Test bench.

Then, Synthesize on two different EDA tools.



Block Diagram:

Truth Table:

A Y

1000 00

0100 01

0010 10

0001 11

Boolean Equation: Y(1) = A(1) + A(0)

Y(0) = A(2) + A(0)

VERILOG HDL Code:

module encoder24(a, b);

input [3:0] a;

output [1:0] b;

reg [1:0] b;

always @(a)

A

4:2

Encoder

Y


Prepared By:


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begin

case (a)

4'b0001: b = 2'b00;

4'b0010: b = 2'b01;

4'b0100: b = 2'b10;

4'b1000: b = 2'b11;

default: b = 2'b00;

endcase

end

endmodule


module encoder_tst_v;

reg [3:0] a;

wire [1:0] b;

decoder24 uut (

.a(a),

.b(b)

);

initial

begin

a = 4'b0001;

#100 a = 4'b0010;

#100 a = 4'b0100;

#100 a = 4'b1000;

#100 $stop;

end

endmodule


Prepared By:


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Synthesis:



Prepared By:


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Prepared By:


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EXPERIEMENT NO. 17

Simulation and Synthesis of 4:2 Priority Encoder using

VERILOG HDL

Aim:

Perform Zero Delay Simulation 4:2 Priority Encoder in VERILOG HDL using a Test

bench. Then, Synthesize on two different EDA tools.




Block Diagram:

Truth Table:

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0

0 0 1 X 0 1

0 1 X X 1 0

1 X X X 1 1

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0

0 0 1 0 0 1

0 0 1 1 0 1

0 1 0 0 1 0

0 1 0 1 1 0

0 1 1 0 1 0

0 1 1 1 1 0

1 0 0 0 1 0

1 0 0 1 1 1

A

4:2

Priority

Encoder

Y


Prepared By:


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1 0 1 0 1 1

1 0 1 1 1 1

1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 1 1

1 1 1 1 1 1

Boolean Equation: Y(1) = A(3) + A(2) Y (0) = A(2).A(1) + A(3).A(2) + A(3).A(0)

VERILOG HDL Code:

module pri_encoder42(a, b);

input [3:0] a;

output [1:0] b;

reg [1:0] b;

always @(a)

begin

if (a[3])

b = 2'b00;

else if (a[2])

b = 2'b01;

else if(a[1])

b = 2'b10;

else if (a[0])

b = 2'b11;

end

endmodule

VERILOG HDL Test Bench: module pri_encoder_tst_v;

reg [3:0] a;

wire [1:0] b;

pri_encoder42 uut (

.a(a),

.b(b)

);

initial

begin

a = 4'b0001;

#10 a = 4'b0010;

#10 a = 4'b0011;


Prepared By:


[email protected]

#10 a = 4'b0100;

#10 a = 4'b0101;

#10 a = 4'b0110;

#10 a = 4'b0111;

#10 a = 4'b1000;

#10 a = 4'b1001;

#10 a = 4'b1010;

#10 a = 4'b1011;

#10 a = 4'b1100;

#10 a = 4'b1101;

#10 a = 4'b1110;

#10 a = 4'b1111;

#10 $stop;

end

endmodule



Prepared By:


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Synthesis:



Prepared By:


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EXPERIEMENT NO. 18

Simulation and Synthesis of magnitude comparator 1-bit using

VERILOG HDL

Aim:

Perform Zero Delay Simulation of magnitude comparator 1-bit in VERILOG HDL

using a Test bench. Then, Synthesize on two different EDA tools.



Block Diagram:

Truth Table:

A B AgtB AltB AeqB

0 0 0 0 1

0 1 0 1 0

1 0 1 0 0

1 1 0 0 1

Boolean Equation: AgtB = A.B AltB = A.B AeqB = A.B + A.B

VERILOG HDL Code:

module magcomp1(a, b, agtb, aeqb, altb);

input a;

A

Magnitude

Comparator

1-bit B

AltB

AgtB

AeqB


Prepared By:


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input b;

output agtb;

output aeqb;

output altb;

assign agtb = (a > b);

assign altb = (a < b);

assign aeqb = (a ==b);

endmodule

VERILOG HDL Test Bench: module magcomp1_tst_v;

reg a;

reg b;

wire agtb;

wire aeqb;

wire altb;

magcomp1 uut (

.a(a),

.b(b),

.agtb(agtb),

.aeqb(aeqb),

.altb(altb) );

initial

begin

a = 0;

b = 0;

#100 a = 0; b = 1;

#100 a = 1; b = 0;

#100 a = 1; b = 1;

end

endmodule


Prepared By:


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Synthesis:

EDA Tool Name: Xilinx Project Navigator 8.1:


Prepared By:


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EXPERIEMENT NO. 19

Simulation and Synthesis of D flip flop using VERILOG HDL

Aim:

Perform Zero Delay Simulation of d flip flop in VERILOG HDL using a Test bench.

Then, Synthesize on EDA tool.



VERILOG HDL Code: D-flip flop with asynchronous and synchronous reset:

module dff(d, clk, reset, q);

input d;

input clk;

input reset;

output q;

reg q;

always @(posedge clk or posedge reset)

begin


Prepared By:


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if (reset)

q


Prepared By:


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#5 clk = ~ clk;

endmodule


Synthesis:



Prepared By:


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EXPERIEMENT NO. 20

Simulation and Synthesis of JK, T Flip Flop using VERILOG

HDL

Aim:

Perform Zero Delay Simulation of JK, T, Flip flop in VERILOG HDL using a Test

bench. Then, Synthesize on EDA tools.



VERILOG HDL Code:

JK-flip flop:

module jkff(j, k, clk, reset, q);

input j;

input k;

input clk;


Prepared By:


[email protected]

input reset;

output q;

reg q;


begin

if(reset == 1'b1)

q


Prepared By:


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jkff uut (

.j(j),

.k(k),

.clk(clk),

.reset(reset),

.q(q) );

initial

begin

j = 0;

k = 0;

clk = 1;

reset = 1;

#20 reset = 0;

#10 j = 0;

k = 1;

#10 j = 1;

k = 0;

#10 j = 1;

k = 1;

end

always

#5 clk = ~ clk;

endmodule

Test Bench of T flip flop:

module tff_tst_v;

reg t;

reg clk;

reg reset;

wire q;

tff uut (

.t(t),

.clk(clk),

.reset(reset),

.q(q)

);

initial

begin

t = 0;

clk = 1;

reset = 1;

#20 reset = 1'b0;


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t = 1'b1;

#20 t = 1'b0;

#30 t = 1'b1;

end

always

#5 clk = ~ clk;

endmodule


JKFF:


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TFF:

Synthesis:

JKFF:


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TFF:


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EXPERIEMENT NO. 21

Simulation and Synthesis of SISO, SIPO, PIPO shift registers

using VERILOG HDL

Aim:

Perform Zero Delay Simulation of SISO, SIPO, PIPO shift registers in VERILOG HDL

using a Test bench. Then, Synthesize on EDA tools.



VERILOG HDL Code:

SISO shift register:

module siso(sin, clk, reset, sout);

input sin;

input clk;

input reset;

output sout;

wire w1,w2,w3;

dff abc1 (.d(sin),

.clk(clk ),

.reset(reset),

.q(w1)

);

dff abc2 (.d(w1),

.clk(clk),

.reset(reset),

.q(w2)

);

dff abc3 (.d(w2),

.clk(clk),

.reset(reset),

.q(w3)

);

dff abc4 (.d(w3),


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.clk(clk),

.reset(reset),

.q(sout)

);

endmodule

module siso1(sin, clk, reset, sout);

input sin;

input clk;

input reset;

output sout;

reg sout;

reg r1,r2,r3;


begin

if (!reset)

begin

sout


Prepared By:


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dff a2 (.d(pout[0]),

.clk(clk),

.reset(reset),

.q(pout[1])

);


.clk(clk),

.reset(reset),

.q(pout[2])

);


.clk(clk),

.reset(reset),

.q(pout[3])

);

endmodule

PIPO:

module pipo(pin, clk, reset, pout);

input [3:0] pin;

input clk;

input reset;

output [3:0] pout;

reg [3:0] pout;

always @ (posedge clk or posedge reset)

begin

if (reset)

pout


Prepared By:


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wire sout;

siso uut ( .sin(sin),

.clk(clk),

.reset(reset),

.sout(sout)

);

initial

begin

sin = 0;

clk = 1;

reset = 1;

#20 reset = 0;

sin = 1'b1;

#10 sin = 1'b0;

#10 sin = 1'b1;

#10 sin = 1'b1;

#40;

end

always

#5 clk = ~ clk;

endmodule

Test Bench of SIPO:

module sipo_tst_v;

reg sin;

reg clk;

reg reset;

wire [3:0] pout;

sipo uut ( .sin(sin),

.clk(clk),

.reset(reset),

.pout(pout)

);

initial

begin

sin = 0;

clk = 1;

reset = 1;

#300

reset = 1'b0;

sin = 1'b1;


Prepared By:


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#100 sin = 1'b0;

#100 sin = 1'b1;

#100 sin = 1'b1;

end

always

#50 clk = ~ clk;

endmodule

Test Bench for PIPO:

module pipo_tst_v;

reg [3:0] pin;

reg clk;

reg reset;

wire [3:0] pout;

pipo uut ( .pin(pin),

.clk(clk),

.reset(reset),

.pout(pout)

);

initial

begin

pin = 4'b0000;

clk = 1;

reset = 1;

#100 reset = 0;

pin = 4'b1010;

#100 pin = 4'b0110;

end

always

#50 clk = ~ clk;

endmodule


Prepared By:


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SISO:

SIPO:


Prepared By:


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PIPO:

Synthesis:

SISO:


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SIPO:

PIPO:


Prepared By:


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Prepared By:


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EXPERIEMENT NO. 22

Simulation and Synthesis of Asynchronous counter and

synchronous counter using VERILOG HDL

Aim:

Perform Zero Delay Simulation of asynchronous and synchronous counter in VERILOG

HDL using a Test bench. Then, Synthesize on EDA tools.



VERILOG HDL Code:

Asynchronous up counter:

module asynccnt3 (clk, reset, count);

input clk;

input reset;

output [2:0] count;

tff a1 (.t(1'b1),

.clk (clk),

.reset (reset),

.q(count[0]) );

tff a2 (.t(1'b1),

366605_634850313970487500

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