331 W02.1Spring 05 Announcements HW1 is due on this Friday Appendix A (on CD) is very helpful to HW1.

331 W02.1 Spring 05

Announcements

HW1 is due on this Friday

Appendix A (on CD) is very helpful to HW1.

331 W02.2 Spring 05

Review I: Execute Cycle

Q1: How does control know which instruction to fetch?

Q2: who does decode? What happens in decode phase?

Q3: How do control and datapath interact to finish exec phase?

Q4: What does datapath have?

Fetch

DecodeExec

331 W02.3 Spring 05

Review II: word length

What does 32-bit architecture mean?

331 W02.4 Spring 05

Assembly Language

Language of the machine

More primitive than higher level languagese.g., no sophisticated control flow

Very restrictivee.g., MIPS arithmetic instructions

We’ll be working with the MIPS instruction set architecture similar to other architectures developed since the 1980's used by NEC, Nintendo, Silicon Graphics, Sony, … 32-bit architecture

- 32 bit data line and address line- data and addresses are 32-bit

331 W02.5 Spring 05

MIPS R3000 Instruction Set Architecture

Instruction Categories Load/Store Computational Jump and Branch Floating Point

- coprocessor

Memory Management Special

R0 - R31

PCHI

LO

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

Registers

Q: How many already familiar with MIPS ISA?

331 W02.6 Spring 05

MIPS Arithmetic Instruction

MIPS assembly language arithmetic statement

add $t0, $s1, $s2

sub $t0, $s1, $s2

Each arithmetic instruction performs only one operation

Each arithmetic instruction specifies exactly three operands

destination source1 op source2

Those operands are contained in the datapath’s register file ($t0, $s1,$s2)

Operand order is fixed (destination first)

331 W02.7 Spring 05

Compiling More Complex Statements

Assuming variable b is stored in register $s1, c is stored in $s2, d is stored in $s3 and the result is to be left in $s0, and $t0 is a temporary register, what is the assembler equivalent to the C statement

h = (b - c) + d

331 W02.8 Spring 05

Registers

Registers are Faster than main memory Can hold variables so that

- code density improves (since registers are named with fewer bits than a memory location) – why is that?

Register addresses are indicated by using $

331 W02.9 Spring 05

MIPS Register File

Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file

Holds thirty-two 32-bit registers- With two read ports and

- One write portRegister File

src1 addr

src2 addr

dst addr

write data

32 bits

src1data

src2data

32locations

325

32

5

5

32

331 W02.10 Spring 05

0 $zero constant 0

1 $at reserved for assembler

2 $v0 expression evaluation &

3 $v1 function results

4 $a0 arguments

5 $a1

6 $a2

7 $a3

8 $t0 temporary: caller saves

. . . (callee can clobber)

15 $t7

Naming Conventions for Registers

16 $s0 callee saves

. . . (caller can clobber)

23 $s7

24 $t8 temporary (cont’d)

25 $t9

26 $k0 reserved for OS kernel

27 $k1

28 $gp pointer to global area

29 $sp stack pointer

30 $fp frame pointer

31 $ra return address

331 W02.11 Spring 05

Registers vs. Memory

Arithmetic instructions operands must be registers,

— only thirty-two registers provided

What about programs with lots of variables? Store variables in the memory Load variables from memory to registers before use;

store them back to memory after use.

Processor

Control

Datapath

Memory

Devices

Input

Output

331 W02.12 Spring 05

MIPS has two basic data transfer instructions for accessing memorylw $t0, 4($s3) #load word from memory

sw $t0, 8($s3) #store word to memory

The data transfer instruction must specify where in memory to read from (load) or write to (store) –

memory address where in the register file to write to (load) or read from

(store) – register destination (source)

The memory address is formed by summing the constant portion of the instruction and the contents of the second register

Accessing Memory

331 W02.13 Spring 05

Memory is viewed as a large, single-dimension array, with an address

A memory address is an index into the array

Processor – Memory Interconnections

ProcessorMemory Addressable

locations

read addr/write addr

read data

write data

32

32

32

232

Q: what should be the smallest addressable unit?

331 W02.14 Spring 05

MIPS Data Types

Integer: (signed or unsigned) 32 bits

Character: 8 bits

Floating point numbers: 32 bits

Memory addresses (pointers): 32 bits

Instructions: 32 bits

Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word

331 W02.15 Spring 05

Byte Addresses

Since 8-bit bytes are so useful, most architectures address individual bytes in memory

memory: 232 bytes = 230 words

Therefore, the memory address of a word must be a multiple of 4 (alignment restriction)

Alignment restriction: requires that objects fall on address that is multiple of their size.

0 1 2 3

Aligned

NotAligned

331 W02.16 Spring 05

Addressing Objects: Endianess and Alignment Big Endian: leftmost byte is word address

IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA

Little Endian: rightmost byte is word addressIntel 80x86, DEC Vax, DEC Alpha (Windows NT)

msb lsb

3 2 1 0

little endian byte 0

0 1 2 3big endian byte 0

331 W02.17 Spring 05

MIPS Memory Addressing The memory address is formed by summing the

constant portion of the instruction and the contents of the second (base) register

lw $t0, 4($s3) #what? is loaded into $t0

sw $t0, 8($s3) #$t0 is stored where?

Memory

. . . 0 1 0 0Data Word Address

0

4

8

12

16

20

24

. . . 1 0 0 0

. . . 0 0 1 0

. . . 0 0 0 1

. . . 1 1 0 0

. . . 0 1 0 1

. . . 0 1 1 0$s3 holds 8

331 W02.18 Spring 05

Compiling with Loads and Stores

Assuming variable b is stored in $s2 and that the base address of integer array A is in $s3, what is the MIPS assembly code for the C statement

A[8] = A[2] - b

$s3+4

$s3+8

$s3+12

$s3

. . .

A[2]

A[3]

. . .

A[1]

A[0]

331 W02.19 Spring 05

Compiling with a Variable Array Index

Assuming A is an integer array whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement

c = A[i] - b

331 W02.20 Spring 05

MIPS Instructions, so far

Category Instr Op Code Example Meaning

Arithmetic

(R format)

add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3

Data

transfer

(I format)

load word 35 lw $s1, 100($s2) $s1 = Memory($s2+100)

store word 43 sw $s1, 100($s2) Memory($s2+100) = $s1

331 W02.21 Spring 05

Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18

Instruction Format:

Can you guess what the field names stand for?

Machine Language - Arithmetic Instruction

op rs rt rd shamt funct

000000 10001 10010 01000 00000 100000

331 W02.22 Spring 05

MIPS Instruction Fields

op

rs

rt

rd

shamt

funct

op rs rt rd shamt funct6 bits 5 bits 5 bits 5

bits5 bits

6 bits

= 32 bits

331 W02.23 Spring 05

Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise

Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register

Example: lw $t0, 24($s2)

Where's the compromise?

Machine Language - Load Instruction

op rs rt 16 bit number

35 18 8 24

100011 10010 01000 0000000000011000

331 W02.24 Spring 05

Memory Address Location

Example: lw $t0, 24($s2)Memory

data word address (hex)0x000000000x000000040x000000080x0000000c

0xf f f f f f f f

$s2 0x12004094

0x00000002

2410 + $s2 =

Note that the offset can be positive or negative

331 W02.25 Spring 05

Example: sw $t0, 24($s2)

A 16-bit address means access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register $s2

Machine Language - Store Instruction

op rs rt 16 bit number

43 18 8 24

101011 10010 01000 0000000000011000

331 W02.26 Spring 05

Assembling Code Remember the assembler code we compiled for the C

statement

A[8] = A[2] - b

lw $t0, 8($s3) #load A[2] into $t0sub $t0, $t0, $s2 #subtract b from A[2]sw $t0, 32($s3) #store result in A[8]

Assemble the MIPS object code for these three instructions

331 W02.27 Spring 05

Review: MIPS Data Types

Integer: (signed or unsigned) 32 bits

Character: 8 bits

Floating point numbers: 32 bits

Memory addresses (pointers): 32 bits

Instructions: 32 bits

Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word

331 W02.28 Spring 05

Beyond Numbers Most computers use 8-bit bytes to represent characters with the

American Std Code for Info Interchange (ASCII)

So, we need instructions to move bytes around

ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char

0 Null 32 space

48 0 64 @ 96 ` 112 p

1 33 ! 49 1 65 A 97 a 113 q

2 34 “ 50 2 66 B 98 b 114 r

3 35 # 51 3 67 C 99 c 115 s

4 EOT 36 $ 52 4 68 D 100 d 116 t

5 37 % 53 5 69 E 101 e 117 u

6 ACK 38 & 54 6 70 F 102 f 118 v

7 39 ‘ 55 7 71 G 103 g 119 w

8 bksp 40 ( 56 8 72 H 104 h 120 x

9 tab 41 ) 57 9 73 I 105 i 121 y

10 LF 42 * 58 : 74 J 106 j 122 z

11 43 + 59 ; 75 K 107 k 123 {

12 FF 44 , 60 < 76 L 108 l 124 |

15 47 / 63 ? 79 O 111 o 127 DEL

331 W02.29 Spring 05

Loading and Storing Bytes

MIPS provides special instructions to move bytes

lb $t0, 1($s3) #load byte from memory

sb $t0, 6($s3) #store byte to memory

What 8 bits get loaded and stored? load byte places the byte from memory in the rightmost 8

bits of the destination register

- what happens to the other bits in the register?

store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory

op rs rt 16 bit number

331 W02.30 Spring 05

Example of Loading and Storing Bytes Given following code sequence and memory state

(contents are given in hexidecimal), what is the state of the memory after executing the code?

add $s3, $zero, $zerolb $t0, 1($s3)sb $t0, 6($s3)

Memory

0 0 9 0 1 2 A 0Data Word

Address (Decimal)

0

4

8

12

16

20

24

F F F F F F F F

0 1 0 0 0 4 0 2

1 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 What value is left in $t0?

What if the machine was little Endian?

331 W02.31 Spring 05

Review: MIPS Instructions, so far

Category Instr Op Code Example Meaning

Arithmetic

(R format)

add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3

Data

transfer

(I format)

load word 35 lw $s1, 100($s2) $s1 = Memory($s2+100)

store word 43 sw $s1, 100($s2) Memory($s2+100) = $s1

load byte 32 lb $s1, 101($s2) $s1 = Memory($s2+101)

store byte 40 sb $s1, 101($s2) Memory($s2+101) = $s1

331 W02.32 Spring 05

Review: MIPS R3000 ISA Instruction Categories

Load/Store Computational Jump and Branch Floating Point

- coprocessor

Memory Management Special

3 Instruction Formats: all 32 bits wide

R0 - R31

PCHI

LO

OP rs rt rd shamt funct

OP rs rt 16 bit number

OP 26 bit jump target

Registers

R format

I format

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits