32 nm logic patterning options with immersion lithography

32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY

K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock^, Z. Baum, M.

Burkhardt, V. Dai^, D. Dunn, E. Geiss^, H. Haffner#, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery^, Y. Zou^, C. Sarma#,

L. Tsou, W. Yan, H. Zhuang#, D. Gil, D. Medeiros

Contact via: [email protected] IBM Computational Scaling & Advanced Lithography Research, Hopewell Junction, NY

^Advanced Micro Devices, Inc, One AMD Place, P.O. Box 3453, Sunnyvale, CA # Infineon Technologies NA Corp, Hopewell Junction, NY

Keywords: Immersion Lithography, double patterning, 193nm lithography, logic patterning, Double Dipole

Lithography, Printing Assist Features, pattern splitting, pitch splitting

ABSTRACT

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

INTRODUCTION

The introduction of water-based immersion lithography enabled the 45nm node to achieve a full shrink from the 65nm node by enabling robust 2D imaging and enhancing process window. As we migrate from the 45nm node to the 32nm node, lithographers are faced with the challenge of continued scaling without the availability of a comparable improvement in NA. This situation will be exacerbated at 22nm with the lack of a mature EUV or a high index (NA>1.35) lithography solution. Consequently, the industry is aggressively pursuing double pattering solutions for the 32nm node. While flash memory applications are largely driven by one-dimensional considerations, logic applications are primarily driven by two-dimensional concerns. Due to various topology and ground rules for different levels, there is no “one DPT fits all” technology. We are targeting cost-effective DPTs that provide the necessary resolution and process window to support each critical levels. Most results shown here

Optical Microlithography XXI, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 6924, 69243C, (2008) · 0277-786X/08/$18 · doi: 10.1117/12.784107

Proc. of SPIE Vol. 6924 69243C-12008 SPIE Digital Library -- Subscriber Archive Copy

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have been demonstrated on a 1.2 NA scanner. Early 1.35 NA results are also presented, which indicate extendability of these techniques to 22nm processes. In the following sections, we describe each DPT approach in detail, including RET (resolution enhancement technique) and process considerations.

DOUBLE PATTERNING TECHNIQUES

A. Splitting Patterns by Grouping In the first 32nm active layer, the memory is nominally unidirectional while the random logic has multiple orientation and a greater variety of pitches and structures. Consequently, the illumination for the memory can be highly tailored for resolution and process window with one set of conditions that are unique and distinct from the random logic. The SRAM tends to drive pitch and density and consequently lends itself to aggressive polarized dipole illumination to which random logic is not amenable. However, the random logic region can be printed with sufficient process window with less aggressive illuminators such as quadrupole or quasar to allow for bi-directional designs.

At 1.2 NA quasar illumination, the logic circuit with structures having pitch greater than 140nm are printed with sufficient depth of focus and exposure latitude. For structures with pitch in 100-104nm range, dipole illumination is required to achieve fidelity and process window at 1.2NA. Figure 1 shows the decomposition of a full chip into a series of regions with unidirectional tight pitch structure and bidirectional looser pitch structures. Each layout has independently optimized illumination conditions. Each region is then printed separately into the same resist film in a multiple exposure process. The result is a single developed pattern that could not be printed with a single illumination-mask combination. Figure 2 shows top down and x-section views of critical pitch grating structures for each region. The individually optimized illuminations used in this work are listed in Table 1.

Fig. 1. A schematic of the circuit splitting between unidirectional designs, and bidirectional designs

Fig. 2. Cross section and top down SEM pictures for a 104 nm pitch grating structure with and without polarized illumination

Table 1. List of optimized Illumination Conditions for Grouping Split Designs

Condition Bidirectional Unidirectional NA 1.1 1.2 Illuminator Quasar45 Y-Dipole Polarization Unpolarized X-Polarization Mask Type Chrome-on-Glass AttnPSM Assist Type Clear SRAFs None

Logic

Logic

SRAM

<140

Logic<140

Logic

Logic

Logic

SRAM

<140

Logic<140

Logic

Unpolarized Polarized

50nm / 104 nm pitch

Unpolarized Polarized

50nm / 104 nm pitch

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One concern with this DPT scheme is the influence of printing one region near the other due to the scanner penumbra (blading shadow) effect as well as overlay between the two pattern groups from two separate masks. To minimize this impact we have introduced a 1 um buffer area between the two layouts and connection between the groups are made non-critical. The process window and MEEF performance of the critical features are shown in Figures 3 and 4. Sufficient lithographic performance is obtained. Figure 5 demonstrates the accuracy of the OPC model for the SRAM level by overlying the OPC prediction and the top down SEM picture. Excellent match between model and experiment is demonstrated. Figure 6 shows the post-Si etch result and a smooth, straight etch profile is obtained.

(a) (b) Fig. 3. Process window for (a) dense, 104nm pitch and (b) isolated, 600nm pitch Fig. 4. MEEF for 55nm space and 50nm line through pitch showing the benefit with polarized light

Fig.5. Two different SRAM cells of varying size. The green contour is the OPC model prediction. Line-ends are well predicted by the OPC using Y- Dipole illumination and X-polarization

RV50: 50nm Space MEF

0.00

0.50

1.00

1.50

2.00

2.50

3.00

100 120 140 160

Pitch (nm)

MEF

UnpolPol

RV50: 50nm Line MEF

0.000.501.001.502.002.503.003.50

100 120 140 160

Pitch (nm)

MEF

UnpolPol

0 0 .05 0.1 0.15 0.20

5

10

DOF (µm)

Exp

osu

re L

atit

ud

e (

%)

DOF: 0.199 µmExp Lat: 3.868 %Center Dos e: 17.127 E0Center Focus : 0.012 µm

0 0.05 0.1 0.150

5

10

DOF (µm)

Exp

osu

re L

atit

ud

e (

%)

DOF: 0.154 µmExp Lat: 3.868 %Center Dose: 16.584 E0Center Focus: 0.027 µm

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(a) (b)

Fig. 6. Cross sectional image of a post-etch trench with inorganic bilayer barc at (a) pitch =140nm and (b) pitch 110nm.

B. 2D imaging decomposition Improvement of the linewidth tolerance control has been the primary focus of the gate or poly conductor (PC) lithographic process for many previous generations. Figure 7 shows a single exposure PC lithographic process for which both line and line-ends are simultaneously imaged, and the etch-trim process is employed to reduce the printed linewidth, which has the undesirable effect of increasing the printed line-ends spacing. While the overall patterning of line-ends has always been important, it becomes critical at the 32nm (and some 45nm) generation devices. At the 32nm generation, the SRAM density is directly limited by PC line-end tolerance control, including both the PC line-ends extensions over active area, and the PC line-end tip to line-end tip distances. The line-end control of a single exposure process is limited by several factors: a) the fore-shortening of the line-ends and non-vertical resist profile control, limited by the aerial image b) high mask error factor at the line-ends and c) the etch trim pullback of the line-end, which typically exceeds the line trim bias by a factor of two. An alternative PC lithographic patterning process is required to enable tight line-end control, sub 80nm line-end tip to line-end tip distances, and also achieve 32nm (and below) technology compliant linewidth tolerance. The ability to tightly control line-ends by PC double patterning has been previously suggested [1]. Double patterning techniques in which the PC lines are imaged with one reticle and a second reticle is used to achieve a “cut” of the line-end, have the advantage of improving the overall PC tolerance control by de-coupling the pattern formation of PC lines from the PC line-ends. Figure 8 shows an on-wafer example of this double exposure double etch (DE2) double patterning process. The PC lines are printed (Fig. 8a) and then etch trimmed. A “cut” (CUT) shape is printed (Fig.8 b), and then the combined patterns are translated to the substrate (Fig. 8c). By decomposing the line and cut masks, optimized independent illumination and optical proximity correction methods can be employed to image lines and cut shapes separately. Additionally, by decoupling the etch/trim patterning of lines from the etch of the cut shapes with near zero etch bias, approximately straight patterned line-ends and extremely narrow line-end tip to line-end tip distances can be achieved. At the 32nm node, with the use of immersion lithography in the hyper NA regime, the resultant loss of depth of focus (DOF) has a significant impact on the utility of sub-resolution assist features (SRAFs) to meet extremely challenging linewidth tolerances at DOF challenged pitches. Figure 9 shows the reduction in DOF as a function of assist width for a forbidden pitch region at double the contacted pitch. The DOF dramatically increases with the assist width from the non-printed to the printed assist width region. In our previous work, Meiring et al. [5] termed these features Printing Assist Features (PrAFs) which are

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populated alongside nested and semi-isolated lines to make the PC line layout appear as a dense grating (in a manner similar to SRAFs). Since the PrAF features are unwanted, the DE2 scheme can be employed to remove these features with the second CT patterning.

The decomposition of the PC design intent which has been split into the line (PC) and cut (CT) mask, shown in Figure 10, has been previously described by Haffner et al.[3,4]. For the first step of this automated decomposition method, all critical dimension line-ends are extended by an amount consistent with linewidth and process overlay tolerances between gate PC and active area. The line-end extensions have the advantage that OPC induced necking or bulging regions are shifted to regions outside the active area thus reducing possible across-device-length degradation. In the next step, PrAFs are inserted using a rules-based, one-dimensional table, followed by clean-up code, to compensate for pitch differences between adjoining layouts and complex two-dimensional environments. In the third step of decomposition, cut mask shapes are formed on all shapes added in the first two steps of the decomposition.

(a) (b)

Fig.7 (a) Post development SEM of standard single exposure PC level of a typical SRAM. This single exposure post develop image shows the rounding and foreshortening of the line-ends. (b) The PC level post etch shows the enhanced trim/pullback on the line-ends which dramatically increases the line-end tip to line-end tip distance.

(a) (b) (c)

Fig. 8 (a) DE2, post development SEM of PC line mask exposure for an SRAM. (b) Post develop SEM of the CT “cut” mask exposure. All line-ends are patterned with this CT mask. (c) The SRAM result of double exposure double etch of PC + CT. The SRAM results show square line-ends, and narrow line-end tip to line-end tip distances.

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05

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0250

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Fig. 9. The depth of focus is shown at 2x the pitch (in the forbidden pitch region), as a function of the assist width size. The assist width increases non-linearly with the assist width, matching the DOF at the 1x pitch feature.

Fig. 10 The decomposition of the PC design is shown (design intent shown in purple). The line-end extension on the PC line mask and the PrAF at 2x the pitch of the neighboring features are shown indicated in blue. The CT mask shapes over the line-ends and the PrAF are shown in grey.

C. Pitch splitting

Contact imaging has traditionally been a primary challenge for lithographers as k1 factor decreases from node-to-node. For the 32nm and 22nm half-pitch nodes this challenge is greater than ever. With the k1 factor for M1 dropping below 0.3 at 1.2NA, the drive to compress contact pitch has resulted in poor process window and high MEEF for pitches less than 120nm. One means to circumvent this issue and enable traditional design scaling is through an alternative DPT integration process. We have explored the feasibility of ‘pitch split’ contacts. In the pitch-split double-exposure double-etch (PS-DE2) process, the design is decomposed with a minimum pitch governed by process window considerations. Here, we show a columnar decomposition. Once the design is decomposed, OPC is applied to the individual mask levels. The lithography stack and illumination conditions for exposure 1 and exposure 2 are identical. The process details are Quasar30 illumination (σin/σout =0.7/0.9) at 1.2NA with a COG reticle that was anchored at 130nm pitch. The resist was 150nm thick and coated on a trilayer barc system, with 80nm of silicon containing ARC followed by 200 nm or an organic underlayer. Topdown and cross-section images are shown in Figure 11. The MEEF performance through pitch with error-bars indicating though focus is shown in Fig. 12. An example of a post PS-DE2 process into etched into the dielectric stack is shown in Figure 13. Figure 14 is a schematic of how the decomposition algorithm was be applied to a scaled design.

(a) (b)

Fig. 11 (a) Cross-section and topdown image of single exposure, and (b) after etch.

Not printing

Poor printing

Robust printing

Same as 1X pitch

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tLayout Design

2d CA Exposure (CAE2)

1 1 Exposure GA (Green) 4-Final GA (white) overand 2' Exposure GA PG (Blue)

(Purple)

2-Split into 1st Exposure, and 2'GA Exposure based on Pitch

•• •• S •

MEEF Through Pitch for Contact Process

0.0

1.0

2.0

3.0

4.0

5.0

6.0

100 150 200 250 300 350Pitch (nm)

ME

EF

Fig. 12. MEEF Performance with Quasar30 (0.7-0.9) at 1.2NA

Fig.13 SEM micrograph of Contact holes formed by Double etch process to double spatial frequency in Y-direction

(a) (b) (c) (d)

Fig. 14 (a) Design data incoming, (b) Design split into first exposure (green), and second exposure (purple). (c) Combined design, (d) example of overlaid design.

D. Orientation splitting In our previous work [6], dark field double dipole lithography was demonstrated as a technique for imaging 100 nm pitch, back end of the line metallization layers. Illumination simulations, OPC methodology, and resist processes were presented. In this work, we discuss the design decomposition strategy for this technique, and the extendibility of this imaging strategy to 80 nm pitch with 1.35 NA lithography

First Second

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Our DDL design decomposition briefly consists of the following steps. First, all features are decomposed into rectangles, separated by width in 1 nm steps. Second, rectangles with width within a specified range are decomposed into horizontal and vertical structures. The following two categories of rectangles are simply placed at “E1” layer (which becomes the M1 mask after OPC): (1) rectangles that are large enough to be imaged with either illumination scheme and (2) any rectangle that has aspect ratio as one (squares) SRAM cells require individual treatment, and the details are beyond the scope of this paper.

Fig. 15. Examples of DDL decomposition for SRAM and the illuminations used (X-Dipoles and Y-Dipoles)

Fig. 16 shows the Overlap of E1 Mask (red) and E2 Mask (Green) from the decomposition of the random logic design using DDL. E1 mask use X-dipole and E2 mask use Y-Dipole.

In this work, we repeat our previous DDL process studies with a 1.35 NA exposure, examining the performance of 80 nm pitch, equal line/space gratings. The dipole blade angle was 35 degrees, and the partial coherence conditions were 0.97/0.75. The patterning film stack was similar to that reported in our previous work [6], with the exception that the photoresist thickness was targeted to be 115 nm. Figure 17 and Figure 18 show cross section and top down views of the nominal focus/dose conditions for a 40 nm half pitch structure. Figure 17 demonstrates straight resist profiles, albeit with some top rounding and dark erosion (resist loss). Figure 19 shows the process window performance through pitch of a trench (resist

SRAM cell (as designed) SRAM decomposed by algorithm into polygons for X dipole (red) & Y dipole (green) mask

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space) structure. The data is reported as depth of focus at 4% exposure latitude. At dense pitch (< 100 nm), the depth of focus is ~ 0.14 µm. At semidense and isolated pitches, the depth of focus is 0.07-0.09 µm. We have demonstrated the feasibility of 1.35 NA to image one dimensional, 80 nm pitch grating structures. The primary challenges for improving and implementing this process will be dealing with four issues: (a) poor focus budget, (b) OPC challenges relating to DDL design decomposition and low k1 factor (c) photoresist image collapse during wet development, and (d) line edge roughness.

Fig. 17. Cross Section views of 80 nm pitch, equal line/space features created with double dipole lithography.

Fig. 18. Top down view of 80 nm pitch, equal line and space features imaged with double dipole lithography.

0

0.02

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0.1

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0.14

0.16

0 200 400 600 800 1000 1200

pitch (nm)

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Fig. 19. Process window through pitch with dipole process, 1.35 NA, σi=.75, σo=0.97

DPT COMPARISON The type of DPT choice depends on the topology and pitch requirement of a level. It requires examination of each level case by case in order to select the most optimum DPT type with broad

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consideration for other unit process steps, integration challenges, yield and cost. In many cases, the simplest lithography solution is likely the most difficult from an etch or integration perspective. Tool limitations are also important factors to be considered. Table 2 summarizes the pros and cons of the DPT processes mentioned above to serve as a guideline for DPT selection at both 32nm and 22nm technology nodes. Table 2. PROS and CONS of double patterning techniques

Level Splitting Scheme Pros Cons Pattern grouping (DE)

Split by layout topology

1. Simple splitting scheme 2. Relatively low cost process

1. Limited usefulness. Only applicable to RX 2. Increased CD uniformity on mask due to large Cr density variation 3. Alignment complication for subsequent levels

Enhanced 2D imaging (DE2)

Use cut mask to define line end and to remove PrAF (Printing Assist Feature)

1. Allow more aggressive illumination for better gate definition 2. Can use PrAF to improve gate CD control 3. Enable smaller tip-to-tip with better process window

1. Higher process cost 2. More complex design rules with cut mask, especially for variable PC pitch 3. Overlay contributes to line end placement error

Pitch Splitting (DE2)

Split contact or via into 2 masks with increased minimum pitch

1. Larger minimum pitch allows balanced process window through pitch 2. Enable redundant contact hole with much smaller space than available with single exposure

1. Only applicable with dark field mask 2. Design rules can be complicated depending on splitting scheme 3. Increased total overlay error to M1

Orientation grouping (DDL)

Split pattern by orientation into grating like geometry orthogonal to each other

1. Enable tighter pitch for both x/y orientation 2. Relatively low cost process

1. Increased requirement on modeling to capture interactions between two exposures 2. More complex OPC 3. Print quality sensitive on both decomposition method and OPC 4. Overlay will cause deformation of pattern where 2 exposures interact

CONCLUSION

A series of level-specific DPT methods have been detailed. Each method is based on the topology and pitch requirement of a level. Specifically, multiple patterning has been demonstrated with four distinct decompositions: 1) Pattern Groupings 2) Pitch Splitting 3) Enhanced 2D Imaging 4) Orientational Grouping Each level was analyzed and several were evaluated for lithographic, integration, and cost implications. Each of the above concepts can be extended from 32nm node early development to 22nm and beyond.

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ACKNOWLEDGMENT We would like to thank many colleagues in the IBM alliance who have contributed to this work through discussion, simulation, tool support and experimentation. We also thank the management team for their support of this work. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities and has been supported by the independent Bulk CMOS and SOI technology development projects at the IBM Microelectornics, Div. Semiconductor Research & Development Center, Hopewell Junction, NY 12533

REFERENCES [1] K. Mistry et al., "A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", IEDM Tech Dig. , pp 247-250, (2007). Y. Borodovsky, "Marching to the Beat of Moorse's Law", SPIE Microlithogaphy, 2006. [2] J. Meiring, H. Haffner, C. Fonseca, S. Halle, and S. Mansfield: “ACLV Driven Double-Patterning Decomposition With Extensively Added Printing Assist Features (PrAFs)”, Proc. SPIE Vol. 6520 (SPIE, Bellingham, WA, 65201U (2007). [3] H. Haffner, J. Meiring, Z. Baum, S. Halle: ”Paving the way to a full chip gate level double patterning application”, Proc. SPIE Vol. 6730 (SPIE, Bellingham, WA, 67302C ( 2007). [4] H. Haffner, J. Meiring, Z. Baum, S. Halle, and S. Mansfield, “Solving the gate level ACLV challenge with double patterning and printing assist features”, Microlithography World, in press. [5] J. E. Meiring et al, “ACLV driven double-patterning decomposition with extensively added printing assist features (PrAFs)” Proceedings of the SPIE, Volume 6520, pp. 65201U (2007). [6] M. Burkhardt, et al, “Dark field double dipole lithography (DDL) for back-end-of-line processes” Proceedings of SPIE, 6520, pp. 65200K (2007) [7] Matrix OPC is a trademark of Mentor Graphics Inc. [8] B. Arnold, M. Dusa, J. Finders, et al ,” Metrology challenges of double exposure and double patterning”, Proceedings of SPIE, 6518, pp. 651902 (2007)

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