3 dimensional integrated circuits

7/26/2019 3 dimensional integrated circuits

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3-Dimensional Integrated circ

PRESENTED BY:S.Deva


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CONTENTS

WHAT IS 3-D IC?

INCENTIVES

LIMITED PERFORMANCE OF 3-D IC

3-D ARCHITECTURE

MANUFACTURING TECHNOLOGY OF 3D ICs

ADVANTAGES OF 3-D ARCHITECTURE

DISADVANTAGES OF 3-D ARCHITECTURE

PERFORMANCE CHARACTERISTICS

PRESENT SCENARIO IN 3-D IC INDUSTRY

CONCLUSION


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3D Integrated circuit is a chip which accommodates two or more layeof active electronic components

They are integrated both horizontally and vertically onto a single

circuit.

What is a 3D

IC??


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To reduce wastage of space on the substrate.

To improve interconnections among different wafers.

To reduce the length of interconnections which in turn reduces heat

dissipation and also RC delays.

Can be used to accommodate both homogenous and heterogeneous chips.

Thus there is a great urge to switch over from 2D ICs to 3D ICs

INCENTIVES:


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LIMITED PERORM!NCE O 3D IC"s

As we try to increase the performance and ecchip, the complexity of chip design increases and thismore and more transistors. So the nal size of the cidelays increases.

he losses increases with large interconnection !eccapacitance and resistances are generated in !etweenand copper.


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3D IC !RC#ITECT$RE

"D #$ is a concept that can signicantly %&

#mprove interconnect performance, #ncrease transistor pac'ing density, (educe chip area (educe )ower dissipation

#n "D design structure the entire chip *Si+ isdivided !y num!er of layers of oxide and metal,to form transistors.


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M!N$!CT$RIN% TEC#NOLO%& O 3D ICs

here are four ways to !uilt "D #$s %&

. -onolithic

. /afer on wafer

". Die on wafer

0. Die on die


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'( Monolit)ic

1lectronic components and their connections 2wiring3 are!uilt in layers on a single semiconductor wafer, which is thendiced into "D #$s.

here is only one su!strate, hence no need for aligning,thinning, !onding, or through&silicon vias.


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*( +a,er on a,er

1lectronic components are !uilt on two or more semiconducwhich are then aligned, !onded, and diced into "D #$s.


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3( Die on a,er

1lectronic components are !uilt on two semiconductor wafers. 4nediced aligned and !onded onto die sites of the second wafer.


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.(Die on die

1lectronic components are !uilt on multiple dice, which are theand !onded.

4ne advantage of die&on&die is that each component die can !erst, so that one !ad die does not ruin an entire stac'


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PERORM!NCE C#!R!CTERISTICS

. #-#56

. 151(67

/ith shorter interconnects in "D #$s, !oth sw

energy and cycle time are expected to !e red


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Timing performance: #n current technologies, timing is interconnect driven.

(educing interconnect length in designs can dramatically reduce ($ del

chip performance he graph !elow shows the results of a reduction in wire length due to "


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Energ performance:

/ire length reduction has an impact on the cycle time and the energy diss

1nergy dissipation decreases with the num!er of layers used in the desig


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PRESENT SCEN!RIO IN 3D IC IND$STR&

-any companies li'e -# 28SA3, #9- are doing research on "D #$ and they are going to introduce cheaper chips for certain applicmemory used in digital cameras, cell phones, handheld gaming dev

he original cost will !e : times lesser than the current ones.


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!DV!NT!%ES:"D integration can reduce the wiring, there!y reducing the capacitances, powe

dissipation and chip area improves performance.

Digital and analog circuits can !e formed with !etter noise performance.

$ost is more e;ective than D integration.

DIS!D"!NT!#ES :


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Applications%

physical limitations for classic D electronicsaddressing all important issues, such as waferprocessing

applications of mixed signal designs.


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CONCL$SION

"D #$s will !e the rst of a new generadense, inexpensive chips having less delinterconnection losses that will replacconventional storage and recording media


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!n

$%eries


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3 dimensional integrated circuits

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