3. Digital Implementation of Mo/Demodulators. General Structure of a Mo/Demodulator MOD amp DSB SSB amp DEM.

3. Digital Implementation of Mo/Demodulators

General Structure of a Mo/Demodulator

MOD)(td

)(tx

amp

CF

)(FD

F

)(FX

FCF

)(FX

FCF

DSB

SSB

ampDEM)(ˆ td

SSB Re{.})(td )(tx

)2( tFj Ce

)(FD

F

F

)(td

)(FX

FCF

)(FD

MOD

Single Side Band (SSB) Modulator

SSB

)(td )(tx

tFC2cos

)(tdR

)(td I

tFC2sin

where )(Im)(

)(Re)(

tdtd

tdtd

I

R

Implementation using Real Components

)(td )(tx

tFC2cos

)(FD

F

)(FX

FCF

DEM

LPF

Single Side Band (SSB) Demodulator

Digital Up Converter

DUC

M

][nd ][ns

ZOH)(txAnalog

MOD

)(ts

DISCRETE TIME CONTINUOUS TIME

IFF~ IFC FF ~

sF sMF

)(td

Single Side Band (SSB) Modulator in Discrete Time

sF

Modulator Implemented in two stages:

Demodulator Implemented in two stages:

Digital Down Converter

DDC

M

][nd][ns)(ty

Analog DEM

)(ts

sMF

DISCRETE TIMECONTINUOUS TIME

IFF~ IFC FF ~

sFZOH

)(td

Single Side Band (SSB) Demodulator in Discrete Time

DUC

M

][nd ][ns

IFF~

sF sMF

( )D f

f21

( )S f

fIFf 2

121

DDC

M

][nd ][ns

sMFsF

Digital Down (DDC) and UP (DUC) Converters

F2

sMFF2

sF

• kHz for voice

• MHz for data

RFBaseband• MHz for voice

• GHz for data

000,1~MOrder of magnitude of resampling:

if M is large, very small transition region high complexity filter

][nd ][nsM LPF

2sF

sF

FD

2sMF

2sMF

LPF

sF

B

B

BFs

Mb

MFBF

s

sf 212

Problem with Large Upsampling Factor

MFs

2

sF

FS

2sF

2sMF

LPF

MFs

B

B

BMFs

bf MFBMF

s

s 212/

][nd][nsMLPF

Problem with Large Downsampling Factor

if M is large, very small transition region high complexity filter

In order to make it more efficient we upsample in L stages

1M )(1 zHLM

][][0 ndnx ][ 22 mx ][][ mymx LL

sFF 0 1F LF2M )(2 zH

][ 11 mx

)(zH L

2FLs FMF

LMMMM ...21

Solution: Upsample in Stages

][ ii mx

11 iFF

iX iF

FiX

1iF)(FH i

iF

2iF

iFB

B

BFi 1

iM ( )iH z

][ 11 ii mx

i

i

FBF

if21

i-th Stage of Upsampling

96 )(zH][nd

kHzF 120

)(kHzF

0F

FD

4

sec/107.755

6562886

2250

2881

152,1812

opsFN

N

f

s

MHzF 152.13

][my

This is not only a filter with high complexity, but also it is computed at a high sampling rate.

Example: Upsample in One Stage

2 )(1 zH 12][nd

][ 22 mx ][][ 33 mymx

kHzF 120 kHzF 241

4 )(2 zH

][ 11 mx

)(3 zH

kHzF 962 MHzF 152.13

)(kHzF

0F

FD

4

311

2250

1

61

24812

1

10336

146

sFN

N

f

622

2250

2

61

96824

2

1034.1

146

sFN

N

f

633

11144

2250

3

14411

1152896

3

105.34

30

sFN

N

f

Total Number of operations/sec= 610176.36

a 95% savings!!!!

Same Example in Three Stages

0( )H z

][][0 ndnx ][ 22 mx ][][ mymx LL

sFF 01F

][ 11 mx

sL

FF

M

1M 1( )H z

2F2M 1( )LH z

1LF LM

0F

LMMMM ...21

Downsample in Stages

][ ii mx

11 iF

FiX

1( )iH F

iF

1

2iF

B

B

iF B

1( )iH z][ 11 ii mx

1

2i

i

F Bi Ff

iM

1

2iF 1

2iF

i

Fi FX

BiFiF

1iF

noise

keep aliased noise away from signal

i-th Stage of Downsampling

200)(zH][nd

1 12F kHz

)(kHzF

0F

FD

4

12 8 12400 600

5022

90

600 1,364

3.273 10 / sec

f

N

N F ops

0 2.4F MHz

][my

Example: Downsample in One Stage

40( )H z][nd

3 12F kHz

)(kHzF

0F

FD

4

0 2.4F MHz

][my

51( )H z 102( )H z

1 600F kHz 2 120F kHz

600 8 10 2400 4.05

500 22

60 0

4.05 10

24 10

f

N

N F

120 8 11 600 5.36

501 22

61 1

5.36 13

7.8 10

f

N

N F

12 8 12 120 30

502 22

62 2

30 68

8.16 10

f

N

N F

Total Number of operations/sec = 639.96 10

… a savings of almost 99% !!!

Same Example in Three Stages

1M )(1 zHLM

][nd ][my

sFF 0 LF1LM )(1 zH L )(zH L

Ls FMF

0( )H z

][nd

sFF 0 1F sL

FF

M

1M 1( )H z2M 1( )LH z LM

0F

][my

highest rates

• the highest sampling rates are close to carrier frequencies, thus very high;

• properly choose intermediate frequencies to have simple filters at highest rates

1LF

Stages at the Highest Rates

11 LF

FLX

1LF

wide region

LM][my

LF)(zH L

Ls FMF

BFL 1B

][1 nxL

Last Stage in UpSampling

1LF

LL FFB 12

0( )H z

][nd

sFF 0

1M0F

][1 mx

11 F

FX

1F

wide region BF 1B

First Stage in DownSampling

BFF 210

1F

Very simple Low Pass Filter: the Comb Integrator Cascade (CIC)

][][]1[][ Nnxnxnyny

these two are the same!

1

0

][][N

nxny

Notice: no multiplications!

11

1 z

Nz 1][ny

“Comb” “Integrator”

)1(1 ...1 Nzz][nx

][nx

same!!!

1

0

][][N

nxny

Frequency Response of the Comb Filter

fNje

eeeefNj

fNjfNjfNjfNj

sin2

1 2

…like a comb!

fjez

Nz 21

fN1

N2

N3

N2

N1

fNje 21

Impulse Response of the CIC

11

1

z

z N][n ][0 mc

N

1

00 ][][

N

mmc

][m][n][0 mc

0 1N

interpolating sequence

The CIC in the Time Domain

11

1

z

z N][nx ][my

N][nx ][ms

][my

][][][ Nmxms

][][][ 0 Nmcxmy

like a discrete time ZOH!

Two Important Identities: The “Noble” Identities

N][nx

][][ kNmNxmy kNz

][ kNnx

N][nx ])[(][ Nkmxmy

kz

][mNx Same !!!

As a consequence we have one of two “Noble Identities”:

N][nx

NzH

][my

N][nx

zH][my

Same!!!

N][nx

kz

][ knx

As a consequence we have the other of the two “Noble Identities”:

N][nx

NzH

][my

N][nx

zH][my

N][nx ][1 my

kNz

][ kNmy

n

nNkNmnxkNmy ][][][1

n

nNmknxmy ][][][2

Same !!!

Other “Noble” Identity

N][my][nx

11 z 11

1 z

1z N

1z

][nx ][my

Use Noble Identity:

Very simple implementation (no multiplications):

11

1 z

][nx ][myN Nz 1

Efficient Implementation of Upsampling CIC

N][my][nx

11 z11

1 z

1zN

1z

][nx][my

Use Noble Identity:

Very simple implementation (no multiplications):

11

1 z

][nx ][myNNz 1

Efficient Implementation of Downsampling CIC

Frequency Response of the CIC

Not a very good Low Pass Filter. We want a better attenuation in the stopband!

0 0.1 0.2 0.3 0.4 0.5-25

-20

-15

-10

-5

0

5

f=F/Fs

dB

PASSfSTOPf

only 13 dB attenuation

Put M Stages together

M

MfNjfj

fNj

M f

fNe

e

efC

sin

sin

1

1)( )1(

2

2

1

1

1

1

MNz

z

][nx ][myN

1

1

1

MNz

z

][nx ][myN

Frequency Response:

0 0.1 0.2 0.3 0.4 0.5-80

-70

-60

-50

-40

-30

-20

-10

0

f=F/Fs

dB

Resampling Factor N=10

2M

3M

4M

5M

With M=4 or 5 we already get a very good attenuation.

Improved Frequency Response of CIC Filter

0 0.1 0.2 0.3 0.4 0.5

-80

-70

-60

-50

-40

-30

-20

-10

0

f=F/Fs

dB

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

-8-6-4-20

f=F/Fs

dB

Example: M=4 Stages

Use Noble Identity:

N][my][nx

Mz 11 M

z

11

1

1z 1z

N1z 1z

][nx ][my

1

1

1

M

z

][nx ][myN 1

MNz

Implementation of M Stage CIC Filter: Upsampling

N][ny][nx ][nxNMN

z

z

11

1

Use Noble Identity:

N][ny][nx

Mz 11 M

z

11

1

1z 1z

N

][nx ][ny

1z 1z

Implementation of M Stage CIC Filter: Downsampling

N][ny][nx

Mz 11 M

z

11

1

1z 1z

N

][nx ][ny

1z 1z

Now we have to be careful: the output of the integrator will easily go to infinity

Problem: DownSampling CIC is Unstable

CIC Implementation.

N][ny][nx [ ]Mx n

1

0

MNk

k

z

]1[...]1[][][ 111 Nnxnxnxnx pppp

This implies: |][|max|][|max 1 nxNnx pp

N][ny

][nx[ ]Mx n1

0

Nk

k

z

1

0

Nk

k

z

1

0

Nk

k

z

1[ ]x n 2[ ]x n 1[ ]px n [ ]px n

At the p stage:

and |][|max|][|max nxNnx MM

If we use Q bits for the integrators then we need to guarantee

1max | [ ] | 2QMx n

1 1max | [ ] | max | [ ] | 2 2M M L QMx n N x n N

Let the input data use L bits:

1max | [ ] | 2Lx n

][nx

Then:

NMLQ 2log

input bitsnumber of stages

decimation factor

Application: Software Defined Radio

Definitions:

• Software Defined Radio: modulation, bandwidth allocation … all in software

• Field Programmable Gate Array (FPGA): reprogrammable logic device which is able to perform a number of operations in parallel. They can process data at a rate of several 100s of MHz

• DSP Chip: optimized for DSP operations by some hardwired ops (such as multiplies).

An HF SSB Software Defined Radio

by Dick Benson, The Mathworks,

Rec/Tr

DAC

64MHz

RF IQ

Rec.

RFIQ

Trans.

FPGA

AUDIO

AUDIO

DSP Chip

Rec.

Trans.

15.6kHz 7.8kHzsF

Transmitter:

( )x t

7.8125 kHz

2 FIR

DSP Chip

Q

AUDIO

I

2 FIR

I

Q

8 FIR 8 FIR 64 CIC

8 FIR 8 FIR 64 CIC

64SF MHz

RF

FPGA

Xilinx Library Modules

SSB

nfC2cos

nfC2sin

RF CIC

CIC

64

64

FIR

FIR

8

8

FIR

FIR

8

8

I

Q

Receiver:

Xilinx Library Modules

FPGA

Q

I FIR

FIR

2

2

DSP Chip

AUDIO

nfC2sin

nfC2cos