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• 1. 3D IC technologyPouya DormianiChristopher Lucas

2. What is a 3D IC?Could be Heterogeneous Stacked 2D (Conventional) ICs 3. Motivation Interconnect structures increasingly consume more of the powerand delay budgets in modern design Plausible solution: increase the number of nearest neighbors seenby each transistor by using 3D IC design Smaller wire cross-sections, smaller wire pitch and longer lines totraverse larger chips increase RC delay. RC delay is increasingly becoming the dominant factor At 250 nm Cu was introduced alleviate the adverse effect ofincreasing interconnect delay.130 nm technology node, substantial interconnect delays will result. 4. 3D Fabrication Technologies Many options available for realization of 3D circuits Choice of Fabrication depends on requirements of Circuit SystemBeamProcessed WaferSilicon EpitaxialSolid PhaseRecrystallization BondingGrowth CrystallizationDeposit polysilliconBond two fully Epitaxially grow a Low Tempand fabricate TFTsprocessed wafers single cystal Si alternative to SE.-not practial for 3D circuits together.due to high temp of meltingpolysillicon-Similar Electrical Properties -High temperatures cause -Offers Flexibilty of creatingon all devices siginificant cause significant multiple layers-Suffers from Low carrier-Independent of temp. sincedegradation in quality of-Compatible with currentmobilityall chips are fabricated thendevices on lower layersprocessing environments-However high perfomancebondedTFTs-Process not yet -Useful for Stacked SRAM-Good for applications where manufacturable and EEPROM cellshave been fabricated usingchips do independentlow temp processing which processingcan be used to implement 3D-However Lack ofcircuitsPrecision(alignemnt) restrictsinterchip communication toglobal metal lines. 5. Performance Characteristics Timing Energy With shorter interconnects in 3D ICs, both switchingenergy and cycle time are expected to be reduced 6. Timing In current technologies, timing isinterconnect driven. Reducing interconnect length indesigns can dramatically reduceRC delays and increase chipperformance The graph below shows theresults of a reduction in wirelength due to 3D routing Discussed more in detail later inthe slides 7. Energy performance Wire length reduction has an impact onthe cycle time and the energy dissipation Energy dissipation decreases with thenumber of layers used in the design Following graphs are based on the 3D tooldescribed later in the presentation 8. Energy performance graphs 9. Design tools for 3D-IC design Demand for EDA tools Asthe technology matures, designers willwant to exploit this design area Current tool-chains Mostlyacademic We will discuss a tool from MIT 10. 3D Standard Cell tool Design 3D Cell Placement Placement by min-cut partitioning 3D Global Routing Inter-wafer vias Circuit layout management MAGIC 11. 3D Standard Cell Placement Natural to think of a 3Dintegrated circuit asbeing partitioned intodevice layers or planes Min cut part-itioningalong the 3rd dimensionis same as minimizingvias 12. Total wire length vs. Vias Can trade off increased total wire length for fewer inter-planevias by varying the point at which the design is partitionedinto planes Plane assignment performed prior to detailed placement Yields smaller number of vias, but greater overall wire length 13. Total wire length vs. Vias (Cont) Planeassignment not made until detailed placement stage Yields smaller total wire length but greater number of vias 14. Intro to Global Routing Overview Global Routing involves generating a loose route for each net. Assigns a list of routing regions to a net withoutactually specifying the geometrical layout of thewires. Followedby detailed routing Finds the actual geometrical shape of the netwithin the assigned routing regions. Usuallyeither sequential or hierarchical algorithms 15. Illustration of routing areas yyx x z z Detailed routing of net when routing areas are known 16. Hierarchical Global Routing Tool uses a hierarchical global routingalgorithm Based on Integer programming and Steinertrees Integer programming approach still too slowfor size of problem and complexity (NP-hard) Hierarchical routing methods break down theinteger program into pieces small enough tobe solved exactly 17. 2D Global Routing A 2D Hierarchical global router works by recursivelybisecting the routing substrate. Wires within a Region are fully contained or terminate at apin on the region boundry. At each partitioning step the pins on the side of therouting region is allocated to one of the two subregions. Wires Connect cells on both sides of the partition line. These are cut by the partition and for each a pin is insertedinto the side of the partition Once complete, the results can be fed to a detailedrouter or switch box router (A switchbox is a rectangulararea bounded on all sides by blocks) 18. Illustration of Bisection 19. Extending to 3D Routing in 3D consists of routing a set of alignedcongruent routing regions on adjacent wafers. Wires can enter from any of the sides of the routing region inaddition to its top and bottom 3D router must consider routing on each of the layers inaddition to the placement of the inter-waver vias Basis idea is: You connect a inter-waver via to the portyou are trying to connect to, and route the wire to that viaon the 2D plane. All we need now is enough area in the 2D routing space to routeto the appropriate via 20. 3D Routing Results Percentage Of 2D Total wire Length Minimizing for Wire Length: 2 Layers ~ 28% 5 Layers ~ 51 % Minimizing for via count: 2 Layers ~ 7% 5 Layers ~ 17% 21. 3D-MAGIC MAGIC is an open source layout editor developed at UCBerkeley 3D-MAGIC is an extension to MAGIC by providingsupport for Multi-layer IC design Whats different New Command :bond Bonds existing 2D ICs and places inter-layer Vias in the designfile Once Two layers are bonded they are treated as one entity 22. Concerns in 3D circuit Thermal Issues in 3D-circuits EMI Reliability Issues 23. Thermal Issues in 3D Circuits Thermal Effects dramatically impact interconnect and device reliability in 2Dcircuits Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharpincrease in power density Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness ofdifferent 3D technology and design options. 24. Heat Flow in 2DHeat generated arises due to switchingIn 2D circuits we have only one layer of Si toconsider. 25. Heat Flow in 3DWith multi-layer circuits , the upperlayers will also generate a significantfraction of the heat.Heat increases linearly with level increase 26. Heat Dissipation All active layers will be insulated from each other by layers of dielectrics With much lower thermal conductivity than Si Therefore heat dissipation in 3D circuits can accelerate many failuremechanisms. 27. Heat Dissipation inWafer Bonding versus Epitaxial Growth Wafer Bonding(b) Epitaxial Growth(a) 2X Area for heat dissipation 28. Heat Dissipation inWafer Bonding versus Epitaxial Growth Design 1 Design 2 Equal Chip Area Equal metal wire pitch 29. High epitaxial temperatureTemperatures actually higher for Epitaxial second layersSince the temperature of the second active layer T2 willBe higher than T1 since T1 is closer to the substrateand T2 is stuck between insulators 30. EMI in 3D ICs Interconnect Coupling Capacitance and cross talk Coupling between the top layer metal of the first active layer and the device on the second active layer devices is expected 31. EMI Interconnect Inductance Effects Shorter wire lengths help reduce theinductance Presence of second substrate close to globalwires might help lower inductance byproviding shorter return paths 32. Reliability Issues? Electro thermal and Thermo-mechanical effectsbetween various active layers can influence electro-migration and chip performance Die yield issues may arise due to mismatchesbetween die yields of different layers, which affectnet yield of 3D chips. 33. Implications on Circuit Designand Architecture Buffer Insertion Layout of Critical Paths Microprocessor Design Mixed Signal ICs Physical design and Synthesis 34. Buffer Insertion Buffer Insertion Use of buffers in 3D circuits to break up long interconnects At top layers inverter sizes 450 times min inverter size for the relevanttechnology These top layer buffers require large routing area and can reach up to10,000 for high performance designs in 100nm technology With 3D technology repeaters can be placed on the second layer andreduce area for the first layer. 35. Layout of Critical Paths andMicroprocessor Design Once again interconnect delay dominates in 2Ddesign. Logic blocks on the critical path need tocommunicate with each other but due toplacement and desig constraints are placed faraway from each other. With a second layer of Si these devices can beplaced on different layes of Si and thus closer toeach other using(VILICs) In Microprocessor design most critical pathsinvolve on chip caches on the critical path. Computational modules which access the cacheare distributed all over the chip while the cacheis in the corner. Cache can be placed on a second layer andconnected to these modules using (VILICs) 36. Mixed Signal ICs and PhysicalDesign Digital signals on chip can couple and interfere withRF signals With multiple layers RF portions of the system can beseparated from their digital counterparts. Physical Design needs to consider the multiple layersof Silicon available. Placement and routing algorithms need to bemodified 37. Conclusion 3D IC design is a relief to interconnectdriven IC design. Still many manufacturing andtechnological difficulties Needs strong EDA applications forautomated design