3 d ic

1. 3D IC STC/ITRI 120090612 CAD

2. Outline More than Moore Process of 3D IC Advantages of 3D IC 2

3. Moore (1965)Relative Manufacturing cost per Computer Number of Computer per Integrated Circuit 3 2008/04 in Golden Moores Office

4. Moores 1st and 2nd Law Moores First Law Chip Density will double ever 18months. This means that memory sizes, processor power, etc. all follow the same curve. Moores Second Law The cost of building chip fabrication plants will continue to increase (and the return on investment to decrease) until it becomes fiscally untenable to build new plants. i.e. while it may be technologically possible to continue to double the density of chips every 18 months, the cost of achieving this goal will eventually surpass the profit. 4www.ucd.ie/mecheng/ams/S%20Daniels%20Recent%20advances%202.pdf

5. Moores Law on Microprocessor Duo core Itanium 1.7 B Trs. Pentium 4864004 5

6. 2003-2008IC (1/2) 2003 2004 2005 2006 2007 2008 250 260 268 267 272 275 () 1,902 2,608 2,850 3,234 3,997 3,749 28.7% 37.1% 9.3% 13.5% 23.6% -6.2% 45% 37% 34% 34% 33% 39% / 3.5% 2.5% 3.0% 3.2% 3.3% 3.1% R&D/ 12.8% 9.1% 10.0% 10.8% 11.2% 11.5% 5,000 40.00% 4,000 30.00% 3,000 20.00% 2,000 1,000 10.00% 0 0.00% 2002 2004 2006 2008 2010 2002 2004 2006 2008 2010 -10.00% 6

7. 2003-2008IC (2/2) 2003 2004 2005 2006 2007 2008 37.0% 34.6% 36.0% 37.0% 37.3% 36.9% 21.4% 19.0% 20.1% 20.6% 20.8% 20.7% 20.4% 15.0% 16.3% 16.8% 17.1% 16.9% 1,514 1,242 1,124 916 1,132 1,116 (/)1999~2007 7 ()

8. More than Moore 3D ICIC ?? More Money 3D ?? 820090612 CAD

9. Skyscrapers Location : Dubai Location : Taiwan Location : Malaysia Height : 705 Meters Height : 508 M Height : 452 Meters Floors : 160 Floors : 101 Floors : 88 9 To Be Completed : 2008 Built : 2004 Built : 1998

10. More Than Moore: 3D IC 3-D Integrated Planar (2-D) Integrated Circuits Solid State Discrete Circuits Transistors Heterogeneous Integration 19471950s 1960s 1958 1970s 1980s 1990s 2000s 2000s 2010s 2020s 1950s 2000s 2010s 2020s >>1B transistors Source: Fairchild, Intel 10 & CS Tan(NTU-SG)

11. 2D vs. 3D 20 (TSV) 11 http://www.jonathassociates.com/AJA/droppedImage.png

12. 2D vs. 3D 12

13. 3D Integration 13

14. Why Not SOC ? (Cost) (Material) (Lithography) 3D (Transistor Architecture) (Variability) (Thermal Dissipation) 14

15. (Cost) (1/2) SOC 2003 ISSCC Intel Architecture Jay Heeb`` 15

16. (Cost) (2/2) 16

17. (Material) (1/2) 17

18. (Material) (2/2) 1990~2000 2000~2005 2005~2010 Glass (oxide) Glass (oxide) Glass (oxide) Tungsten Tungsten Tungsten Copper Copper Shallow Trench Shallow Trench Polysilicon Polysilicon Low K Cap Ultra Low k Metal Gates Gate Insulators High k Dielectrics Ir & Pt Electrodes Magnetics 18

19. Delay in Low-k Implementation 19

20. (Lithography) (1/2) 45nm Lithography Lithography Layout pattern Layout pattern 65nm dependence dependence90nm Lithography Lithography Immersion litho, Immersion litho, Back-end integration Back-end integration OPC/PSM integr. w/ OPC/PSM integr. w/ OPC/PSM integration OPC/PSM integration Low-k Low-k photo-window photo-window w/ photo window w/ photo window CMP CMP Front-end/Transistor Front-end/Transistor Front end/Transistor Front end/Transistor Product ramp issues Product ramp issues Layout dependent Layout dependent New gate/oxide New gate/oxide Yield vs. Yield vs. performance performance architectures architectures performance performance Parametric variation Parametric variation Reliability Reliability 20

21. (Lithography) (2/2) Layout 0.25 0.18 0.13 90-nm 65-nm 21

22. 3D (TransistorArchitecture) 22

23. (Variability) 23

24. (Thermal Dissipation) (1/2) IBM 24

25. (Thermal Dissipation) (2/2) Intel 25

26. Via First Process 26

27. Via Last Process Laser drilling Wet Etching Plasma (DRIE) Etching 27

28. Aspect Ratio 28

29. FSI (Front Side Illumination) vs. BSI 29

30. SoC vs. SiP vs. 3D IC SOC SIP 3DICForm Factor Density Performance (speed, X frequency, power)Signal process packing X densityManufacturing cost in high X quantitiesHeterogeneous integration X Manufacturing cost in Xlow/medium quantitiesManufacturing ready (2007) X : Best, : Medium, X: Worst 30

31. 3D-IC (1/2) (Improve Interconnect Density) (Reduce Form Factor) (Reduce Parasitic Capacitance/Inductance) (Increase Speed) (Reduce Power Consumption) (Reduce Cost) (Provide Heterogeneous Integration) (Improve Reliability) 31

32. 3D-IC (2/2) ESD (Reduce ESD Requirement) (Improve Heat Dissipation) (Increase Yield) (Improve Data Security) // (Scalable/Reconfigurable/Replaceable) (Simple Interposer) 32

33. Technical Barriers -- Design EDA Tools Front-end Back-end Multi-Process Application 33

34. Technical Barriers -- Thermal Thermally aware P&R Cooling Thermal vias Micro-fluid 34

35. Technical Barriers -- Test KGD (Known Good Die) Yield 35

36. Major Applications of 3D IC (CMOS Image Sensors) (Memories) SRAM/DRAM NAND (Processor) DSP (Sensor and DSP) (FPGA) (MEMS) 36

37. 3D IC Application Forecast 37

38. 3D-IC iSuppli 2010 33 iSuppli 2014 173 Prismark 2006 340 Prismark 2010 143D IC Yole 2010 10 Flash Memory TSV Yole 2015 (Test) (EDA)(Thermal Management) 2011 Yole 2015 25% 3D-TSV Yole 2015 6% IC () 3D-TSV ITIS 3D IC SSD 2010~2012 EMC-3D 20073D-LSI41020082412009 16220060% NXP 2012 3D IC Cost, performance, Form factor. 2008 3D-IC t 45000 Wafer, 2014 4 Aviza 2007: 5~10 50% TSV Advanced 2008 TSV 2009 Flash Memory2010 3D SRAM Package DRAM 38

39. 3D IC Elpida DRAM (Prototype) Freescale RF (Prototype), MEMS (R&D) Hynix Flash DRAM (Prototype) IBM RF (Prototype), CIS (R&D) Intel Logic (R&D) Micron Flash, DRAM (Prototype), CIS (Production) IDM NEC DRAM (Prototype) NXP RF (Production), MEMS (R&D) Renesas Logic (R&D) Samsung CIS (Prototype), Flash, DRAM (Prototype) Sharp CIS (Prototype), Logic (R&D) Sony Logic (R&D) STM RF (Production), CIS (Production)MEMS (R&D) Chartered DRAM (Production), Logic (Prototype) Foundry TSMC CIS, MEMS (R&D) Amkor Flash, DRAM (Prototype) Packaging ASE RF (Prototype), DRAM, Flash (Prototype) Xintec CIS (Production) 39

40. 3D IC Example: Samsung Samsung 16Gb NAND stack with TSVhttp://www.techpowerup.com/10837/Samsung_Develops_3D_Memory_Package.html 40

41. 3D IC Example: IMEC 41

42. Intel 80 cores 3D IC structure 42

43. e-Cube /MuChip /RaLink /MediaTek /Holtek, /ELAN /PixArt /Richtek () 43

44. 3D IC EDA Tool: R3 Logic 44

45. 3D EDA Tool: Cadence 45

46. 2 D or 3D ? Intel 45nm Systems-in-a-Cube (Source: IMEC)http://www.solid-state.com/articles/article_display.html?id=224942 46

47. Effort Needed for Manufacutrable 3D 47

48. Technical Challenges for 3D IC 48

49. Business Challenge for 3D IC 49

50. More Closed Link on 3D IC ?? CMP 50

51. ? 51

52. 3D altitu D e D ocument rea D ing 52

53. Thanks for Your Attention 53

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