1 Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation Dong Hyuk Woo Nak Hee Seong Hsien-Hsin S. Lee The 54th IEEE International Midwest Symposium on Circuits and Systems Electrical and Computer Engineering Georgia Tech Intel Labs
19
Embed
3-D Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation Dong Hyuk Woo Nak Hee Seong Hsien-Hsin S. Lee The 54th.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design EvaluationDong Hyuk
Woo
Nak Hee SeongHsien-Hsin S. Lee
The 54th IEEE International Midwest Symposium on Circuits and Systems