3. CURRENT MIRRORS

3. CURRENT MIRRORS
50 Prepared by Binoy K P, Asst. Prof., Dept of AE&I, GECK For More Visit www.ktunotes.in
A MOS current source biased by means of a resistive divider
suffers from dependence on VDD and temperature.
Figure 3.1
Since both the mobility and the threshold voltage vary with
temperature, I1 is not constant even if VGS is.
Typical biasing schemes fail to establish a constant drain current if
the supply voltage or the ambient temperature are subject to change.
An elegant method of creating supply- and temperature-
independent voltages and currents exists and appears in almost all
microelectronic systems called the “bandgap reference circuit”
and employing several tens of devices.
An integrated circuit may incorporate hundreds of current sources.
The complexity of the bandgap prohibits its use for each current
source in a large integrated circuit.
A bandgap reference can provide a “golden current” while requiring
a few tens of devices.
We must seek a method of “copying” the golden current without
duplicating the entire bandgap circuitry.
Current Mirrors serve this purpose.
The golden current generated by a bandgap reference is
“read” by the current mirror and a copy having the same
characteristics as those of IREF is produced.
For example, Icopy = IREF or 2IREF.
(a) Conceptual illustration of copying a current by an NMOS
device
(b) Generation of a Voltage proportional to square root of current
(c) NMOS current mirror.
where channel-length modulation is neglected.
Thus, the black box must satisfy the following input
(current)/output (voltage) characteristic:
It must operate as a “square-root” circuit.
A diode-connected MOSFET provides such a characteristic
[Fig.3.3b], thus arriving at the NMOS current mirror in Fig 3.3c
We can view the circuit’s operation from two perspectives:
1. MREF takes the square root of IREF and M1 squares the result; or
2. The drain currents of the two transistors can be expressed as
where the threshold voltages are assumed equal. It follows that
which reduces to Icopy = IREF if the two transistors are identical. 56 Prepared by Binoy K P, Asst. Prof., Dept of AE&I, GECK
For More Visit www.ktunotes.in
follows the principles. For example,
Figure 3.4
58 Prepared by Binoy K P, Asst. Prof., Dept of AE&I, GECK
MOS CURRENT MIRRORS
modulation
This effect results in significant error in copying current as
shown by equations below
Figure 3.6
While VDS1=VGS1 =VGS2, VDS2 may not equal VGS2 because
of the circuitry fed by M2.
In order to suppress the effect of channel-length modulation, a
cascode current source can be used.
a. Cascode Current Source
b. Modification of Mirror circuit to generate the Cascode bias voltage
c. Cascode Current Mirror.
CASCODE CURRENT MIRRORS
If Vb is chosen such that VY=VX, then Iout closely tracks IREF.
This is because, the cascode device “shields” the bottom
transistor from variations in VP.
VY remains close to VX and hence ID2≈IDl with high accuracy.
Such accuracy is obtained at the cost of the voltage headroom
consumed by M3.
While L1 must be equal to L2, the length of M3 need not be
equal to L1 and L2.
How do we generate Vb?
Objective is to ensure VY = VX
Vb - VGS3 = VX or Vb = VGS3 + VX
How do we generate Vb? continues…
The idea is to place another diode-connected device M0 Fig (b)
in series with M1, thereby generating a voltage
VN = VGS0 + VX
Proper choice of the dimensions of M0 wrt those of M3 yields
VGS0 = VGS3
Connecting node N to the gate of M3 as shown in Fig (c) we
have
then, VGS0 = VGS3 and VX = VY
Result holds even if M0 and M1 suffer from body effect.
Since M2 and M3 are properly ratioed wrt M1 and M0, we have VY=VX=
The behavior is plotted in Fig (b).
Figure 3.8 (a) Cascode Current Mirror (b) Plot between (VX,VY) v/s IREF
b. Headroom consumed by Cascode Current Mirror.
66
Prepared by Binoy K P, Asst. Prof., Dept of AE&I, GECK For More Visit www.ktunotes.in
While operating as a current source with high output impedance and
accurate value, the consumes substantial voltage headroom.
For simplicity, let us neglect the body effect and assume all of the
transistors are identical.
Then, the minimum allowable voltage at node P is equal to
i.e., two overdrive voltages plus one threshold voltage.
In Fig. 3.9a, Vb is chosen to allow the lowest possible value of VP
but the output current does not accurately track IREF because M1 and
M2 sustain unequal drain-source voltages.
In Fig. 3.9b, higher accuracy is achieved but the minimum level at P
is higher by one threshold voltage.
Figure 3.10 68 Prepared by Binoy K P, Asst. Prof., Dept of AE&I, GECK
In Fig. 3.10(a), assuming all of the transistors are identical, we can sketch IX and VB as VX drops from a large positive value.
For VX ≥ VN - VTH, both M2 and M3 are in saturation, IX = IREF and VB = VA.
As VX drops, M3 enters the triode region first.
Reason:
Suppose M2 enters the triode region before M3 does. For this to occur, VDS2 must drop and, since VGS2 is constant, so must ID2. This means VGS3 increases while ID3 decreases, which is not possible if M3 is still in saturation.
As VX falls below VN - VTH, M3 enters the triode region, requiring a greater gate-source overdrive to carry the same current
Thus, as shown in Fig. 3.10b, VB begins to drop, causing ID2 and hence IX to decrease slightly.
As VX and VB decrease further, eventually we have
VB < VA - VTH and M2 enters the triode region.
At this point, ID2 begins to drop sharply.
For VX = 0, IX = 0, and M2 and M3 operate in deep triode region.
As VX drops below VN – VTH3, the output impedance of the cascode falls rapidly because gm3 degrades in the triode region.
AMPLIFIERS
Qualitative Analysis
Figure 4.1
A zero differential input gives a zero differential output.
To compute the “equilibrium overdrive voltage” of M1 and M2
We assume λ = 0 and hence
ID = (1/2)μnCox(W/L)(VGS − VTH)2
Carrying a current of ISS/2, each device exhibits an overdrive
of

A greater tail current or a smaller W/L translates to a larger
equilibrium overdrive.
To guarantee that M1 andM2 operate in saturation, we require
that their drain voltages not fall below VCM − VTH
VDD − RD (ISS/2) > VCM − VTH
It can also be observed that a change in VCM cannot alter ID1 =
ID2 = ISS/2, leaving VX and VY undisturbed.
The circuit thus rejects input CM variations.
Qualitative Analysis
If Vin1 is well above Vin2 [Fig. 4.2a], then M1 carries the entire tail current, generating
VX = VDD - RD ISS
VY = VDD - RD ISS
VX = VDD
The circuit steers the tail current from one side to the other, producing a differential output in response to a differential input[Fig. 4.2c]
Figure 4.2
(a)Response of MOS differential pair to very positive input, (b) response of MOS differential pair to very negative input, (c) qualitative plots of currents and voltages.
Figure 4.3
inputs
ID1 = (ISS/2) + ΔI and ID2 = (ISS/2) - ΔI or
ID1 = (ISS/2) + Δ ID1 and ID2 = (ISS/2) + Δ ID2
It follows that
Δ ID2 = - gmΔV
The differential voltage gain is given by
Av = −gmRD
Figure 4.4
MOS pair as the differential input varies from very negative
to very positive values.
To obtain ID1-ID2, we neglect channel length modulation and
write a KVL around the input network and a KCL at the tail
node:
Squaring both sides yields
MOS DIFFERENTIAL AMPLIFIERS
Hence
Only the solution with the sum of the two terms is acceptable
83
Eqn 4.1
The equation 4.1 is as expected from the characteristics in
Fig.4.2c, the right-hand side is an odd (symmetric) function of
Vin1-Vin2, dropping to zero for a zero input difference.
The difference under the square root vanishes suggests that
ID1-ID2 falls to zero as (Vin1-Vin2) 2 reaches 4ISS/(μnCoxW/L)
As |Vin1-Vin2| rises, at some point M1 or M2 turns off, violating
the above equations.
We must therefore determine the input difference that places
one of the transistors at the edge of conduction.
Figure 4.5
If, for example, M1 approaches the edge of conduction, then
its gate-source voltage falls to a value equal to VTH.
Also, the gate-source voltage of M2 must be sufficiently large
to accommodate a drain current of ISS:
one transistor at the edge of conduction.
Figure 4.6
Variation of (a) drain currents, (b) the difference between drain currents, and (c) differential output voltage as a function of input.
To calculate the equivalent Gm of M1 and M2 and Av of Differential Amplifier
Denoting ID1-ID2 and Vin1-Vin2 by ΔID and ΔVin resp., taking derivative of eqn 4.1 wrt ΔVin
For ΔVin = 0,
Since Vout1-Vout2= RDΔID= RDGmΔVin, the small signal differential voltage gain of the circuit in equilibrium
and the circuit operates linearly.
Figure 4.7
If λ = 0, the circuit reduces to that shown in Fig 4.7(a), yielding
Assuming perfect symmetry, v1 = -v2 and for differential inputs, we require
vin1 = - vin2.
Thus we get vin1 = v1 and hence vP = vin1 - v1 = 0
With node P acting as a virtual ground, the concept of half circuit applies,
leading to the simplified topology in Fig 4.7(b).
(Refer Slide No 10 – 12 for derivation)
(Refer Slide No 8 – 9 for derivation)
headroom, creating a trade-off between the output voltage swings,
the voltage gain, and the input CM range.
For given bias current and input device dimensions, the circuit’s gain
and the PMOS overdrive voltage scale together.
To achieve a higher gain, (W/L)P must decrease, thereby increasing
|VGSP-VTHP| and lowering the CM level at nodes X and Y.
In order to alleviate the above difficulty, part of the bias currents of
the input transistors can be provided by PMOS current sources (Fig
4.10).
94
CASCADED LOAD
Figure 4.10
their current rather than their aspect ratio.
If M5 and M6 carry 80% of the drain current of M1 and M2, the
current through M3 and M4 is reduced by a factor of five.
For a given |VGSP-VTHP|, this translates to a factor of five
reduction in the transconductance of M3 and M4 because the
aspect ratio of the devices can be lowered by the same factor.
Thus, the differential gain is approximately five times that of
the case with no PMOS current sources.
96
CASCADED LOAD
source loads is relatively low.
We increase the output impedance of both PMOS and NMOS
devices by creating a differential version of the cascode stage.
To calculate the gain, consider the half circuit of Fig. 4.11(b).
Voltage gain and output resistance is same as that of Cascode
Stage (Refer Slide No 39 – 40 for derivation)
Av ≈ −gm3rO3gm1rO1
a. Differential MOS Cascode
b. Half Circuit 98 Prepared by Binoy K P, Asst. Prof., Dept of AE&I, GECK
b. AC Equivalent of Half Circuit
Voltage gain and output resistance is same as that of Cascode
Amplifier with Cascode Current Source Load
(Refer Slide No 41 for derivation)
Av ≈ −gm1[(gm3rO3rO1)||(gm5rO5rO7)]
Rout = (gm3rO3rO1)||(gm5rO5rO7)
CURRENT MIRROR LOAD
In response to a small, differential input, ID1 rises to ISS/2 +ΔI
and ID2 falls to ISS/2 - ΔI.
The change in ID2 tends to raise Vout.
Also, the change in ID1 and ID3 is copied into ID4, increasing
|ID4| and raising Vout.
Figure
4.13
Figure 4.14: MOS pair for small-signal analysis.
The existence of the signal paths in the differential to single-ended converter circuit suggests that the voltage gain of the circuit must be greater than that of a differential topology in which only one output node is sensed with respect to ground.
MOS DIFFERENTIAL AMPLIFIERS WITH
CURRENT MIRROR LOAD While the transistors themselves are symmetric and the input signals
are small and differential, the circuit is asymmetric.
With the diode-connected device, M3, creating a low impedance at
node A, we expect a relatively small voltage swing on the order of
the input swing at this node.
On the other hand, transistors M2 and M4 provide a high impedance
and hence a large voltage swing at the output node.
The asymmetry resulting from the very different voltage swings at
the drains of M1 and M2 disallows grounding node P for small-
signal analysis.
Two approaches to solving this circuit. 103 Prepared by Binoy K P, Asst. Prof., Dept of AE&I, GECK
Approach I
Without a half circuit available, the analysis can be performed through the
use of a complete small-signal model of the amplifier.
Referring to the equivalent circuit shown in Fig. 4.15, where the dashed
boxes indicate each transistor, we perform the analysis in two steps.
In the first step, we note that iX and iY must add up to zero at node P and
hence iX = −iY.
Also,
Small signal equivalent circuit of differential pair with active load.
CURRENT MIRROR LOAD
In the second step, we write a KVL around the loop consisting of all
four transistors.
The current through rON of M1 is equal to iX - gmNv1 and that through
rON of M2 equal to iY - gmNv2.
It follows that
CURRENT MIRROR LOAD
The gain is independent of gmP and equal to that of the fully-
differential circuit.
In other words, the use of the active load has restored the gain.
Approach II
As illustrated in Fig. 4.16(a), we find a Thevenin equivalent for the section consisting of vin1, vin2, M1 and M2, assuming vin1 and vin2 are differential.
vThev is the voltage between A and B in the “open-circuit condition” [Fig. 4.16(b)].
Under this condition, the circuit is symmetric. Then,
vThev = −gmN rON (vin1 − vin2)
To determine the Thevenin resistance, we set the inputs to zero and apply a voltage between the output terminals [Fig. 4.16(c)].
M1 and M2 have equal gate-source voltages (v1=v2) and writing a KVL around the “output” loop, we have
(iX − gm1v1)rO1 + (iX + gm2v2)rO2 = vX
and hence
RThev = 2rON.
Figure 4.16
Diode-connected transistor M3 is replaced with (1/gm3)||rO3
and the output impedance of M4 is drawn explicitly.
The objective is to calculate vout in terms of vThev.
Since the voltage at node E wrt ground is equal to vout+vThev,
we can view vA as a divided version of vE:
Given by gm4vA, the small-signal drain current of M4 must
satisfy KCL at the output node:
where the last term on the left-hand side represents the current
flowing through RThev.
Then
And hence

3. CURRENT MIRRORS

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