1 2xCBC2 hybrid functional test results Mark Raymond, CMS Tracker Week, Tracker Phase 2 Electronics, May 2013. results from screening first 5 bump-bonded hybrids objective to verify functionality - looking for anything that might indicate failure of bump-bonding process
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
11
2xCBC2 hybrid functional test results
Mark Raymond, CMS Tracker Week, Tracker Phase 2 Electronics, May 2013.
results from screening first 5 bump-bonded hybrids
objective to verify functionality - looking for anything that mightindicate failure of bump-bonding process
2
nylon screws Kapton tape
power
LVDS
+
3.3V I2C
hybrid test setup
level shift &power distribution
chip A
chip B
Al support
plate for
hybrid
3
measured power parameters1110
1100
1090
1080
LD
O o
ut
[mV
]
610600590
band-gap [mV]
band-gap voltage accessible via on-chip analogue mux
LDO O/P voltage recorded for baseline set of bias parameters
powering measurementsboth chips powered from 1.2V VDDD railanalogue powered via LDO (VDDD in / VDDA out)current measured in VDDD rail
baseline current (digital + quiescent analogue) ~ 6mA / chip
total hybrid power supply current [mA]baseline
I2C bias values
IPRE1 35
IPRE2 20
IPSF 45
IPA 30
IPAOS 45
VPAFB 0
ICOMP 30
VPC 74
VPLUS 100
LDO out vs. band-gap
conditions hybrid 1
hybrid 2
hybrid 3
hybrid 4
hybrid 5
all current biases zero, SLVS off, both chips 7.0 7.2 6.7 6.7 6.7
all current biases zero, SLVS on for one chip 9.5 9.9 9.3 9.2 9.5
all current biases zero, SLVS on, both chips 12.2 12.7 12.0 11.8 12.3
current biases to baseline values, chip A 39.6 40.1 39.9 41.9 41.1
current biases to baseline values, both chips 67.6 68.8 67.7 70.6 69.6
note: baseline I2C values chosen for no significant external capacitance(IPRE1 needs to be chosen appropriately, depending on sensor capacitance)
4
0.8
0.6
0.4
0.2
[Volts]
400350300250200150100500
I2C value [50 / division]
VCTH VPAFB VPC VPLUS hybrid_1_Chip_A hybrid_1_Chip_B
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2250200150100500
VCTH VPLUS VPC VPAFB
VPAFB, VPC, VPLUS offset by
50, 100, 150 I2C units
respectively
CBC1 measurementvoltage bias sweep measurements
voltage biases externally accessible via on-chip analogue mux
sweep the parameter of interest, all other I2C parameters set to baseline values
no surprises, behaviour as expected, and not significantly different to prototype measurements
CBC2
5
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
[Volts]
250200150100500
I2C value
Chip_A Chip_B
hybrid #10.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
[Volts]
250200150100500
I2C value
Chip_A Chip_B
hybrid #2 hybrid #30.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
[Volts]
250200150100500
I2C value
Chip_A Chip_B
hybrid #4 hybrid #50.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
[Volts]
250200150100500
I2C value
Chip_A Chip_B
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
[Volts]
250200150100500
I2C value
Chip_A Chip_B
voltage bias sweep results - all hybrids
6
200
150
100
50
0250200150100500
80
60
40
20
0
IPRE1 IPRE2 IPSF IPA IPAOS ICOMP
CBC2A solidCBC2B dashed
225
200
175
150
125
100
75
50
25
0
IPR
E1
curr
en
t [m
icro
am
ps]
250200150100500
I2C register setting
90
80
70
60
50
40
30
20
10
0
All o
the
r cu
rren
ts [m
icro
am
ps]
IPRE1 IPRE2 IPSF IPA IPAOS ICOMP
CBC1 measurementcurrent bias sweep measurementsCBC2
IPR
E1 c
urr
ent/channel [u
A]
I2C value
all o
ther c
urre
nts
/channel [u
A]
total current (all channels) measured in supply railsubtract zero value and divide by 254
results as expected, and similar to prototype
7
hybrid #1
200
150
100
50
02001000
IPRE1 IPRE2 IPSF IPA IPAOS ICOMP
A solidB dashed
hybrid #2 hybrid #3
20010002001000 2001000
hybrid #4
2001000
80
60
40
20
0
hybrid #5
IPR
E1 c
urr
ent
[uA
/channe
l]all o
ther c
urre
nts
[uA
/channel]
current bias sweep measurements - all hybrids
I2C value
8
240
220
200
180
160
140
1206050403020100
gain measurements
VC
TH
[I2
C u
nits]
test pulse amplitude [I2C units]
hybrid 5, chip A, 254 channels sweep test pulse amplitude and measures-curve mid-points by sweeping global comparatorthreshold voltage VCTH
comparator offsets tuned to a VCTH vlaue of 150at test pulse amplitude 12
(12 corresponds to approximately 1 fCassuming 20fF charge injection capacitance)
12
150
9
240
200
160
1206040200 6040200
hybrid#1
s-c
urv
e m
id-p
oin
ts [
VC
TH
I2C
units]
test pulse amplitude [I2C units]
240
200
160
1206040200 6040200
hybrid#2
240
200
160
1206040200 6040200
240
200
160
1206040200 6040200
hybrid#3 hybrid#4
240
200
160
1206040200 6040200
hybrid#5
not much differencechip-to-chip orhybrid-to-hybrid
gain measurements - all hybrids
10
2.0
1.8
1.6
1.4
1.2
1.02001000 2001000
2.0
1.8
1.6
1.4
1.2
1.02001000 2001000
2.0
1.8
1.6
1.4
1.2
1.02001000 2001000
2.0
1.8
1.6
1.4
1.2
1.02001000 2001000
2.0
1.8
1.6
1.4
1.2
1.02001000 2001000
GA
IN [
VC
TH
I2C
units /
TP
I2C
units]
channel number
hybrid#1
hybrid#3
hybrid#5
hybrid#2
hybrid#4
fit shows slope for some chipshigher gains for higher channel nos.~ flat for some chips (but no negative slope)across chip trend in charge inject capacitors?would expect opposite slope as well
... need more data
gain vs. channel number
11
250
200
150
100
50
0
I2C
valu
e
250200150100500
CBC2 channel
250200150100500
CBC2 channel
250200150100500
CBC2 channel
250
200
150
100
50
0
I2C
valu
e
250200150100500
CBC2 channel
250200150100500
CBC2 channel
hybrid#1 hybrid#2 hybrid#3
hybrid#5hybrid#4
chip A
chip B
all channels tuned to position S-curve midpoints at same value of global comparator threshold VCTH
chip-to-chip variation in average level and channel-to-channel spread within tuning range
not necessary to adjust any other parameter
individual comparator channel offset tuning - all hybrids
80f
VPLUS
IPAOS
20k
VPAFB
1M
hybrid 5, CBC2_A
100
80
60
40
20
025020015010050
100
80
60
40
20
025020015010050
100
80
60
40
20
025020015010050
100
80
60
40
20
025020015010050
counts
charge injection time [nsec]
test pulse injection time sweep
using on-chip test pulse
sweep time of charge injection for range of test pulse amplitudes
comparator threshold at 1 fC
test pulse amplitudes 1.25, 2, 4, 10 fC
TP amp 1.25 fC
TP amp 2 fC
TP amp 4 fC
TP amp 10 fC
13
hybrid#1 hybrid#2
hybrid#3 hybrid#4
hybrid#5
test pulse injection time sweep - all hybrids
not much differencechip-to-chip orhybrid-to-hybrid
14
Kapton tape
input channel connectivity testing
asynchronous squarewave applied to hybrid support plate
capacitively couples to hybrid input sensor traces
repetitively trigger chip and count hits
expect more hits in channels on bottom of substrate
hybrid substrate
Al support plate
Kaptonpads on substrate bottom connectto odd channel numbers on CBC
pads on substrate top connectto even channel numbers on CBC
15
input channel connectivity testing
triggered output frame shows multiple hits
stub shift register output indicates multiple stubs found
trigger output very active
16
100
1000
250200150100500
100
1000
250200150100500
100
1000
250200150100500
100
1000
250200150100500
100
1000
250200150100500
hybrid #1
hybrid #2
hybrid #3
hybrid #4
hybrid #5
channel
input channel connectivity testing - chip position A
=> all channels connected
17
100
1000
250200150100500
100
1000
250200150100500
100
1000
250200150100500
100
1000
250200150100500
100
1000
250200150100500
hybrid #1
hybrid #2
hybrid #3
hybrid #4
hybrid #5
channel
input channel connectivity testing - chip position B
=> all channels connected
18
summary
1st run of five 2xCBC2 hybrid assemblies successful fromelectrical viewpoint
all chips functional, good uniformity of performance
strong evidence of very high yield of bump-bond connectivity
some redundancy in back end padsbut 100% yield of input channel bonds (254 bonds per chip)
DC
-DC
LDO
pipeline+
buffering
254 a
mp
lifi
er/
co
mp
ara
tor
ch
an
nels
CW
D,
off
set
co
rrecti
on
an
d c
ollera
ltio
n lo
gic
ban
dg
ap
bia
s g
en
.
254
inputs
5 mm
11mm
inter-chip
signals
inter-chip
signals
Related Documents
