$P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $V $V $V $V $V $V $V $V $V $V $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $P $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V $V U700 $V $V $V $V $V $V $V Engineer LVPECL Size 7 Latch Enable Clock H 3 100MHz LVDS REV Drawn by D E The University of Chicago 5620 S. Ellis Ave. R&D CHK 1 H 7 G 8 5 D JTAG Connector TIME: A DRW. 2793 L 400MHz LVPECL H H H C Not Used F A 2 9/18/12 5 B QA CHK F 2:00 pm 4 Sheet A Chicago, IL 60637 16-Ch, GHz AC/DC ADC Module 4 4 FPGA 2 E G 8 1 TITLE B 6 DATE: C 3 6 C 1V2 0 1 2 M.Bogdan M.Bogdan 0 TC0 15 PLL_EN 0 $V $V 4 10u C28 18 31 12 13 10 C1V5_24 0.1 $V 0 6 7 8 9 10 5 6 7 8 23 16 17 0.1 C1V5_36 $V 13 14 AJ9 VREFB7N1_AJ9 AK2 VREFB7N2_AK2 AK31 VREFB8N0_AK31 AJ24 VREFB8N1_AJ24 AK19 VREFB8N2_AK19 AL3 nCEO_AL3 C30 nCE_C30 AL30 nCONFIG_AL30 AK3 nIO_PULLUP_AK3 B30 nSTATUS_B30 C31 VREFB3N2_C31 C2 VREFB4N0_C2 D9 VREFB4N1_D9 C14 VREFB4N2_C14 P3 VREFB5N0_P3 J5 VREFB5N1_J5 F5 VREFB5N2_F5 AG5 VREFB6N0_AG5 AD5 VREFB6N1_AD5 W3 VREFB6N2_W3 AK14 VREFB7N0_AK14 VCC_PLL12_OUT_AF16 J16 VCC_PLL5_OUT_J16 AF15 VCC_PLL6_OUT_AF15 W30 VREFB1N0_W30 AD28 VREFB1N1_AD28 AG28 VREFB1N2_AG28 F28 VREFB2N0_F28 J28 VREFB2N1_J28 P30 VREFB2N2_P30 C19 VREFB3N0_C19 D24 VREFB3N1_D24 N12 VCCPD5_N12 R12 VCCPD5_R12 V12 VCCPD6_V12 Y12 VCCPD6_Y12 AA13 VCCPD7_AA13 AA15 VCCPD7_AA15 AA18 VCCPD8_AA18 AA20 VCCPD8_AA20 AC23 VCCSEL_AC23 J17 VCC_PLL11_OUT_J17 AF16 AH21 VCCIO8_AH21 AM18 VCCIO8_AM18 AM30 VCCIO8_AM30 V21 VCCPD1_V21 Y21 VCCPD1_Y21 N21 VCCPD2_N21 R21 VCCPD2_R21 M18 VCCPD3_M18 M20 VCCPD3_M20 M13 VCCPD4_M13 M15 VCCPD4_M15 VCCIO5_R1 T12 VCCIO5_T12 AA5 VCCIO6_AA5 AK1 VCCIO6_AK1 U12 VCCIO6_U12 V1 VCCIO6_V1 AA16 VCCIO7_AA16 AH12 VCCIO7_AH12 AM15 VCCIO7_AM15 AM3 VCCIO7_AM3 AA17 VCCIO8_AA17 A18 VCCIO3_A18 A30 VCCIO3_A30 E21 VCCIO3_E21 M17 VCCIO3_M17 A15 VCCIO4_A15 A3 VCCIO4_A3 E12 VCCIO4_E12 M16 VCCIO4_M16 C1 VCCIO5_C1 M5 VCCIO5_M5 R1 Y16 VCCINT_Y16 Y18 VCCINT_Y18 Y20 VCCINT_Y20 AA28 VCCIO1_AA28 AK32 VCCIO1_AK32 U21 VCCIO1_U21 V32 VCCIO1_V32 C32 VCCIO2_C32 M28 VCCIO2_M28 R32 VCCIO2_R32 T21 VCCIO2_T21 VCCINT_U19 V14 VCCINT_V14 V16 VCCINT_V16 V18 VCCINT_V18 V20 VCCINT_V20 W13 VCCINT_W13 W15 VCCINT_W15 W17 VCCINT_W17 W19 VCCINT_W19 W21 VCCINT_W21 Y14 VCCINT_Y14 R15 VCCINT_R15 R17 VCCINT_R17 R19 VCCINT_R19 T14 VCCINT_T14 T16 VCCINT_T16 T18 VCCINT_T18 T20 VCCINT_T20 U13 VCCINT_U13 U15 VCCINT_U15 U17 VCCINT_U17 U19 K23 VCCINT_K23 M21 VCCINT_M21 N13 VCCINT_N13 N15 VCCINT_N15 N17 VCCINT_N17 N19 VCCINT_N19 P14 VCCINT_P14 P16 VCCINT_P16 P18 VCCINT_P18 P20 VCCINT_P20 R13 VCCINT_R13 VCCD_PLL2_V25 U7 VCCD_PLL3_U7 T9 VCCD_PLL4_T9 H15 VCCD_PLL5_H15 AD15 VCCD_PLL6_AD15 H25 VCCD_PLL7_H25 AF25 VCCD_PLL8_AF25 AE8 VCCD_PLL9_AE8 AA12 VCCINT_AA12 AC10 VCCINT_AC10 K10 VCCINT_K10 R9 VCCA_PLL4_R9 G15 VCCA_PLL5_G15 AE15 VCCA_PLL6_AE15 H26 VCCA_PLL7_H26 AF26 VCCA_PLL8_AF26 AE7 VCCA_PLL9_AE7 H7 VCCD_PLL10_H7 J18 VCCD_PLL11_J18 AE18 VCCD_PLL12_AE18 U24 VCCD_PLL1_U24 V25 C3 TDO_C3 B3 TEMPDIODEn_B3 G9 TEMPDIODEp_G9 AE24 TMS_AE24 AK30 TRST_AK30 H8 VCCA_PLL10_H8 H17 VCCA_PLL11_H17 AF18 VCCA_PLL12_AF18 T24 VCCA_PLL1_T24 V26 VCCA_PLL2_V26 U9 VCCA_PLL3_U9 NC_N11 P22 NC_P22 P23 NC_P23 W10 NC_W10 W11 NC_W11 W22 NC_W22 W23 NC_W23 AF8 PLL_ENA_AF8 AL2 PORSEL_AL2 AF24 TCK_AF24 AL31 TDI_AL31 H3 NC_H3 H4 NC_H4 H5 NC_H5 H6 NC_H6 H9 NC_H9 J29 NC_J29 J30 NC_J30 L27 NC_L27 L28 NC_L28 N10 NC_N10 N11 AF5 NC_AF5 AF6 NC_AF6 AG21 NC_AG21 AG25 NC_AG25 F21 NC_F21 F25 NC_F25 G14 NC_G14 G27 NC_G27 G28 NC_G28 G5 NC_G5 G6 NC_G6 NC_AC30 AD29 NC_AD29 AD3 NC_AD3 AD30 NC_AD30 AD4 NC_AD4 AE5 NC_AE5 AE6 NC_AE6 AE9 NC_AE9 AF14 NC_AF14 AF27 NC_AF27 AF28 NC_AF28 Y5 IO_Y5 Y6 IO_Y6 Y7 IO_Y7 Y8 IO_Y8 Y9 IO_Y9 B2 MSEL0_B2 F6 MSEL1_F6 J10 MSEL2_J10 H10 MSEL3_H10 AC29 NC_AC29 AC30 Y23 IO_Y23 Y24 IO_Y24 Y25 IO_Y25 Y26 IO_Y26 Y27 IO_Y27 Y28 IO_Y28 Y29 IO_Y29 Y3 IO_Y3 Y30 IO_Y30 Y31 IO_Y31 Y4 IO_Y4 IO_W32 W4 IO_W4 W5 IO_W5 W6 IO_W6 W7 IO_W7 W8 IO_W8 W9 IO_W9 Y10 IO_Y10 Y11 IO_Y11 Y2 IO_Y2 Y22 IO_Y22 V9 IO_V9 W1 IO_W1 W2 IO_W2 W24 IO_W24 W25 IO_W25 W26 IO_W26 W27 IO_W27 W28 IO_W28 W29 IO_W29 W31 IO_W31 W32 V23 IO_V23 V24 IO_V24 V28 IO_V28 V29 IO_V29 V3 IO_V3 V30 IO_V30 V31 IO_V31 V4 IO_V4 V5 IO_V5 V6 IO_V6 V7 IO_V7 IO_U2 U22 IO_U22 U23 IO_U23 U27 IO_U27 U28 IO_U28 U31 IO_U31 U32 IO_U32 U5 IO_U5 U6 IO_U6 V10 IO_V10 V2 IO_V2 T23 IO_T23 T27 IO_T27 T28 IO_T28 T31 IO_T31 T32 IO_T32 T5 IO_T5 T6 IO_T6 U1 IO_U1 U10 IO_U10 U11 IO_U11 U2 R30 IO_R30 R31 IO_R31 R4 IO_R4 R5 IO_R5 R6 IO_R6 R7 IO_R7 T1 IO_T1 T10 IO_T10 T11 IO_T11 T2 IO_T2 T22 IO_T22 IO_R11 R2 IO_R2 R22 IO_R22 R23 IO_R23 R24 IO_R24 R25 IO_R25 R26 IO_R26 R27 IO_R27 R28 IO_R28 R29 IO_R29 R3 IO_R3 P29 IO_P29 P31 IO_P31 P32 IO_P32 P4 IO_P4 P5 IO_P5 P6 IO_P6 P7 IO_P7 P8 IO_P8 P9 IO_P9 R10 IO_R10 R11 N8 IO_N8 N9 IO_N9 P1 IO_P1 P10 IO_P10 P11 IO_P11 P2 IO_P2 P24 IO_P24 P25 IO_P25 P26 IO_P26 P27 IO_P27 P28 IO_P28 IO_N26 N27 IO_N27 N28 IO_N28 N29 IO_N29 N3 IO_N3 N30 IO_N30 N31 IO_N31 N4 IO_N4 N5 IO_N5 N6 IO_N6 N7 IO_N7 M4 IO_M4 M6 IO_M6 M7 IO_M7 M8 IO_M8 M9 IO_M9 N2 IO_N2 N22 IO_N22 N23 IO_N23 N24 IO_N24 N25 IO_N25 N26 M22 IO_M22 M23 IO_M23 M24 IO_M24 M25 IO_M25 M26 IO_M26 M27 IO_M27 M29 IO_M29 M3 IO_M3 M30 IO_M30 M31 IO_M31 M32 IO_M32 IO_L32 L4 IO_L4 L5 IO_L5 L6 IO_L6 L7 IO_L7 L8 IO_L8 L9 IO_L9 M1 IO_M1 M10 IO_M10 M11 IO_M11 M2 IO_M2 L21 IO_L21 L22 IO_L22 L23 IO_L23 L24 IO_L24 L25 IO_L25 L26 IO_L26 L29 IO_L29 L3 IO_L3 L30 IO_L30 L31 IO_L31 L32 L10 IO_L10 L12 IO_L12 L13 IO_L13 L14 IO_L14 L15 IO_L15 L16 IO_L16 L17 IO_L17 L18 IO_L18 L19 IO_L19 L2 IO_L2 L20 IO_L20 IO_K29 K3 IO_K3 K30 IO_K30 K31 IO_K31 K32 IO_K32 K4 IO_K4 K6 IO_K6 K7 IO_K7 K8 IO_K8 K9 IO_K9 L1 IO_L1 K18 IO_K18 K19 IO_K19 K2 IO_K2 K20 IO_K20 K21 IO_K21 K22 IO_K22 K24 IO_K24 K25 IO_K25 K26 IO_K26 K27 IO_K27 K29 J7 IO_J7 J8 IO_J8 J9 IO_J9 K1 IO_K1 K11 IO_K11 K12 IO_K12 K13 IO_K13 K14 IO_K14 K15 IO_K15 K16 IO_K16 K17 IO_K17 IO_J20 J21 IO_J21 J22 IO_J22 J23 IO_J23 J26 IO_J26 J27 IO_J27 J3 IO_J3 J31 IO_J31 J32 IO_J32 J4 IO_J4 J6 IO_J6 H31 IO_H31 H32 IO_H32 J1 IO_J1 J11 IO_J11 J12 IO_J12 J13 IO_J13 J14 IO_J14 J15 IO_J15 J19 IO_J19 J2 IO_J2 J20 H19 IO_H19 H2 IO_H2 H20 IO_H20 H21 IO_H21 H22 IO_H22 H23 IO_H23 H24 IO_H24 H27 IO_H27 H28 IO_H28 H29 IO_H29 H30 IO_H30 IO_G29 G3 IO_G3 G30 IO_G30 G31 IO_G31 G32 IO_G32 G4 IO_G4 H1 IO_H1 H11 IO_H11 H12 IO_H12 H13 IO_H13 H14 IO_H14 G12 IO_G12 G13 IO_G13 G19 IO_G19 G2 IO_G2 G20 IO_G20 G21 IO_G21 G22 IO_G22 G23 IO_G23 G24 IO_G24 G25 IO_G25 G29 F29 IO_F29 F3 IO_F3 F30 IO_F30 F31 IO_F31 F32 IO_F32 F4 IO_F4 F8 IO_F8 F9 IO_F9 G1 IO_G1 G10 IO_G10 G11 IO_G11 IO_F14 F15 IO_F15 F16 IO_F16 F17 IO_F17 F18 IO_F18 F19 IO_F19 F2 IO_F2 F20 IO_F20 F22 IO_F22 F23 IO_F23 F24 IO_F24 E5 IO_E5 E6 IO_E6 E7 IO_E7 E8 IO_E8 E9 IO_E9 F1 IO_F1 F10 IO_F10 F11 IO_F11 F12 IO_F12 F13 IO_F13 F14 E24 IO_E24 E25 IO_E25 E26 IO_E26 E27 IO_E27 E28 IO_E28 E29 IO_E29 E3 IO_E3 E30 IO_E30 E31 IO_E31 E32 IO_E32 E4 IO_E4 IO_E11 E13 IO_E13 E14 IO_E14 E15 IO_E15 E16 IO_E16 E17 IO_E17 E18 IO_E18 E19 IO_E19 E2 IO_E2 E20 IO_E20 E22 IO_E22 D26 IO_D26 D27 IO_D27 D28 IO_D28 D31 IO_D31 D32 IO_D32 D5 IO_D5 D6 IO_D6 D7 IO_D7 D8 IO_D8 E1 IO_E1 E11 D15 IO_D15 D16 IO_D16 D17 IO_D17 D18 IO_D18 D19 IO_D19 D2 IO_D2 D20 IO_D20 D21 IO_D21 D22 IO_D22 D23 IO_D23 D25 IO_D25 IO_C5 C6 IO_C6 C7 IO_C7 C8 IO_C8 C9 IO_C9 D1 IO_D1 D10 IO_D10 D11 IO_D11 D12 IO_D12 D13 IO_D13 D14 IO_D14 C21 IO_C21 C22 IO_C22 C23 IO_C23 C24 IO_C24 C25 IO_C25 C26 IO_C26 C27 IO_C27 C28 IO_C28 C29 IO_C29 C4 IO_C4 C5 B8 IO_B8 B9 IO_B9 C10 IO_C10 C11 IO_C11 C12 IO_C12 C13 IO_C13 C15 IO_C15 C16 IO_C16 C17 IO_C17 C18 IO_C18 C20 IO_C20 IO_B23 B24 IO_B24 B25 IO_B25 B26 IO_B26 B27 IO_B27 B28 IO_B28 B29 IO_B29 B4 IO_B4 B5 IO_B5 B6 IO_B6 B7 IO_B7 B13 IO_B13 B14 IO_B14 B15 IO_B15 B16 IO_B16 B17 IO_B17 B18 IO_B18 B19 IO_B19 B20 IO_B20 B21 IO_B21 B22 IO_B22 B23 AM28 IO_AM28 AM29 IO_AM29 AM4 IO_AM4 AM5 IO_AM5 AM6 IO_AM6 AM7 IO_AM7 AM8 IO_AM8 AM9 IO_AM9 B10 IO_B10 B11 IO_B11 B12 IO_B12 IO_AM14 AM16 IO_AM16 AM17 IO_AM17 AM19 IO_AM19 AM21 IO_AM21 AM22 IO_AM22 AM23 IO_AM23 AM24 IO_AM24 AM25 IO_AM25 AM26 IO_AM26 AM27 IO_AM27 AL29 IO_AL29 AL4 IO_AL4 AL5 IO_AL5 AL6 IO_AL6 AL7 IO_AL7 AL8 IO_AL8 AL9 IO_AL9 AM10 IO_AM10 AM11 IO_AM11 AM12 IO_AM12 AM14 AL18 IO_AL18 AL19 IO_AL19 AL20 IO_AL20 AL21 IO_AL21 AL22 IO_AL22 AL23 IO_AL23 AL24 IO_AL24 AL25 IO_AL25 AL26 IO_AL26 AL27 IO_AL27 AL28 IO_AL28 IO_AK7 AK8 IO_AK8 AK9 IO_AK9 AL10 IO_AL10 AL11 IO_AL11 AL12 IO_AL12 AL13 IO_AL13 AL14 IO_AL14 AL15 IO_AL15 AL16 IO_AL16 AL17 IO_AL17 AK23 IO_AK23 AK24 IO_AK24 AK25 IO_AK25 AK26 IO_AK26 AK27 IO_AK27 AK28 IO_AK28 AK29 IO_AK29 AK4 IO_AK4 AK5 IO_AK5 AK6 IO_AK6 AK7 AK10 IO_AK10 AK11 IO_AK11 AK12 IO_AK12 AK13 IO_AK13 AK15 IO_AK15 AK16 IO_AK16 AK17 IO_AK17 AK18 IO_AK18 AK20 IO_AK20 AK21 IO_AK21 AK22 IO_AK22 IO_AJ23 AJ25 IO_AJ25 AJ26 IO_AJ26 AJ27 IO_AJ27 AJ28 IO_AJ28 AJ31 IO_AJ31 AJ32 IO_AJ32 AJ5 IO_AJ5 AJ6 IO_AJ6 AJ7 IO_AJ7 AJ8 IO_AJ8 AJ14 IO_AJ14 AJ15 IO_AJ15 AJ16 IO_AJ16 AJ17 IO_AJ17 AJ18 IO_AJ18 AJ19 IO_AJ19 AJ2 IO_AJ2 AJ20 IO_AJ20 AJ21 IO_AJ21 AJ22 IO_AJ22 AJ23 AH4 IO_AH4 AH5 IO_AH5 AH6 IO_AH6 AH7 IO_AH7 AH8 IO_AH8 AH9 IO_AH9 AJ1 IO_AJ1 AJ10 IO_AJ10 AJ11 IO_AJ11 AJ12 IO_AJ12 AJ13 IO_AJ13 IO_AH20 AH22 IO_AH22 AH24 IO_AH24 AH25 IO_AH25 AH26 IO_AH26 AH28 IO_AH28 AH29 IO_AH29 AH3 IO_AH3 AH30 IO_AH30 AH31 IO_AH31 AH32 IO_AH32 AH1 IO_AH1 AH11 IO_AH11 AH13 IO_AH13 AH14 IO_AH14 AH15 IO_AH15 AH16 IO_AH16 AH17 IO_AH17 AH18 IO_AH18 AH19 IO_AH19 AH2 IO_AH2 AH20 AG22 IO_AG22 AG23 IO_AG23 AG24 IO_AG24 AG29 IO_AG29 AG3 IO_AG3 AG30 IO_AG30 AG31 IO_AG31 AG32 IO_AG32 AG4 IO_AG4 AG8 IO_AG8 AG9 IO_AG9 IO_AG11 AG12 IO_AG12 AG13 IO_AG13 AG14 IO_AG14 AG15 IO_AG15 AG16 IO_AG16 AG17 IO_AG17 AG18 IO_AG18 AG19 IO_AG19 AG2 IO_AG2 AG20 IO_AG20 AF22 IO_AF22 AF23 IO_AF23 AF29 IO_AF29 AF3 IO_AF3 AF30 IO_AF30 AF31 IO_AF31 AF32 IO_AF32 AF4 IO_AF4 AG1 IO_AG1 AG10 IO_AG10 AG11 AE32 IO_AE32 AE4 IO_AE4 AF1 IO_AF1 AF10 IO_AF10 AF11 IO_AF11 AF12 IO_AF12 AF13 IO_AF13 AF19 IO_AF19 AF2 IO_AF2 AF20 IO_AF20 AF21 IO_AF21 IO_AE21 AE22 IO_AE22 AE23 IO_AE23 AE25 IO_AE25 AE26 IO_AE26 AE27 IO_AE27 AE28 IO_AE28 AE29 IO_AE29 AE3 IO_AE3 AE30 IO_AE30 AE31 IO_AE31 AD9 IO_AD9 AE1 IO_AE1 AE10 IO_AE10 AE11 IO_AE11 AE12 IO_AE12 AE13 IO_AE13 AE14 IO_AE14 AE19 IO_AE19 AE2 IO_AE2 AE20 IO_AE20 AE21 AD22 IO_AD22 AD23 IO_AD23 AD24 IO_AD24 AD25 IO_AD25 AD26 IO_AD26 AD27 IO_AD27 AD31 IO_AD31 AD32 IO_AD32 AD6 IO_AD6 AD7 IO_AD7 AD8 IO_AD8 IO_AD1 AD10 IO_AD10 AD11 IO_AD11 AD12 IO_AD12 AD13 IO_AD13 AD14 IO_AD14 AD18 IO_AD18 AD19 IO_AD19 AD2 IO_AD2 AD20 IO_AD20 AD21 IO_AD21 AC26 IO_AC26 AC27 IO_AC27 AC3 IO_AC3 AC31 IO_AC31 AC32 IO_AC32 AC4 IO_AC4 AC6 IO_AC6 AC7 IO_AC7 AC8 IO_AC8 AC9 IO_AC9 AD1 AC15 IO_AC15 AC16 IO_AC16 AC17 IO_AC17 AC18 IO_AC18 AC19 IO_AC19 AC2 IO_AC2 AC20 IO_AC20 AC21 IO_AC21 AC22 IO_AC22 AC24 IO_AC24 AC25 IO_AC25 IO_AB4 AB5 IO_AB5 AB6 IO_AB6 AB7 IO_AB7 AB8 IO_AB8 AB9 IO_AB9 AC1 IO_AC1 AC11 IO_AC11 AC12 IO_AC12 AC13 IO_AC13 AC14 IO_AC14 AB24 IO_AB24 AB25 IO_AB25 AB26 IO_AB26 AB27 IO_AB27 AB28 IO_AB28 AB29 IO_AB29 AB3 IO_AB3 AB30 IO_AB30 AB31 IO_AB31 AB32 IO_AB32 AB4 AB13 IO_AB13 AB14 IO_AB14 AB15 IO_AB15 AB16 IO_AB16 AB17 IO_AB17 AB18 IO_AB18 AB19 IO_AB19 AB2 IO_AB2 AB20 IO_AB20 AB21 IO_AB21 AB23 IO_AB23 IO_AA31 AA32 IO_AA32 AA4 IO_AA4 AA6 IO_AA6 AA7 IO_AA7 AA8 IO_AA8 AA9 IO_AA9 AB1 IO_AB1 AB10 IO_AB10 AB11 IO_AB11 AB12 IO_AB12 AA2 IO_AA2 AA22 IO_AA22 AA23 IO_AA23 AA24 IO_AA24 AA25 IO_AA25 AA26 IO_AA26 AA27 IO_AA27 AA29 IO_AA29 AA3 IO_AA3 AA30 IO_AA30 AA31 A28 IO_A28 A29 IO_A29 A4 IO_A4 A5 IO_A5 A6 IO_A6 A7 IO_A7 A8 IO_A8 A9 IO_A9 AA1 IO_AA1 AA10 IO_AA10 AA11 IO_AA11 IO_A14 A16 IO_A16 A17 IO_A17 A19 IO_A19 A21 IO_A21 A22 IO_A22 A23 IO_A23 A24 IO_A24 A25 IO_A25 A26 IO_A26 A27 IO_A27 W20 GND_W20 Y1 GND_Y1 Y13 GND_Y13 Y15 GND_Y15 Y17 GND_Y17 Y19 GND_Y19 Y32 GND_Y32 A10 IO_A10 A11 IO_A11 A12 IO_A12 A14 V11 GND_V11 V13 GND_V13 V15 GND_V15 V17 GND_V17 V19 GND_V19 V22 GND_V22 V27 GND_V27 W12 GND_W12 W14 GND_W14 W16 GND_W16 W18 GND_W18 GND_R18 R20 GND_R20 T13 GND_T13 T15 GND_T15 T17 GND_T17 T19 GND_T19 T7 GND_T7 U14 GND_U14 U16 GND_U16 U18 GND_U18 U20 GND_U20 N20 GND_N20 N32 GND_N32 P12 GND_P12 P13 GND_P13 P15 GND_P15 P17 GND_P17 P19 GND_P19 P21 GND_P21 R14 GND_R14 R16 GND_R16 R18 J24 GND_J24 K28 GND_K28 K5 GND_K5 L11 GND_L11 M12 GND_M12 M14 GND_M14 M19 GND_M19 N1 GND_N1 N14 GND_N14 N16 GND_N16 N18 GND_N18 GND_AM13 AM2 GND_AM2 AM20 GND_AM20 AM31 GND_AM31 B1 GND_B1 B32 GND_B32 E10 GND_E10 E23 GND_E23 F27 GND_F27 F7 GND_F7 G17 GND_G17 AC28 GND_AC28 AC5 GND_AC5 AF17 GND_AF17 AF9 GND_AF9 AG6 GND_AG6 AH10 GND_AH10 AH23 GND_AH23 AH27 GND_AH27 AL1 GND_AL1 AL32 GND_AL32 AM13 AG27 GNDA_PLL8_AG27 AF7 GNDA_PLL9_AF7 AG7 GNDA_PLL9_AG7 A13 GND_A13 A2 GND_A2 A20 GND_A20 A31 GND_A31 AA14 GND_AA14 AA19 GND_AA19 AA21 GND_AA21 AB22 GND_AB22 GNDA_PLL3_U8 V8 GNDA_PLL3_V8 R8 GNDA_PLL4_R8 T8 GNDA_PLL4_T8 G16 GNDA_PLL5_G16 H16 GNDA_PLL5_H16 AD16 GNDA_PLL6_AD16 AE16 GNDA_PLL6_AE16 F26 GNDA_PLL7_F26 G26 GNDA_PLL7_G26 AG26 GNDA_PLL8_AG26 G7 GNDA_PLL10_G7 G8 GNDA_PLL10_G8 G18 GNDA_PLL11_G18 H18 GNDA_PLL11_H18 AD17 GNDA_PLL12_AD17 AE17 GNDA_PLL12_AE17 T25 GNDA_PLL1_T25 T26 GNDA_PLL1_T26 U25 GNDA_PLL2_U25 U26 GNDA_PLL2_U26 U8 U3 CLK9p_U3 J25 CONF_DONE_J25 B31 DCLK_B31 D4 FPLL10CLKn_D4 D3 FPLL10CLKp_D3 D29 FPLL7CLKn_D29 D30 FPLL7CLKp_D30 AJ29 FPLL8CLKn_AJ29 AJ30 FPLL8CLKp_AJ30 AJ4 FPLL9CLKn_AJ4 AJ3 FPLL9CLKp_AJ3 EP2S60F1020 U699 $V T4 CLK11n_T4 T3 CLK11p_T3 T29 CLK1n_T29 T30 CLK1p_T30 U29 CLK3n_U29 U30 CLK3p_U30 U4 CLK9n_U4 1 2 $V 0 R00 19 6 6 PLL1v2 0.001uF +3.3V 26 +3.3V 1 R44 1K $V C10 20 1 2 3 4 5 2 3 4 3 18 C17 C18 0.001uF C15 0.1uF 0.1uF 0.001uF 0.001uF C16 C1V5_23 0.1 $V 15 C14 28 +2.5V 9 TC0 18 3 4 0.1 C1V5_22 $V $V TDp 0 $V 19 14 3 C1V5_13 0.1 PLL1V17 C1V5_20 0.1 $V $V 16 JTAG_0 4 0.001uF 0.1 C1V5_19 $V 0.1 C1V5_3 VCC3 67 VCC4 68 VCC5 92 VCC6 43 VCCW 45 WP_ 60 nCS 16 nINIT_CONF 1 PGM2 66 PORSEL 37 RY_BY_ 35 TCK 42 TDI 44 TDO 71 TM0 40 TM1 48 TMS 12 VCC1 22 VCC2 59 2 GND1 41 GND2 58 GND3 70 GND4 69 GND5 79 GND6 23 OE 80 OE_ 14 PGM0 13 PGM1 15 DQ6 100 DQ7 82 DQ8 85 DQ9 61 EXCLK 75 F_A0 56 F_A1 25 F_A15 6 F_A16 39 F_RP_ 38 F_WE_ 87 DQ10 90 DQ11 94 DQ12 97 DQ13 99 DQ14 1 DQ15 86 DQ2 89 DQ3 93 DQ4 95 DQ5 98 73 DATA0 84 DATA1 88 DATA2 91 DATA3 96 DATA4 10 DATA5 9 DATA6 8 DATA7 11 DCLK 81 DQ0 83 DQ1 A7 34 A8 32 A9 5 BYTE_ 78 CE_ 65 C_A0 62 C_A1 21 C_A15 17 C_A16 72 C_RP_ 33 C_WE_ 26 A14 49 A17 47 A18 46 A19 55 A2 36 A20 54 A3 53 A4 52 A5 51 A6 50 1 6 10 EPC16_0 EPC16_100 31 A10 29 A11 28 A12 27 A13 17 8 C1V5_28 0.1 $V F70 0.1uF 6 1 TC0 0 0 1 TC0 2 7 Q2 Q2n 4 5 Q3 Q3n 6 7 VCC1 VCC2 14 11 VT Vref 10 +3.3V 7 EP4 GND 13 9 INn In 12 Q0 15 16 Q0n Q1 1 2 Q1n 3 5 6 Q3n 7 VCC1 VCC2 14 VT 11 10 Vref +3.3V NB6N14S F3 8 EN EP4 13 GND INn 9 12 In 15 Q0 Q0n 16 1 Q1 Q1n 2 Q2 3 4 Q2n Q3 21 0 F2 NB6N14S EN 8 0.1 C1V5_29 $V 11 1 F1_2V 1A $V 2 18 TROE 8 6 6 8 DIRTR 1 2 11 12 9 O4 8 14 VDD 0.1uF C1 2 $V U566 3D3314_10 DDD GND 7 1 I1 3 I2 4 I3 5 I4 O1 12 O2 10 O3 10u C26 15 15 4 $V 240 R51 9 19 1 2 5 0 22 R65 C1V5_39 0.1 $V 0.1 $V 10 26 11 15 PLL1V13 0.1uF C1V5_11 1K R58 1 +3.3V 16 0.1uF C2 +3.3V +3.3V $V 7 5 0.1 C1V5_35 $V 0.001uF 4 2 0.1uF PLL1V11 PLL1V15 C1V5_6 0.1 $V 4 0 9 +1.2V_PLL 17 18 19 20 4 3 0 4 2 3 14 tp TDI_0 2 3 0 C1V5_15 0.1 $V 12 16 0.1 C1V5_1 $V 0.001uF C20 0.1uF C19 8 9 C24 10u 18 7 15 30 4 5 6 7 PLL1V12 PLL1V18 0.001uF PLL1V16 0.001uF 0.1uF PLL1V19 0.1uF PLL1V10 0.1uF 0.001uF 3 0.001uF U631 PLL1V14 JTAG_0 5 C27 10u C5 0.1uF 10 11 tp2 PGM2_0 C1V5_26 $V 17 10u C25 21 0.1 $V 14 0.1 0.1uF C13 16 C1V5_38 R43 2 JTAG_0 7 3 4 3 +1.2V_PLL C4 0.001uF $V 1K 0.1uF 1 18 JTAG_0 R56 10K $V C7 14 15 16 MSEL3 0 $V 20 Rclkin 100 $V 1 11 12 13 16 +3.3V 12 13 14 7 9 10 4 20 5 7 13 11 2 C30 0.1uF $V 21 22 19 nIO_PULL 0 $V 3V3PLL $V 0.1 C1V5_14 4 9 tp2 PORSEL_0 +3.3V 0 8 3 8 11 12 13 0 MSEL0 24 20 9 2 10 17 12 19 $V 8 9 10 11 12 13 JTAG_0 14 15 16 17 7 6 5 $V 0 MSEL2 27 20 2 0 1 10 6 4 3 21 22 0.1 $V 0 1 5 21 0.1 C1V5_12 $V C1V5_17 C1V5_27 $V 14 21 18 13 0.1 C1V5_31 $V 0.1 1 2 4 11 12 1 23 3 R53 240 $V 17 11 0.1 C1V5_5 $V 8 21 22 17 16 1 Q1 Q1n 2 Q2 3 4 Q2n Q3 5 6 Q3n 7 VCC1 VCC2 14 VT 11 10 Vref +3.3V F5 NB6N14S EN 8 EP4 13 GND INn 9 12 In 15 Q0 Q0n 0.1 C1V5_30 $V 13 17 C6 14 15 15 18 29 C29 10u +3.3V 0.001uF 0 1 2 3 0 14 4 5 12 3 21 5 $V 0 1 2 3 2 3 4 +3.3V 0.1 C1V5_8 9 13 1 C1V5_34 0.1 $V $V 10K R57 11 12 13 C1V5_10 0.1 $V 4K7 R502 12 8 9 10 8 2 3 13 14 6 25 4 $V 1K R50 +3.3V 0 0 9 $V 10K R55 13 27 $V 1K R45 6 8 9 10 11 16 17 9 PGM0_0 tp2 6 7 5 6 2 3 $V 0 VCCSEL 19 9 8 7 F65 0.1uF F66 0.1uF $V F64 0.1uF 18 17 14 16 11 R54 1K C11 0.1uF JTAG_0 8 +3.3V 0.1uF C9 0 1 4 5 15 +3.3V C1V5_32 0.1 $V +3.3V 0 F44 space F45 space +3.3V space F48 F43 space 11 12 17 0.001uF C8 12 0.1uF C3 0.1 C1V5_4 $V nCE 0 $V 10 F31 5 10 12 F69 0 3 F57 50 0.1uF F68 0.1uF 0.1uF 0.1uF F67 0.1uF F33 F35 16 3 18 18 19 20 0.1 $V 24 15 13 $V 0 TDn C1V5_16 1 TC0 16 space F37 125 F52 84 F55 F54 84 F32 +1.2V 22 F51 125 +3.3V F34 0.1uF 10uF 18 SEL0 19 SEL1 7 SEL2 14 SEL3 VCC1 4 17 VCC2 VCCA 15 VCO 13 8 VEE +3.3V 1 CLKn 2 6 FBIN FBINn 5 3 MR 20 NC 16 PLL_SEL Q 12 10 QFB QFBn 9 11 Qn 14 JTAG_0 2 1K F46 15 8735AM_21 F50 CLK TC0 1 C1V5_25 0.1 $V 23 8 TC0 19 TC0 20 3 B 5 GND 1 NC 4 Vbb 8 Vcc 7 Y 6 Z 10 F59 50 50 F60 SN65LVDS100DR F58 2 A 0.1uF F61 0.1uF F62 F36 0.1uF +3.3V F72 125 F74 84 84 F73 F56 0.1uF +3.3V 125 F71 13 13 17 TC0 10 TC0 11 TC0 12 TC0 6 5 2 3 15 18 +3.3V 17 25 9 0 7 $V F19 SM7745DV125M CLK125 3 CLK 1 EN 2 GND 4 VCC F39 F47 space 14 +3.3V 5 C1V5_18 $V 0.1uF F63 1K 2 1 0 10 0.1 5 11 23 +3.3V 7 16 3 TDO_TDI_0 tp 16 20 21 1 7 $V tp2 TP1 21 22 23 12 +3.3V 1K F38 +3.3V 19 20 $V 23 R46 10K $V 0 0.1 C1V5_33 $V 7 1V2PLL PGM1_0 tp2 3 $V 1K R49 16 C1V5_9 0.1 $V 22 5 6 0.1 C1V5_37 $V C1V5_40 $V $V 10K R47 $V 0 TRST 29 +3.3V 0.1 0.1 $V 10 9 MSEL1 0 $V 16 8 5 6 30 C1V5_21 10 JTAG_0 1 3 4 7 JTAG_0 6 2 GND 3 IN 2 OUT 4 1 SD_ 15 TC0 14 17 1 2 R48 1K $V $V U600 LP3883ET 5 BIAS +3.3V_PLL TC0 9 28 PLL3v3 4 3 1 2 18 19 20 31 F40 space 25 2 VCCO5 35 VCCO6 38 VCCO7 48 VCCO8 6 VEE1 19 VEE2 30 VEE3 VEE4 43 +3.3V F42 1K Q7_ Q8 9 Q8_ 10 Q9 7 Q9_ 8 VCC1 12 VCC2 13 1 VCCO1 11 VCCO2 14 VCCO3 24 VCCO4 25 29 Q2_ 26 Q3 27 Q3_ 22 Q4 23 Q4_ 20 Q5 21 Q5_ 17 Q6 18 Q6_ 15 Q7 16 3 Q12 46 Q12_ 47 Q13 44 Q13_ 45 Q14 41 Q14_ 42 Q15 39 Q15_ 40 32 Q1_ 28 Q2 +3.3V SY898530U F53 CLK 36 CLK_ 37 33 Q0 34 Q0_ 31 Q1 Q10 4 Q10_ 5 Q11 2 Q11_ 15 R42 1K $V +3.3V 5 $V 33 Rerr $V VCC 13 14 1 +3.3V +3.3V +3.3V C1V5_2 0.1 $V 19 20 21 0 11 R501 4K7 C1V5_7 0.1 TC0 7 TC0 8 7 18 3 TC0 4 TC0 5 TC0 6 JTAG_0 10 17 18 2 TC0 dp124 DigInput2 LVDS dp124 DigInput1n LVDS dp122 DigOutput3n LVDS dp123 DigOutput2n LVDS dp121 DigInput1 LVDS dp122 DigOutput3 LVDS dp123 DigOutput2 LVDS dp121 DigIO2(7:0) 1K F41 +3.3V +3.3V +1.2V_PLL DigInput2n LVDS ADC_Aux_0 GND +3.3V VCCIO11 VCCIO12 VCCIO9 VCCIO10 master_clock0 LVDS dp120 master_clock0n LVDS dp120 +3.3V +3.3V ADC_Aux_2n ADC_Aux_2 GND three_tr_5 three_tr_5n zero_tr_5 zero_tr_5n GND* GND* GND* GND* GND* GND* VCCPD6 GND VCCINT GND VCCINT GND VCCINT GND VCCINT VCCPD1 GND* GND* GND* GND* GND* GND* DigInput0n DigInput0 ADC_Aux_0n GND GND* GND* ADC_Aux_3n ADC_Aux_3 VCCIO1 zero_tr_6 zero_tr_6n VREFB6 GND* GND* GND* GND* GND* GND* GND VCCINT GND VCCINT GND VCCINT GND VCCINT GND VCCINT GND* GND* GND* GND* GND* GND* VREFB1 GND* GND* GND+ GND+ ADC3_0n ADC3_0 VCCIO6 one_tr_6 one_tr_6n GND* GND* GND* GND* GNDA_PLL3 GND* GND* GND VCCPD6 GND VCCINT GND VCCINT GND VCCINT GND VCCINT VCCPD1 GND GND* GND* VCCD_PLL2 VCCA_PLL2 GND* GND* GND+ GND+ ADC1_0n ADC1_0 two_tr_6 two_tr_6n GND+ GND+ GND* GND* VCCD_PLL3 GNDA_PLL3 VCCA_PLL3 GND* GND* VCCIO6 VCCINT GND VCCINT GND VCCINT GND VCCINT GND VCCIO1 GND* GND* VCCD_PLL1 GNDA_PLL2 GNDA_PLL2 GND* GND* GND* ADC4_0n ADC4_0 VCCIO2 three_tr_6 three_tr_6n GND+ GND+ GND* GND* GND GNDA_PLL4 VCCD_PLL4 GND* GND* VCCIO5 GND VCCINT GND VCCINT GND VCCINT GND VCCINT VCCIO2 GND* GND* VCCA_PLL1 GNDA_PLL1 GNDA_PLL1 GND* GND* GND* VREFB2 ADC2_0n ADC2_0 VCCIO5 one_tr_7 one_tr_7n GND* GND* GND* GND* GNDA_PLL4 VCCA_PLL4 GND* GND* VCCPD5 VCCINT GND VCCINT GND VCCINT GND VCCINT GND VCCPD2 GND* GND* GND* GND* GND* GND* GND* GND* ADC2_2n ADC2_2 ADC1_1n ADC1_1 GND zero_tr_7 zero_tr_7n VREFB5 GND* GND* GND* GND* GND* am_2 GND* GND* GND GND VCCINT GND VCCINT GND VCCINT GND VCCINT GND GND* GND* GND* GND* GND* GND* GND* GND* VCCIO2 ADC2_1n ADC2_1 ADC3_1n ADC3_1 GND three_tr_7 three_tr_7n two_tr_3 two_tr_3n address_13 address_12 address_21 GND* VCCPD5 VCCINT GND VCCINT GND VCCINT GND VCCINT GND VCCPD2 GND* GND* GND* debug_6 GND* GND* GND* GND* GND* ADC4_2n ADC4_2 ADC4_1n ADC4_1 two_tr_7 two_tr_7n one_tr_3 one_tr_3n VCCIO5 address_11 address_22 GND* GND* GND* GND* GND VCCPD4 GND VCCPD4 VCCIO4 VCCIO3 VCCPD3 GND VCCPD3 VCCINT GND* DRS_A3_3 GND* VCCINT _iackin DRS_PLLLCK2 GND* GND* GND ADC1_2n ADC1_2 ADC3_2n ADC3_2 zero_tr_3 zero_tr_3n three_tr_3 three_tr_3n GND* GND* GND* GND* GND* GND* GND GND* GND* address_20 vme_data_10 vme_data_23 vme_data_2 address_8 DRS_SRIN4 DRS_A3_1 GND* GND* DRS_A4_3 GND* GND* GND CONF_DONE GND* GND* VREFB2 ADC3_3n ADC3_3 zero_tr_2 zero_tr_2n one_tr_2 one_tr_2n GND GND* GND* GND* GND* VCCINT GND* GND* vme_data_13 vme_data_27 vme_data_1 vme_data_12 _modsel address_14 DRS_SRCLK2 DRS_PLLLCK4 GNDA_PLL11 GND* DRS_A2_1 GND* GND* DRS_WSRIN2 VCCD_PLL7 VCCA_PLL7 GND* GND* ADC2_4n ADC2_4 ADC1_3n ADC1_3 two_tr_2 two_tr_2n zero_tr_1 zero_tr_1n VREFB5 DRS_REFCLK DRS_REFCLKn Compclk Compclkn MSEL2 debug_3 GND* GND* am_1 vme_data_24 VCC_PLL5_OUT VCC_PLL11_OUT VCCD_PLL11 address_24 address_18 address_25 vme_data_19 VCCA_PLL5 GNDA_PLL5 GND GNDA_PLL11 DRS_DWRITE ~CRC_ERROR~ GND* GND* GND* GND* _iackout GNDA_PLL7 ADC3_4n ADC3_4 ADC4_3n ADC4_3 three_tr_2 three_tr_2n VCCD_PLL10 VCCA_PLL10 MSEL3 GND* GND* GND* address_9 VCCD_PLL5 GNDA_PLL5 VCCA_PLL11 MSEL1 GND debug_13 GND* GND* address_10 address_26 vme_data_30 vme_data_7 vme_data_18 _dtack dir_trans _vme_data_str _vme_write GND* GND* DRS_WSRIN4 GND* GNDA_PLL7 GND VREFB2 ADC1_4n ADC1_4 ADC2_3n ADC2_3 one_tr_1 one_tr_1n two_tr_1 two_tr_1n GNDA_PLL10 GNDA_PLL10 TEMPDIODEp GND* GND* GND* GND* GND address_23 VCCIO4 vme_data_6 vme_data_8 vme_data_29 vme_data_15 transceivers_OE address_3 DRS_SRCLK4 DRS_SRIN3 VCCIO3 GND* GND GND* GND* GND* GND* GND* ADC4_5n ADC4_5 ADC4_4n ADC4_4 three_tr_1 three_tr_1n zero_tr_0 zero_tr_0n VREFB5 GND* GND* GND* VREFB4 address_15 vme_data_14 vme_data_22 vme_data_5 vme_data_11 vme_data_4 _iack address_2 clkswitchcontrol DRS_SRIN2 DRS_RESET GND* GND* GND* VREFB3 GND* DRS_A2_2 GND* GND* GND+ _berrin ADC2_5n ADC2_5 one_tr_0 one_tr_0n two_tr_0 two_tr_0n GND* DRS_PLLLCK1 GND* GND* GND* GND* vme_data_17 vme_data_20 vme_data_0 VREFB4 _ds_1 _ds_0 address_6 led_0 VREFB3 DRS_SRIN1 PDWN GND* DRS_A1_0 DRS_A3_0 GND* DRS_A2_3 GND* GND* GND* nCE VREFB3 VCCIO2 three_tr_0 three_tr_0n GND+ DRS_SROUT1 DRS_SRLOAD1 GND* GND* GND* GND* GND* vme_data_26 vme_data_9 vme_data_25 address_17 _as vme_data_16 address_4 address_5 address_16 DRS_DENABLE GND* GND* DRS_A2_0 DRS_A4_1 DRS_A3_2 DRS_A1_3 GND* GND* debug_2 nSTATUS DCLK GND VCCIO5 VREFB4 TDO GND* GND* GND* GND* GND* GND* DRS_SRLOAD4 GND* GND* GND* GND GND* VCCIO7 led_2 master_clock0 VCCIO8 samplingclock GND CSB1 CSB_Aux GND* GND* GND* GND* GND* debug_11 GND* VCCIO8 GND GND MSEL0 TEMPDIODEn GND* _berr address_31 GND* GND* GND* GND* GND* GND* GND* GND* DRS_WSRIN3 GND* GND* clkswitch master_clock0n DRS_calib_clock samplingclockn DAC_Control_1 SDIO3 SDIO_Aux GND* GND* GND* debug_16 GND* SCLK2 GND* nCONFIG TDI GND GND VCCIO7 address_28 am_3 debug_15 GND* GND* GND* GND* GND* GND* DRS_SROUT3 DRS_SROUT2 VREFB7 GND* GND* master_clock1 DRS_calib_clockn VREFB8 DAC_Control_3 SDIO4 DAC_ControlBi_4 RecOut GND* SCLK_Aux GND* GND* GND* GND* TRST VREFB8 VCCIO1 GND PORSEL nCEO address_27 _ga_0 GND* GND* GND* VREFB7 GND* GND* DRS_SRLOAD3 DRS_SRLOAD2 GND* GND* GND* GND* CLK_Aux DAC_Control_4 Sw_control2 SDIO1 DAC_ControlBi_2 DAC_ControlBi_1 VREFB8 GND* GND* GND* SCLK4 GND+ GND+ GND* GND* VCCIO6 VREFB7 nIO_PULLUP ADC3_5n _ga_4 GND* GND* GND* GND* GND GND* VCCIO7 GND* GND* GND* led_1 DRS_SRCLK3 CLK_Auxn DAC_Control_2 Sw_control4 VCCIO8 CRC_ERROR_IN GND GND* debug_18 GND* GND debug_17 GND* GND* FCO_Auxn FCO_Aux ADC1_5 ADC1_5n am_0 ADC3_6n ADC4_6 ADC4_6n VREFB6 GND GNDA_PLL9 GND* GND* GND* GND* GND* GND* GND* GND* debug_8 DRS_WSROUT3 DRS_WSROUT4 DRS_WSROUT1 GND* DAC_ControlBi_5 debug_10 GND* GNDA_PLL8 GNDA_PLL8 VREFB1 GND* GND* FCO4n FCO4 ADC2_6 ADC2_6n ADC3_5 FCO2n FCO2 ADCclk1n ADCclk1 ADC1_7 ADC1_7n ADC1_6 ADC1_6n GNDA_PLL9 PLL_ENA GND GND* debug_19 debug_14 GND* VCC_PLL6_OUT VCC_PLL12_OUT GND VCCA_PLL12 CSB3 GND* GND* GND* GND* TCK VCCD_PLL8 VCCA_PLL8 FCO1n FCO1 FCO3n FCO3 ADC3_6 DigOutput2n DigOutput2 GND* GND* VREFB1 ADCclk2n ADCclk2 ADC4_7 ADC4_7n ADC2_7 ADC2_7n VCCA_PLL9 VCCD_PLL9 GND* GND* sysclk GND* GND* VCCA_PLL6 GNDA_PLL6 GNDA_PLL12 VCCD_PLL12 DRS_WSROUT2 GND* GND* GND* debug_7 TMS DigOutput1n DigOutput1 DigOutput0n DigOutput0 SCLK1 debug_9 GND* VCCSEL GND* GND* GND* GND* GND ADC_Aux_Clockn ADC_Aux_Clock ADC3_7 ADC3_7n VREFB6 GND* GND* _ga_3 _ga_1 address_30 GND* GND* GND* GND* VCCD_PLL6 GNDA_PLL6 GNDA_PLL12 DAC_ControlBi_3 DRS_SRCLK1 SCLK3 GND* GND* debug_4 GND* debug_12 GND DigOutput3n DigOutput3 GND* GND* ADCclk4n ADCclk4 ADCclk3n ADCclk3 DigInput2n DigInput2 one_tr_4 one_tr_4n zero_tr_4 zero_tr_4n GND GND* GND* am_4 _lword VCCINT GND* GND* GND* debug_5 GND* GND* DAC_ControlBi_0 DAC_Control_0 Sw_control1 VCCPD8 GND GND* GND* GND* GND* GND* GND* VCCIO1 DigInput1n DigInput1 ADC_Aux_1n ADC_Aux_1 three_tr_4 three_tr_4n two_tr_4 two_tr_4n GND* GND* GND* GND* address_29 _ga_2 am_5 DRS_SROUT4 GND* GND* DRS_PLLLCK3 GND* PDWN_Aux Sw_control3 SDIO2 address_19 GND CSB4 CSB2 DRS_A4_0 DRS_A1_1 DRS_A4_2 DRS_A1_2 GND* GND* GND* VCCIO3 GND two_tr_5 two_tr_5n one_tr_5 one_tr_5n VCCIO6 GND* GND* GND* GND* GND* GND* VCCINT VCCPD7 GND VCCPD7 VCCIO7 VCCIO8 VCCPD8 GND +3.3V DAC_ControlBi_5 TTL BIDAC_Control[5:0] ~DATA0~ GND VCCIO4 GND* DRS_WSRIN1 GND* GND* GND* GND* GND* vme_data_21 vme_data_28 GND vme_data_31 VCCIO4 vme_data_3 address_7 VCCIO3 ck2p ck2n ck3p ck3n ck4p ck4n ck5p ck5n ck6p ck6n ck7p ck7n ck8p ck8n ck9p ck9n ck10p ck10n ck11p ck11n ck12p ck12n ck13p ck13n ck14p ck14n ck15p ck15n ck16p ck16n +3.3V ck15n dp78 LVDS three_tr_6 dp79 LVDS three_tr_6n dp79 LVDS three_tr_7 dp80 LVDS three_tr_7n dp80 LVDS ck16p dp81 LVDS ck16n dp81 LVDS +3.3V Compclk LVDS dp125 Compclkn LVDS dp125 ck1p ck1n dp73 LVDS three_tr_2n dp73 LVDS three_tr_3 dp74 LVDS three_tr_3n dp74 LVDS ck14p dp75 LVDS ck14n dp75 LVDS three_tr_4 dp76 LVDS three_tr_4n dp76 LVDS three_tr_5 dp77 LVDS three_tr_5n dp77 LVDS ck15p dp78 LVDS two_tr_7 dp57 LVDS two_tr_7n dp57 LVDS ck12p dp58 LVDS ck12n dp58 LVDS Comp_IO4[23:0] three_tr_0 dp70 LVDS three_tr_0n dp70 LVDS three_tr_1 dp71 LVDS three_tr_1n dp71 LVDS ck13p dp72 LVDS ck13n dp72 LVDS three_tr_2 dp51 LVDS ck10p dp52 LVDS ck10n dp52 LVDS two_tr_4 dp53 LVDS two_tr_4n dp53 LVDS two_tr_5 dp54 LVDS two_tr_5n dp54 LVDS ck11p dp55 LVDS ck11n dp55 LVDS two_tr_6 dp56 LVDS two_tr_6n dp56 LVDS ck8n dp35 LVDS Comp_IO3[23:0] two_tr_0 dp47 LVDS two_tr_0n dp47 LVDS two_tr_1 dp48 LVDS two_tr_1n dp48 LVDS ck9p dp49 LVDS ck9n dp49 LVDS two_tr_2 dp50 LVDS two_tr_2n dp50 LVDS two_tr_3 dp51 LVDS two_tr_3n dp30 LVDS one_tr_4n dp30 LVDS one_tr_5 dp31 LVDS one_tr_5n dp31 LVDS ck7p dp32 LVDS ck7n dp32 LVDS one_tr_6 dp33 LVDS one_tr_6n dp33 LVDS one_tr_7 dp34 LVDS one_tr_7n dp34 LVDS ck8p dp35 LVDS LVDS one_tr_1 dp25 LVDS one_tr_1n dp25 LVDS ck5p dp26 LVDS ck5n dp26 LVDS one_tr_2 dp27 LVDS one_tr_2n dp27 LVDS one_tr_3 dp28 LVDS one_tr_3n dp28 LVDS ck6p dp29 LVDS ck6n dp29 LVDS one_tr_4 ck3p dp9 LVDS ck3n dp9 LVDS zero_tr_6 dp10 LVDS zero_tr_6n dp10 LVDS zero_tr_7 dp11 LVDS zero_tr_7n dp11 LVDS ck4p dp12 LVDS ck4n dp12 LVDS Comp_IO1[23:0] Comp_IO2[23:0] one_tr_0 dp24 LVDS one_tr_0n dp24 +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V dp7 LVDS zero_tr_4n dp7 LVDS zero_tr_5 dp8 LVDS zero_tr_5n dp8 LVDS debug_2 debug_3 debug_4 debug_5 debug_6 debug_7 debug_8 debug_9 debug_10 debug_11 debug_12 debug_13 debug_14 debug_15 debug_16 debug_17 debug_18 debug_19 TTL DAC_ControlBi_2 TTL DAC_ControlBi_3 TTL DAC_ControlBi_4 TTL ck1p dp3 LVDS ck1n dp3 LVDS zero_tr_2 dp4 LVDS zero_tr_2n dp4 LVDS zero_tr_3 dp5 LVDS zero_tr_3n dp5 LVDS ck2p dp6 LVDS ck2n dp6 LVDS zero_tr_4 dp100 DRS_calib_clock LVDS $P dp100 DRS_calib_clockn LVDS $P dp101 DRS_REFCLK LVDS $P dp101 DRS_REFCLKn DAC_Control[4:0] DAC_Control_0 TTL DAC_Control_1 TTL DAC_Control_2 TTL DAC_Control_3 TTL DAC_Control_4 TTL DAC_ControlBi_0 TTL DAC_ControlBi_1 DRS_REFCLK2 LVDS dp107 DRS_REFCLK2n LVDS dp107 DRS_calib_clock3 LVDS dp104 DRS_calib_clock3n LVDS dp104 DRS_REFCLK3 LVDS dp108 DRS_REFCLK3n LVDS dp108 DRS_calib_clock4 LVDS dp105 DRS_calib_clock4n LVDS dp105 DRS_REFCLK4 LVDS dp109 DRS_REFCLK4n LVDS dp109 LVDS $P LVDS dp99 $P samplingclock LVDS dp99 $P samplingclockn +3.3V +3.3V DRS_calib_clock1 LVDS dp102 DRS_calib_clock1n LVDS dp102 DRS_REFCLK1 LVDS dp106 DRS_REFCLK1n LVDS dp106 DRS_calib_clock2 LVDS dp103 DRS_calib_clock2n LVDS dp103 ADC_Aux_0n dp113 LVDS ADC_Aux_1 dp114 LVDS ADC_Aux_1n dp114 LVDS ADC_Aux_2 dp115 LVDS ADC_Aux_2n dp115 LVDS ADC_Aux_3 dp116 LVDS ADC_Aux_3n dp116 LVDS +3.3V samplingclock1 samplingclock1n samplingclock2 samplingclock2n samplingclock3 samplingclock3n samplingclock4 samplingclock4n dp92 ADC_Control4[3:0] SCLK4 TTL SDIO4 TTL CSB4 TTL PDWN TTL ADC_Out_Aux[13:0] CLK_Aux dp110 LVDS CLK_Auxn dp110 LVDS FCO_Aux dp111 LVDS FCO_Auxn dp111 LVDS ADC_Aux_Clock dp112 LVDS ADC_Aux_Clockn dp112 LVDS ADC_Aux_0 dp113 LVDS ADC4_2n LVDS dp87 ADC4_3 LVDS dp88 ADC4_3n LVDS dp88 ADC4_4 LVDS dp89 ADC4_4n LVDS dp89 ADC4_5 LVDS dp90 ADC4_5n LVDS dp90 ADC4_6 LVDS dp91 ADC4_6n LVDS dp91 ADC4_7 LVDS dp92 ADC4_7n LVDS LVDS dp82 samplingclock4n LVDS dp82 FCO4 LVDS dp83 FCO4n LVDS dp83 ADCclk4 LVDS dp84 ADCclk4n LVDS dp84 ADC4_0 LVDS dp85 ADC4_0n LVDS dp85 ADC4_1 LVDS dp86 ADC4_1n LVDS dp86 ADC4_2 LVDS dp87 TTL DRS_SRCLK4 TTL DRS_SRIN4 TTL DRS_SROUT4 TTL DRS_WSROUT4 TTL DRS_WSRIN4 TTL DRS_A4_0 TTL DRS_A4_1 TTL drs_A4_2 TTL DRS_A4_3 TTL DRS_PLLLCK4 TTL ADC_Control_Aux[3:0] SCLK_Aux TTL SDIO_Aux TTL CSB_Aux TTL PDWN_Aux TTL ADC_Out4[21:0] samplingclock4 ADC3_5 LVDS dp67 ADC3_5n LVDS dp67 ADC3_6 LVDS dp68 ADC3_6n LVDS dp68 ADC3_7 LVDS dp69 ADC3_7n LVDS dp69 DRS_Control4[20:0] Sw_control4 TTL DRS_calib_clock4 DRS_calib_clock4n DRS_REFCLK4 DRS_REFCLK4n DRS_DENABLE TTL DRS_DWRITE TTL DRS_RESET TTL DRS_SRLOAD4 LVDS dp61 ADC3_0 LVDS dp62 ADC3_0n LVDS dp62 ADC3_1 LVDS dp63 ADC3_1n LVDS dp63 ADC3_2 LVDS dp64 ADC3_2n LVDS dp64 ADC3_3 LVDS dp65 ADC3_3n LVDS dp65 ADC3_4 LVDS dp66 ADC3_4n LVDS dp66 drs_A3_2 TTL DRS_A3_3 TTL DRS_PLLLCK3 TTL ADC_Control3[3:0] SCLK3 TTL SDIO3 TTL CSB3 TTL PDWN TTL ADC_Out3[21:0] samplingclock3 LVDS dp59 samplingclock3n LVDS dp59 FCO3 LVDS dp60 FCO3n LVDS dp60 ADCclk3 LVDS dp61 ADCclk3n ADC2_7n LVDS dp46 DRS_Control3[20:0] Sw_control3 TTL DRS_calib_clock3 DRS_calib_clock3n DRS_REFCLK3 DRS_REFCLK3n DRS_DENABLE TTL DRS_DWRITE TTL DRS_RESET TTL DRS_SRLOAD3 TTL DRS_SRCLK3 TTL DRS_SRIN3 TTL DRS_SROUT3 TTL DRS_WSROUT3 TTL DRS_WSRIN3 TTL DRS_A3_0 TTL DRS_A3_1 TTL LVDS dp41 ADC2_2n LVDS dp41 ADC2_3 LVDS dp42 ADC2_3n LVDS dp42 ADC2_4 LVDS dp43 ADC2_4n LVDS dp43 ADC2_5 LVDS dp44 ADC2_5n LVDS dp44 ADC2_6 LVDS dp45 ADC2_6n LVDS dp45 ADC2_7 LVDS dp46 ADC_Out2[21:0] samplingclock2 LVDS dp36 samplingclock2n LVDS dp36 FCO2 LVDS dp37 FCO2n LVDS dp37 ADCclk2 LVDS dp38 ADCclk2n LVDS dp38 ADC2_0 LVDS dp39 ADC2_0n LVDS dp39 ADC2_1 LVDS dp40 ADC2_1n LVDS dp40 ADC2_2 TTL DRS_SRLOAD2 TTL DRS_SRCLK2 TTL DRS_SRIN2 TTL DRS_SROUT2 TTL DRS_WSROUT2 TTL DRS_WSRIN2 TTL DRS_A2_0 TTL DRS_A2_1 TTL drs_A2_2 TTL DRS_A2_3 TTL DRS_PLLLCK2 TTL ADC_Control2[3:0] SCLK2 TTL SDIO2 TTL CSB2 TTL PDWN TTL LVDS dp20 ADC1_5 LVDS dp21 ADC1_5n LVDS dp21 ADC1_6 LVDS dp22 ADC1_6n LVDS dp22 ADC1_7 LVDS dp23 ADC1_7n LVDS dp23 DRS_Control2[20:0] Sw_control2 TTL DRS_calib_clock2 DRS_calib_clock2n DRS_REFCLK2 DRS_REFCLK2n DRS_DENABLE TTL DRS_DWRITE TTL DRS_RESET dp15 ADCclk1n LVDS dp15 ADC1_0 LVDS dp16 ADC1_0n LVDS dp16 ADC1_1 LVDS dp17 ADC1_1n LVDS dp17 ADC1_2 LVDS dp18 ADC1_2n LVDS dp18 ADC1_3 LVDS dp19 ADC1_3n LVDS dp19 ADC1_4 LVDS dp20 ADC1_4n dp1 LVDS zero_tr_1 dp2 LVDS zero_tr_1n dp2 LVDS ADC_Control1[3:0] SCLK1 TTL SDIO1 TTL CSB1 TTL PDWN TTL ADC_Out1[21:0] samplingclock1 LVDS dp13 samplingclock1n LVDS dp13 FCO1 LVDS dp14 FCO1n LVDS dp14 ADCclk1 LVDS DRS_DENABLE TTL TTL DRS_DWRITE DRS_RESET TTL DRS_SRLOAD1 TTL DRS_SRCLK1 TTL DRS_SRIN1 TTL DRS_SROUT1 TTL DRS_WSROUT1 TTL DRS_WSRIN1 TTL DRS_A1_0 TTL DRS_A1_1 TTL drs_A1_2 TTL DRS_A1_3 TTL DRS_PLLLCK1 TTL zero_tr_0 dp1 LVDS zero_tr_0n +3.3V +3.3V power_line 5 +3.3V DigIO1(7:0) nConfig TTL RecOut TTL Reconfig[1:0] ~CRC_ERROR~ TTL CRC_ERROR_IN TTL DRS_Control1[20:0] Sw_control1 TTL DRS_calib_clock1 DRS_calib_clock1n DRS_REFCLK1 DRS_REFCLK1n clkswitch $P +3.3V master_clock1 +3.3V +3.3V VCCD_PLL3 VCCD_PLL4 VCCD_PLL5 VCCD_PLL6 VCCD_PLL7 VCCD_PLL8 VCCD_PLL9 VCCD_PLL10 VCCD_PLL11 VCCD_PLL12 +1.2V_PLL +3.3V PORSEL nSTATUS $P ~DATA0~ $P DCLK $P CONF_DONE nCONFIG led_1 $P $P led_0 $P JTAG_TCK JTAG_TDO JTAG_TMS JTAG_TDI GND VCCA_PLL3 VCCIO3 VCCPD2 VREFB8 GND+ VCCA_PLL4 VCCIO4 VCCPD3 VCCA_PLL5 VCCIO5 VCCPD4 VCCA_PLL6 VCCIO6 VCCPD5 VCCA_PLL7 VCCIO7 VCCPD6 VCCA_PLL8 VCCIO8 +2.5V VCCPD7 VCCA_PLL9 VCCPD8 VCCA_PLL10 VCCA_PLL11 VCCA_PLL12 VCCD_PLL1 VCCD_PLL2 GNDA_PLL2 GNDA_PLL3 VCC_PLL5_OUT GNDA_PLL4 VCC_PLL6_OUT GNDA_PLL5 VCC_PLL11_OUT GNDA_PLL6 VCC_PLL12_OUT $P +3.3V_PLL GNDA_PLL7 VREFB1 GNDA_PLL8 VREFB2 GNDA_PLL9 VREFB3 GNDA_PLL10 VREFB4 GNDA_PLL11 VREFB5 GNDA_PLL12 VCCA_PLL1 VREFB6 GND* VCCA_PLL2 $P VCCIO2 VCCPD1 VREFB7 dp119 DigInput0 LVDS dp118 VME_ETC(30:0) _berrin TTL +3.3V clkswitchcontrol TEMPDIODEn TEMPDIODEp TRST PLL_ENA MSEL3 DigOutput0n LVDS dp117 DigOutput1n LVDS dp119 DigInput0n LVDS dp118 VCCIO1 VCCINT $P GNDA_PLL1 address_29 TTL address_30 TTL address_31 TTL transceivers_OE TTL dir_trans TTL _modsel TTL _vme_data_str TTL _delayed_modsel TTL _delayed_ds TTL +3.3V _as_undel TTL _as TTL +1.2V DigOutput0 LVDS dp117 DigOutput1 LVDS address_13 TTL address_14 TTL address_15 TTL address_16 TTL address_17 TTL address_18 TTL address_19 TTL address_20 TTL address_21 TTL address_22 TTL address_23 TTL address_24 TTL address_25 TTL address_26 TTL address_27 TTL address_28 TTL _iack TTL am_2 TTL am_5 TTL am_0 TTL _iackin TTL address_2 TTL address_3 TTL address_4 TTL address_5 TTL address_6 TTL address_7 TTL address_8 TTL address_9 TTL address_10 TTL address_11 TTL address_12 TTL _iackout TTL sysclk TTL _ds_1 TTL _lword TTL _ds_0 TTL _vme_write TTL am_4 TTL _berr TTL am_3 TTL am_1 TTL _dtack TTL _ga_0 TTL _ga_1 TTL _ga_2 TTL _ga_3 TTL _ga_4 TTL short_A1 short_A15 short_A16 short_A0 short_A1 short_A15 short_A16 VME_Addr(31:2) _as_undel TTL TDI TMS TCK JTAG_TDI MSEL1 MSEL0 MSEL2 nCE VCCSEL nIO_PULLUP +3.3V vme_data[31:0] GND GND +3.3V +3.3V JTAG_TCK JTAG_TDO JTAG_TMS TCK TDO TMS short_A0 +3.3V vme_data_16 TTL vme_data_17 TTL vme_data_18 TTL vme_data_19 TTL vme_data_20 TTL vme_data_21 TTL vme_data_22 TTL vme_data_23 TTL vme_data_24 TTL vme_data_25 TTL vme_data_26 TTL vme_data_27 TTL vme_data_28 TTL vme_data_29 TTL vme_data_30 TTL vme_data_31 TTL vme_data_0 TTL vme_data_1 TTL vme_data_2 TTL vme_data_3 TTL vme_data_4 TTL vme_data_5 TTL vme_data_6 TTL vme_data_7 TTL vme_data_8 TTL vme_data_9 TTL vme_data_10 TTL vme_data_11 TTL vme_data_12 TTL vme_data_13 TTL vme_data_14 TTL vme_data_15 TTL