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251931229 Multi Core Processors Ppt

Jun 01, 2018

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    GROUP MEMBERS

    Ali Raza SP13-BCS-006

    Usman Ahmed SP13-BCS-017

    Sajid Imtiaz SP13-BCS-025

    Mudassa Rehman SP13-BCS-0

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    TOPIC

    Multi-!"e #"!ess"s

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    HISTORY

    In the eal$ 1%70&s the 'ist Mi!"#"!ess" (as de)el"#ed *$

    Intel+

    It (as a , *it ma!hine that (as named the ,00,

    he ,00, (as '"ll"(ed *$ Intel&s .00. and .0.0/ as (ell asm"t""la&s 6.00 and 6.000

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    CHANGES TIME TO

    TIME

    ith ea!h ne( eneati"n "' #"!ess"s thee (ee se)eal

    de)el"#ments su!h as

    Smalle sizeaste

    In!eased heat dissi#ati"n

    4eate C"nsum#ti"n "' #"(e

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    SINGLE CORE

    PERFORMANCE

    n te!hniue used t" in!ease sinle !"e #e'"man!e (as

    Pi#elinin *einnin "the (aitin instu!ti"ns *e'"e the

    'ist 'inishes

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    SINGLE CORE

    CONTINUED

    An"the te!hniue (as multitheadin

    Multitheadin in)"l)es ee!uti"n "' t(" se#aate

    theads+

    ime is di)ided and intela!ed *et(een the t("

    theads in "de t" simulate simultane"us

    ee!uti"n

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    PROBLEMS WITH

    SINGLE CORE

    " ee!ute the tas8s 'aste $"u must in!ease the !l"!8 time+

    In!easin !l"!8 times t"" hih dasti!all$ in!eases #"(e

    !"nsum#ti"n and heat dissi#ati"n t" etemel$ hih le)els/ma8in the #"!ess" ine''i!ient+

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    MULTI CORE

    Ceatin t(" !"es " m"e "n the sametime/ in!eases #"!essin #"(e (hile8ee#in !l"!8 s#eeds at an e''i!ient le)el+

    A #"!ess" (ith 2 !"es unnin ate''i!ient !l"!8 s#eeds !an #"!ess

    instu!ti"ns (ith simila s#eed t" a sinle!"e #"!ess" unnin at t(i!e the !l"!8s#eed/ $et the dual !"e #"!ess" ("uldstill !"nsume less ene$+

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    MODEL OF MULTI

    CORE

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    IMPLEMENTATIONS

    (" main (a$s t" ha)e multi#le !"es intea!t ae theshaed mem"$ m"del/ and the disti*uted mem"$m"del+

    In the shaed mem"$ m"del/

    all !"es shae the same !a!he

    mem"$+

    In the disti*uted mem"$ m"del/

    ea!h !"e has its "(n !a!he

    mem"$+

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    WHAT IS CACHE AND

    SYSTEM BUS

    A CPU !a!he is a !a!he used *$ the !ental #"!essin unit9CPU: "' a !"m#ute t" edu!e the a)eae time t" a!!ess data

    '"m the main mem"$+ he !a!he is a smalle/ 'aste mem"$(hi!h st"es !"#ies "' the data '"m 'euentl$ used mainmem"$ l"!ati"ns

    A s$stem *us is a sinle !"m#ute *us that !"nne!ts the maj"!"m#"nents "' a !"m#ute s$stem+ he te!hniue (as

    de)el"#ed t" edu!e !"sts and im#")e m"dulait$+ It !"m*inesthe 'un!ti"ns "' a data *us t" !a$ in'"mati"n/ an addess *ust" detemine (hee it sh"uld *e sent/ and a !"nt"l *us t"detemine its

    "#eati"n

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    EXAMPLE OF MULTI-

    CORE

    he Intel !"e du" desin

    has a se#aate ;1 !a!he

    mem"$ '" ea!h !"e/ *ut

    *"th !"es shae an ;2

    !a!he+

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    EXAMPLE OF MULTI-

    CORE

    he AM< Athl"n 6, =2

    im#lementati"n has

    se#aate ;1 and ;2

    !a!he mem"$ '" ea!h

    !"e+

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    MULTI-CORE

    ADVANTAGES

    >a)in multi !"es *e the same ma8es #"du!ti"n easie and

    8ee#s instu!ti"n !"m#leit$ t" a minimum+

    >a)in di''eent !"es that ae s#e!ialized in s#e!i'i! tas8sin!eases !"m#leit$ *ut has the #"tential t" *e mu!h m"e

    e''i!ient in s#eed and #"(e !"nsum#ti"n+

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    MULTI-CORE

    ADVANTAGES

    hile ("8in (ith man$ theads/ a Multi C"e #"!ess"

    (ith n !"es !an ee!ute n theads simultane"usl$ *$

    assinin a !"e t" ea!h thead+

    A Sinle !"e #"!ess" must multithead (ith e)e$ sinle

    thead+

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