Instruction Set Architecture What is an instruction set? Portion of the machine visible to the programmer or compiler writer Each instruction is directly executed by hardware Examples DEC VAX INTEL IA-32 H and P DLX MIPS, Power PC, SPARC ARM Instruction Set Principles Chapter 2 in both 2 nd and 3 rd edition
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Instruction Set Architecture
� What is an instruction set?�Portion of the machine visible to the programmer or
compiler writer�Each instruction is directly executed by hardware
� Examples�DEC VAX
�INTEL IA-32
�H and P DLX
�MIPS, Power PC, SPARC
�ARM
Instruction Set Principles
� Chapter 2 in both 2nd and 3rd edition
operand
Instruction Set Architecture
� How are they represented?�By bits
�Typically 16, 32, 64
� Variable or Fixed�Fixed – each instruction is same size
What you see What the machine sees
Add A,B
op-code operand
Application Areas
� Desktop computing� Code size not important
� Integer and floating-point performance is important
� Servers� Floating-point not important
� Integer performance is important
� Embedded applications� Value cost and power efficiency is important
� Code size is important
� Multimedia and DSP applications� Real time constraints
� Power efficient
Classifying Instruction Sets
� Type of internal CPU storage�Stack – operands are implicit
�Accumulator – one operand is implicit
�General purpose registers – explicit operands
Classifying Instruction Sets
� Where are the operands?�Accumulator, Stack, registers, memory
� Advantages� Data access immediate without loading� Instruction format simple� Instruction density higher than (0,3) model� Note: instruction density better use of bits
� Disadvantages� Source may be destroyed� Need for memory address may limit the number of registers� CPI will vary depending on type of operands
Memory Addressing
� How is the memory address interpreted?
� Byte addressed
� Byte order�Big Endian vs. Little Endian
� Alignment�An object of size s bytes at byte address A is aligned if
A mod s = 0
� Addressing modes
Memory-Memory (3,3)
� Advantages�Best instruction density
�Doesn’t waste registers for temporary results
� Disadvantages�Large variation in instruction size (3 operand
instructions)�Large variation in CPI
�Can worsen memory bottleneck
� Most complex model – currently extinct� VAX
Interpreting Addresses
• Memory is just a bunch of bits.• How big can the address be?
32-Bit addressing
Address Memory
Interpreting Addresses
• Memory is just a bunch of bits.• How do we address it?
Byte addressing
Address Memory
Byte Ordering
Interpreting Addresses
• What is the length of the thing we are addressing?
•Typical lengths: byte 8, half-word16, word 32, double word 64
Word addressing
Address Memory
Alignment
� For a byte addressed machine�all byte accesses are aligned
�word accesses are aligned if the address is a multiple of 4
�32-bit integer accesses are aligned if the address is a multiple of 4
�64-bit floating point accesses are aligned if the address is a multiple of 8
Alignment
�An object of size s bytes at byte address A is aligned ifA mod s = 0
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
Accessing this word is a misaligned access.
Misalignment may cause slow performance
Addressing Modes – DataMode Example Meaning When used
Register Add R4,R3 R[4]=R[4]+R[3] When a value is in a register
Immediate Add R4,#3 R[4]=R[4]+3 For constants
Displacement Add R4,100(R1) R[4]=R[4]+M[100+R[1]] Accessing local variables
Register Add R4,(R1) R[4]=R[4]+M[R[1]] Accessing Deferred or pointer Indirect