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24.422 - Switching Theory - B. Rahardjo - v. 0.4.0 1

24.422Switching Theory

Budi Rahardjo

TRLabs or

U of M - Room 511A Eng. Bldg.Electrical and Computer EngineeringUniversity of Manitoba

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Topics

z Review of Digital Logic

z Boolean Functions and Logic Minimization

z Sequential Circuits

z Asynchronous Circuits

z Fault, Testing, Verification

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Format & Grading

z Lectures

z Assignments (4) and Labs (5) -(25%)

z Mid Term (25%)

z Final (50%)

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Textbooks and References

z No textbook, but some recommendedreferences will be available in the Reservesection in Eng. Library. There are twofolders in library:1. Course notes2. References (reading materials)

z Course notes will be available online (WWW)

http://www.ee.umanitoba.ca/~rahard/24.422z Some references that can be used (when they are being used,

they will be announced)

R. K. Brayton, G. D. Hachtel, C. T. McMullen, A. L.Sangiovanni-Vincentelli, Logic Minimization Algorithmsfor VLSI Synthesis, Kluwer Academic Publishers.

J. Bell and M. Machover, A Course in MathematicalLogic, North-Holland.

Frederick J. Hill and Gerald R. Peterson, Introduction to

Switching Theory & Logical Design, John Wiley & Sons,Inc.

Zvi Kohavi, Switching and Finite Automata Theory,McGraw-Hill, 1978.

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Review of Digital LogicBasic Definitions

z Truth values: TRUE, FALSE

z

Meaning/implementation: open, closeswitch or close,open switch, 5V,0V or 0V, 5V

z Boolean values: {0,1}{0,1,X}, {0,1,2} where X or 2 is usuallyused to indicate dont care values

z Boolean functions.A logic (Boolean, switching) function finn

input variables, x1, ..., xn, andm output

variables, y1, ..., ym, is a function

f: BnYm

Symbol f is used to describe incompletelyspecified logic functions.

A completely specified function f is a logicfunction taking values in {0,1}m, I.e. allvalues of the input map into 0 or 1 for all the

components of f.

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Review (continued)

z On-set XiON

the set of input values x such that

fi (x) = 1

z Off-set XiOFF

the set of input values x such thatfi (x) = 0

z Dont care set XiDC

the set of input values x such thatfi (x) = 2

z Reference: for more info seeR. K. Brayton, et al., Logic Minimization Algorithms for VLSISynthesis, Kluwer Academic Publishers.

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Review (continued)

z Truth-table

x1 x2 x3 y1 y20 0 0 1 10 0 1 1 00 1 0 0 10 1 1 0 11 0 0 1 01 0 1 1 2

1 1 0 1 11 1 1 2 1

z For y1, the ON, OFF, and DC sets are

z X1ON={ [0,0,0], [0,0,1], [1,0,0], [1,0,1], [1,1,0] }

z X1OFF

= { [0,1,0], [0,1,1] }z X1

DC={ [1,1,1] }

z Compose the ON, OFF, and DC sets for y2

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Geometrical Representationusing Boolean n-cubes

z The tabular representation (truth-table) canbe mapped into a geometrical

representation by making use of Boolean n-cubes.

z See Figure 2.1 (page 17) of Braytons book.

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Cubes and cover

z

A cube can be specified by its vertices and by an indexindicating to which component of function fit belongs. Theinformation can be given in a compact form.

z Letp be a product term associated with an algebraic sum-of-product expression of a logic function withn inputs andmoutputs. Then a cube ofp is specified by a row vector

c = [c1,, cn, cn+1, , cn+m]

whereci = 0 if xi appears complemented in p

1 if xi appears not complemented in p

2 if xi does not appear in p(i = 1, , n)

3 ifp is not present in the algebraic representationoffi-n (i=n+1, , n+m)

4 ifp is present in the algebraic representationiffi-n

z Example:f1 = x2 + x1 x3f2 = x2 + x1 x3For p = x2, c = [2 0 2 4 3]I(c) = [2 0 2] O(c) = [4 3]

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Cubes and cover (continued)

z

A set of cubes C = {c1, c2, , ck} is said to be a cover for alogic funtionf with n inputs and m outputs, if, for j=1, , mthe set of input parts of the cubes that have a 4 in the j th

position contain all vertices corresponding to the on-set offjand none of the vertices of the off-set offj, i.e., a coverrepresents the union of the on-set and some arbitrary portionof the dont care-set.

z The matrix M(C) associated with a cover C = {c1, , ck} is thematrix obtained by stacking the row vectors representing eachof the cubes.

z

Example:

2 0 2 4 3F = M(C) = 1 2 0 4 3

2 1 2 3 40 2 0 3 4

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Review (continued)z Boolean Algebra

(of a set element S = {0,1} and operators +, *,and ). AXIOMS:

Commutativex + y = y + xx * y = y * x

Distributivex * (y + z) = (x * y) + (x * z)x + (y * z) = (x + y) * (x + z)

Neutral Element Existsx + 0 = x

x * 1 = x Inverse Element Exists / Complementary

x + x = 1x * x = 0

There exist at least two elements x,y in Ssuch thatx does not equaly

If elements x andy are members of the set S,

then elements x * y and x + y are alsomembers of S

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Review (continued)

z DeMorgans theorem

(x + y) = x y

(xy) = x + y

z Notation

Negation: , horizontal bar, or e.g. x, x, x

Implication: e.g.x yThis formula will be false iff x is true but

y is false. Whenever x is false, x yshould be regarded as (vacuously) true,irrespective of the truth value of y

Create the truth table for Implication!

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Design Process

z Specification: a description of what the design must dowithout describing how to achieve that. Could be in English orby using formal notations.

z Synthesis: automatic generation of implementations

z Implementation: has a lower abstraction compared tospecification

z Translation: from an implementation to anotherimplementation such as when doing optimization,minimization

z Verification: Show that the implementation meets(satisfies) the specification

z Validation: show that the implementation is what the userwants (e.g. with simulation, testing)

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Implementations

z Full Custom VLSI

flexible, but expensive and time consuming

z Gate Array programming/personalizing an array of uncommitted

gates using a set of interconnections. Design isconstrained by the fixed structure, limited routing

z Standard Cells

Design/circuit is implemented with a standard cell/unit.More flexible than gate array but longer development time

z Macro Cells

somewhere between gate array and standard cells. e.g.PLA

z ROM

easy to program butn-input requires2n memory cells

n-inputs form an address into the memory

m-outputs are the data contained in that address

most combinational logic functions require only a smallfraction of all 2n product minterms. Thus, may waste area

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PLA Example

z PLA implementation of

**1**0 1000

*1*0** 0100

1****0 0001

1***1* 0100

0***** 0010

*****1 0001

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Logic Minimization

z The goal is to have faster, smaller, andhigher yielddesigns. Function is preserved.

z Original functions must be preserved

z Optimizationmay be a better term since aminimized size (area) may not be the bestimplementation in terms of speed and cost.

z The objective of a minimizer is to find alogic representation with a minimal number

of implicants and literalswhile preservingthe functionality.

z Minimization using discrete off-the-shelflogic gates was not a big problem, butbecame a problem in VLSI designs whichoften involve logic functions with more

than 30 inputs and 100 product terms

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Logic Minimization

z Two-level logic minimization seeks a logicrepresentation with a minimal number of

implicants and literals.z Less implicants, smaller implementation

(e.g. PLA) area.

z Less number of literals, less number ofdevices and less number of contactsrequired.

z The number of prime implicants of a logicfunction with ninput variables can be aslarge as 3n/nThis is impractical even for medium sizedproblems (10-15 variables).

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Logic Minimization

z Function Simplification

z Karnaugh-map

z Quine-McCluskeyE. J. McCluskey, Minimization of Boolean Functions, In Bell Lab.Technical Journal, Vol. 35, pp. 1417-1444. Bell Lab., November1956.

z MINI, two-level logic minimizer developed atIBMS. J. Hong, R. G. Cain, and D. L. Ostapko, MINI: A heuristic

approach for logic minimization, IBM. J. of Res. And Dev. Vol. 18,pp. 443-458, September 1974.

z PRESTO, SPAM, SHRINK

z ESPRESSOR. K. Brayton, G,D. Hatchel, C. T. McMullen, A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSISynthesis, Kluwer Academic Publishers.

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Function Simplification

z Algebra is used to simplify functions byeliminating terms, combining terms, and

eliminating literals in terms.z Literals: any variable or its complement

z Example: Simplifyxy + xz + yz= xy + xz + yz (x + x)= xy + xz +xyz + xyz

= xy (1+z) + xz (1+y)= xy (1) + xz (1)= xy + xz

z Draw the original and minimized circuits,youll see that a gate (which represents yz)can be eliminated

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Logic minimization withKarnaugh map

z K-map: pictorial representation with visualinspection (+ human pattern recognition)

z Good for a small number of literals (< 6)

z adjacent cells differ in one bit

z entries are from expansion of function intominterms (product terms which contain all xi)

z implicant: a rectangle of 1s

z prime implicants: rectangle that has been made

as large as possible (maximum area)z z = x2 x4 + x1 x3

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Logic minimization withQuine - McCluskey

z Review

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Logic Minimization withEspresso

z References (Bryants book)

z Lab

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Circuit Equivalences -Preserving Functionality

z To check whether a design implementationor revision is functionally equivalent to the

golden versionz Important in Synthesis

z New area: Formal Verification (also FormalEquivalence Checking)

z It is predicted than in 1997 there will be more formal tools.Examples: Design VERIFYer from Chrysalis Symbolic DesignInc.

z

Example papers:

S. Clayton, J. Sweeney, M. Tetreault, & Scott Sandler, ASet of Formal Applications, Integrated System Design,November 1996.

z Gate Equivalences (Example:NAND may be replacedwith an AND and an INVERTER)

z

This may be useful in situations whereby implementations are

restricted to certain types of gates, blocks, modules, orpackages

z Example: implement by using NAND gates

z = x1 x2 x3 + x4 x5

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Circuit Equivalences

z Another example: AND gate is replaced by NOR andbubbles

z

Circuit equivalence: Proof with Boolean Algebra, truthtable, canonical sum-of-product, propositional

tableaux, HOL, BDD. Some of these techniques areuseful for small circuits only.

z ReferencesB. Rahardjo, Hardware Equivalences, UMECE TR-95-002,Technical Report, 1995.

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Gate Equivalences

z NAND may be replaced by AND & INVERTER

z Use Boolean Algebra and De Morgans theorem

to rewrite equationsz This technique is only useful in certain cases

(gate level)

z EXAMPLE:AND gate may be replaced by a NOR with twobubles at the input ports.

Show equivalency the truth table.

Show with Boolean Algebra

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Circuit Equivalence: Proofwith propositional tableaux

z Tautology:f 1

z Reference:J. Bell and M. Machover, A Course in Mathematical Logic,North-Holland.

z A tableaux is a collection of elements callednodes, partially ordered and classified intolevels

z Each node is associated with a finite set of

formulasz Each node my have successor(s)

z If it has no successors, it is called aterminal node

z A tableaux can be extended by applyingrules. For example, if at nodex there is a

formulaa b, then we add two nodes {a}and {b} as successors tox.

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Propositional Tableaux

z Rules: Rule : If among the formulas of a branch of Tterminating

node there is a formula , add a new node {} assuccessor to .

|

Rule : If among the formulas of a branch of Tterminatingnode there is a formula , add two new nodes {} and{} as successors to .

Rule : If among the formulas of a branch of Tterminatingnode there is a formula (), a new node {, } assuccessor to .

()

|

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More Rulessee page 28 of Bell & Machovers book

z -rule

z -rule

z -rule

z -rule

z -rule

z -rule

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Propositional Tableaux

z A branch is closed if there is a primeformulaa such that botha and a are in that

branch.z A tableau is called a confutation if all its

branches are closedA branch is closed ifthere is a prime formulaa such that bothaand a are in that branch.

z A tableau is called a confutation if all its

branches are closed.z To show a tautology is to find a confutation

of its negated formula.

z Example:

[ () () () ]

From Hardware Equivalences paper:~(a/\b ==> ~(~a\/~b)) /\ (~(~a\/~b)==>a/\b)

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Proving two circuits areequivalence with HOL

z Reference:M. J. C. Gordon and T. F. Melham, Introduction to HOL: Atheorem proving environment for higher order logic,Cambridge University Press.

z Brief introduction to HOL Theorem proving environment: (1) for directly

proving theorems, (2) as embedded theoremproving support for application-specific

verification systems.

ML programming language

Free, needs Lisp to compile

Others theorem provers: Isabelle, PVS

z Example of proving two circuits areequivalent

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Binary Decision Diagrams

(BDDs)

z Reference R. E. Bryant, Graph-Based Algorithms for Boolean

Function Manipulation, IEEE Trans. On Computers, vol.

C-35, No. 8, pp. 677-691, 1986.z Methods for representing and manipulating

Boolean functions:

Truth tables

Karnaugh maps

Canonical sum-of-products form

z They are impractical: every function ofnarguments has a representation of size2n

or more.

z Boolean operations (e.g. complementations,satisfiability) could yield a function with anexponential representation

z None of those representations arecanonical form

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BDD - Continued

z BDD notation was introduced by Lee andpopularized by Akers. Bryant put restrictionon the ordering of the decision variables:

Ordered BDD (OBDD)z OBDDs provide compact and canonical

representation of Boolean functions. Morecompact than traditional normal forms.

z Bryant provides efficient algorithms tomanipulate BDDs: the time complexity of any

single operation is bounded by the product of thegraph sizes for the functions being operated on.e.g.Complementing requires time proportional to the size of thegraph.Combining two functions with a binary operation requires atmost time proportional to the product of the graph sizes.

z Since OBDD is canonical,

testing for equivalence becomes testing whether thetwo graphs match exactly,testing for satisfiability becomes comparing the graphto constant function 0

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OBDD - Continued

Common functions have reasonablerepresentations

Performance degrades slowly

Complexity is bounded by the product ofgraph sizes

Reduced graph has canonical form

Sensitive to orderingsome understanding to the problem can yieldappropriate ordering, except for integermultiplier

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BDD - Continued

z Applications of BDDs

Minimization

Synthesis

Logic design verification

Test pattern generation

Combinatorics

z Example of BDD

(just to give an idea what we are going to deal with)

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Binary Decision TreesAdapted from E. M. Clarke (CMU) tutorial on Symbolic Model Checking @FORTE95

z To start the discussion, lets considerBinaryDecision Trees

z A binary decision tree is a rooted, directed treewith two types of vertices: terminaland non-terminalvertices

z Each non terminal vertex v is labeled by avariable var(v) (or in some implementations iscalled index(v) ) and has two successors:

low(v) corresponding to the case where thevariable v is assigned 0

high(v) corresponding to the case wherethe variable v is assigned 1

z Each terminal vertex v is labeled by value(v)

which is either 0 or 1

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Binary Decision Trees (Cont.)Adapted from E. M. Clarke (CMU) tutorial on Symbolic Model Checking @FORTE95

z A binary decision tree for a two-bit comparator,given by the formula

f(a1, a2, b1, b2) = (a1b1) (a2b2)

is shown below

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Binary Decision Trees (Cont.)Adapted from E. M. Clarke (CMU) tutorial on Symbolic Model Checking @FORTE95

z We can decide if a truth assignment satisfiesthe formula as follows:

Traverse the tree from the root to a terminalvertex

If a variable v is assigned 0, the next vertexon the path will be low(v)

If a variable v is assigned 1, the next vertexon the path will be high(v)

The value that labels the terminal vertexwill be the value of the function for thisassignment

z In the comparator example, the assignment

(a11, a2 0, b1 1, b2 1)

leads to a leaf vertex labeled 0, so the formulais false for this assignment.

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Binary Decision Trees to

Binary Decision DiagramAdapted from E. M. Clarke (CMU) tutorial on Symbolic Model Checking @

FORTE95

z Binary decision tress do not provide a veryconcise representation for Boolean functions.

z But, there is usually a lot of redundancy insuch trees.

z In the comparator example, there are eight subtrees with roots labeled b2, but only three aredistinct.

z We can obtain a more concise representation

by merging isomorphic sub-trees.

z The result is a directed acyclic graph (DAG)called a Binary Decision Diagram.

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BDD

z Notation

function withn argumentsx1, , xn choose some ordering

z Cofactor

f|xi=b(x1, , xn) =f(x1, , xi-1, b, xi+1, , xn)

z Shannon expansion: a function aroundxif=xi f|xi=1

+ xi f|xi=0z

Compositionf|xi=g(x1,,xn) =f(x1,,xi-1,g(x1,,xn),xi+1,,xn)

z Dependence set of functionf

If= {i |fxi=0fxi=1

} (i.e. f depends on xi)

z Satisfying set of function f

Sf= {(x1,,xn) |f(x1,,xn) = 1}

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Binary Decision DiagramAdapted from E. M. Clarke (CMU) tutorial on Symbolic Model Checking @FORTE95

z A Binary Decision Diagram is a rooted,directed acyclic graph with two types of

vertices, terminal vertices and non-terminalvertices.

z Each non-terminal vertex v is labeled by avariable var(v) and has two successors, low(v)and high(v).

z Each terminal vertex is labeled by either 0 or 1.

z A binary decision diagram with root vdetermines a boolean functionfv(x1, , xn) in

the following manner:

If v is a terminal vertex:(a) If value(v) = 1 thenfv(x1, , xn) = 1(b) If value(v) = 0 thenfv(x1, , xn) =0

If v is non-terminal vertex with var(v)=xithenfv(x1, , xn) is given byxi flow(v)(x1, , xn) +xi fhigh(v)(x1, , xn)

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Canonical Form PropertyAdapted from E. M. Clarke (CMU) tutorial on Symbolic Model Checking @FORTE95

z In practical applications, it is desirable to havea canonical representationfor Boolean

functions.z This simplifies tasks like checking equivalence

of two formulas and deciding if a given formulais satisfiable or not

z Such a representation must guarantee that twoBoolean functions are logically equivalen if and

only if they have isomorphic representations.

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Canonical Form PropertyAdapted from E. M. Clarke (CMU) tutorial on Symbolic Model Checking @FORTE95

z Two binary decision diagrams are isomorphic ifthere exists a bijection h between the graphs

such thatz terminals are mapped to terminals and non-

terminal are mapped to non-terminals,

z for every terminal vertex v,value(v) = value(h(v)) , and

z for every non-terminal vertex v:var(v) = var(h(v))

h(low(v)) = low(h(v))

h(high(v)) = high(h(v))

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Canonical Property (Cont.)

Bryant showed how to obtain a canonicalrepresentation for Boolean functions by placing

two restrictions on binary decision diagrams: First, the variables should appear in the same order along

each path from the root to a terminal

Second, there should be no isomorphic subtrees or

redundant vertices in the diagram

The first requirement is easy to achievez We impose total ordering < on the variables in the formula

z We require that if vertex u has a non-terminal successor v,then var(u) < var(v)

The second requirement is achieved byrepeatedly applying three transformation rulesthat do not alter the function represented bythe diagram

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Reduction Rules

z Remove duplicate terminals: Eliminate all butone terminal vertex with a given label and redirect all arcs

to the eleminated vertices to the remaining one.z Remove duplicate non-terminals: If non-

terminals u and v have:var(u) = var(v)low(u) = low(v)high(u) = high(v)

then eliminate one of the two vertices and redirect allincoming arcs to the other vertex.

z Remove redundant tests: If non-terminal vertex vhas low(v) = high(v), then eliminate v and redirect allincoming arcs to low(v)

The canonical form may be obtained by applying thesetransformation rules until the size of the diagram

can no longer be reduced.

Bryant shows how to achieve this in linear time.

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Ordered Binary DecisionDiagrams (OBDDs)

The term Ordered Binary Decision Diagram(OBDD) will be used to refer to the graph

obtained in this mannerIf OBDDs are used as a canonical form for

Boolean functions, then

checking equivalence is reduced tochecking isomorphism between OBDDs

satisfiability can be determined by checking

equivalence with the trivial OBDD thatconsists of only one terminal labeled 0.

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OBDD for Comparator

z If we use the ordering a1 < b1 < a2 < b2 for thecomparator function, we obtain the OBDD

belowz figure

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Variable Ordering

The size of an OBDD depends critically on thevariable ordering.

If we use the ordering a1 < a2 < b1 < b2 for thecomparator function, we get the OBDD below

figure

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Variable Ordering forComparator

For an n-bit comparator:

z if we use the ordering a1 < b1 < an < bn, the

number of vertices will be 3n+2.

z if we use the ordering a1 < < an < b1 < bn

the number of vertices is 3 . 2n-1.

In general, finding an optimal ordering is known tobe NP-complete. Moreover, there are Booleanfunctions that have exponential size OBDDs

for any variable ordering. An example is themiddle output (nth output) of a combinational

circuit of an integer multiplier, which multipliestwo n bit integers.

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Heuristics for variableordering

z Heuristics have been developed for finding agood variable ordering when such an ordering

exists.z The intuition for these heuristics comes from

the observation that OBDDs tend to be smallwhen related variables are close together inthe ordering. In our example, a1 and b1 arecloser than a1 and a2.

z The variables appearing in a subcircuit arerelated in that they determine the subcircuitsoutput. Hence, these variables should usuallybe grouped together in the ordering.

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Examples / Properties

z The function which yields the value of the ithargument is denoted by a graph with a single

non-terminal vertex having index I and havingas low child a terminal vertex with value 0 andas high child a terminal with value 1.

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Examples

z The odd parity function of n variable is denoted by a graphcontaining 2n+1 vertices. This is better than reduced sum-

of-product form, which requires 2n terms.

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Example

z a1 . b1 + a2 . b2 + a3 . b3

a1 < b1 < a2 < b2 < a3 < b3

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Different Ordering

z a1 . b1 + a2 . b2 + a3 . b3

a1 < a2 < a3 < b1 < b2 < b3

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ExampleR. E. Bryant, Symbolic Boolean Manipulation with Ordered BinaryDecision Diagrams, Technical report, CMU-CS-92-160, 1992.

z x1 x2 x3 f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

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Example

z Reducing OBDD

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Operation (recap)

z Reduction (inductive method)

id(low(v)) = id(high(v))

id(v) = id(low(v)) (v is redundant)

vertex u with index(u) = I

id(low(v)) = id(low(u))

id(high(v)) = id(high(v))

id(v) = id(u)

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Operation: Restriction

z Restriction or Cofactor. We begin with thefunction that restricts some argument xi of the

Boolean function f to constant value b.z This function is denoted byf|xib

and satisfiesthe identity

f|xi=b(x1, , xn) =f(x1, , xi-1, b, xi+1, , xn)

z If f is represented as an OBDD, the OBDD for

the restrictionf|xibis computed by a depth-

first traversal of the OBDD.z For any vertex v which has a pointer to a

vertex w such that var(w) = xi, we replace thepointer by low(w) if b is 0 and high(w) if b is 1.

z When the graph is not in canonical form, we

apply Reduce to obtain the OBDD forf|xib

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Logical Operations

z All two-argument logical operations can beimplemented efficiently on Boolean functions

that are represented as OBDDs.z The complexity of these operations is linear in

the size of the argument of OBDDs.

z The key idea for efficient implementation ofthese operations is the Shannon expansion

f = x . f|x 0 + x . f|x 1

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Logical Operations

z Bryant gives a uniform algorithm called Applyfor computing all logical operations.

z Let * be an arbitrary two argument logicaloperation, and letfandf be two Booleanfunctions.

z To simplify the explanation of the algorithm, weintroduce the following notation:

v and v are roots of the OBDDs for fandf

x = var(v) andx = var(v)

z We consider several cases depending on therelationship betweenv and v

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Logical Operations OBDDs

z If v and v are both terminal vertices, thenf * f = value(v) * value(v)

z Ifx = x, then we use the Shanon expansionf * f = x . (f|x 0 * f|x 0) +x . (f|x 1 * f|x 1)

to break the problem into two subproblems.The subproblems are solved recursively.

z

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