240-334 by Wannarat 240-334 Computer System Design Lecture 2 Instruction Set Architecture.

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-240334

Computer Syste m Design 2Lecture

Instruction Set Architecture

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What’re the co mponent of ISA

?Machine Instruction SetInstruction formatNature of the fetch through execute

wannarat:

machine instruction set :make use of storage cells, formats, and result of fetch/execute , register transfer

instruction format : size and meaning of field within instruction

the nature of the fetch-execute cycle : things that are done before the operation code is known.

wannarat:

machine instruction set :make use of storage cells, formats, and result of fetch/execute , register transfer

instruction format : size and meaning of field within instruction

the nature of the fetch-execute cycle : things that are done before the operation code is known.

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Vari es Programm i ngModel

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What must an inst ruction specify?

Which Operation is perform?

ADD r1,r2,r3Where to find the operands

ADD r1,r2,r3Place to store the result

ADD r1,r2,r3Location of next instruction

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Basic ISA Class Accumulator (1 register)

1 address add A; acc <= acc + mem[A]

1 + x address addx A; acc <= acc + mem[A+x] Stack :

0 address add tos <= tos + next General Purpose Register

2 address add A, B

3 address add A, B, C

wannarat:

add A, B ; A = A + B

add A B C; A = B + C

wannarat:

add A, B ; A = A + B

add A B C; A = B + C

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Basic ISA Classes(con’t) Load/Store

load Ra, RbRa <= mem[Rb]

Store Ra, Rb mem[Rb] <= Ra

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Compare numb er of instruction

Code Sequence for C = A + B

Stack Accumulator Register Register

(reg. - mem) (load/store)

Push A Load A Load R1,A Load R1,A

Push B Add B Add R1,B Load R2,B

Add Store C Store C, R1 Add R3,R1,R2

Pop C Store C,R3

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CPU RegisterStack Register Arithmetic Register &

Address Register

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General PurposeRegi ster 1975 - 1995 all machines use general purpose re

gisters. Advanced of Registers

- faster than memory

- easier for compiler to use

- hold variables

wannarat:

easier for compiler to use : (A*B) - (C*D) - (E*F) can do multiplies in any order vs. stack

hold variables: memory traffic is reduced (program speed up), code density improves ( register named with fewer bits than memory location)

wannarat:

easier for compiler to use : (A*B) - (C*D) - (E*F) can do multiplies in any order vs. stack

hold variables: memory traffic is reduced (program speed up), code density improves ( register named with fewer bits than memory location)

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Summary Instru ction Set Class

Data Movement Instructions

- Load

- Store Arithmetic and Logic (ALU) Instruction

- Add, Sub, Shift … Branch Instructions

- Br, Brz, …

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- 3 Address Mac hine and ISA

wannarat:

Address of next instruction kept in Proces sor state register (PC)

wannarat:

Address of next instruction kept in Proces sor state register (PC)

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- 2 Address Mac hine ISA

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- 1 Address Mach ine and ISA

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- 0 Address Machi neandI SA

wannarat:

- Push down stack in CPU,

Arithmetic uses stack for both operands and result,

- Computer must have 1 address instructi on to push and pop operands to and fro

m the stack

wannarat:

- Push down stack in CPU,

Arithmetic uses stack for both operands and result,

- Computer must have 1 address instructi on to push and pop operands to and fro

m the stack

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EEEEEEEE - *a = (b+c) d e

-3 address -2 address -1 address EEEEE ,, load a,b load b push b ,, add a,c EEE E push c

sub a,a,e mpy a,d mpy d EEE sub a,e sub e push d

store a mpy push e sub pop a

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Real Machi ne Have mixture of 3, 2, 1 or 0 address instructions if ALU instructions only use registers for operan

ds and result, machine type is load-store mix of register-memory and memory-memory

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Break 5 Minutes

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Addressing ModE

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Addressing ModE

Addressing Mode Examples MeaningRegister Add r4,r3 r4 <= r4 + r3Immediate Add r4,#3 r4 <= r4 + 3

Displacement Add r4,100(r1) r4 <= r4 + mem[100+r1]indirect(r) Add r4,(r1) r4 <= r4 + mem[r1]

index+base Add r3,(r1+r2) r3 <= r3 + mem[r1+r2]Direct Add r1,(1001) r1 <= r1 + mem[1001]

indirect(m) Add r1,@(r3) r1 <= r1 + mem[mem[r3]]-auto incre Add r1,(r2)+ r1 <= r1+mem[r2];r2=r2+d-auto decre -Add r1, (r2) -r2 <=r2 d,r1<=r1+mem[r2]

scaled Add r1,100(r2)[r3] r1 <=r1+mem[100+r2+r3*d]

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MIPS Registers - 3132 0 0x bitGPR(R= ) - 32 32x bit FP registerPC EE EE-EEEEEEEEEE EEEEEE EEEEEEEE0R1R

31R

PC

lohi

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Memory AddresEEEE EEEEEEE EE EEEEE EE E-EEEE EEEEEE1980, 8()

How do byte address map onto words? Can a word be placed on any byte boundary?

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Endianess andAlignment EE EE:68, , , :8086,(, )

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Generic of Instruct ion format width

Variable :

Fixed:

Hybrid:

...

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Summary ISA Variable length instructions, if code

size is very important. Fixed length instructions, if perform

ance is most important. Embedded Machine (ARM, MIPS) hav

-e optional mode to execute 16 bitwide.

(decide performance or density)

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To be Continuous

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Part II : Lecture2

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MIPS ISA Target Embedded System EEEEEEEEE EEEEEEE EEEEEEEEE EEEE,,,

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MIPS ISA

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MIPS AddressinE E EEEE - All instructions have 32 bit wide.

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MIPS ArithmeticInstructionInstruction Exampl e Meaning1 .add 1 2 3add $ ,$ ,$ 1 2 3$ = $ + $2.subtract sub $1,$2,$3 ------------------

3.add imme addi $1,$2,100 ------------------ 4.add unsign 1 2 3addu $ ,$ ,$ ------------------

5. 123subu $ ,$ ,$ ------------------6. -----------------1 2100addiu $ ,$ ,7.multiply EEEE 2 3$ ,$

2 3Hi,Lo = $ x$8. multu $2,$3 ------------------

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MIPS ArithmeticInstructionInstruction Example Meani ng9.divide 2 3 =2/3 ,

=2 3 ,10. 2 3Divu $ ,$11.mov mfhi $112. mflo $1

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MIPS Logical InstructionInstruction Example Meani ng13.AND and14.OR or15.XOR xor16.NOR nor17. andi18. ori19. xori

20.shift left logical sll $1 ,$2 ,1 021. 1 210Srl $ ,$ ,

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MIPS Logical InstructionInstruction Example Meani ng

22 210.shift rightarithmsra $,$ , EEEEE EEEEEEE23. sl l v24. srl v25. srav

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MIPS data transEEE EEEEEEEEEEEE

26. 50043sw (r),r EEEEE EEEE27. 502 4 3sh (r ),r

store half word 28. 41 4 3sb (r ,r store byte

29. 1,30(2) load word30. 1,40(2) load half word31. 140 2Lb r , (r ) load byte32 140lui r , load upper

16 16immediate ( bits shifted left by )

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EEEEEEE EEEEEEEEE Condition Code

EEE 1 2 3r ,r ,rbz label

Condition RegisterEEE 1 2 3r ,r ,rEEE 1r ,label

Compare and BranchEEE 1 2r ,r ,label

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MIPS Compare a nd Branch

Compare and BranchBEQ rs,rt,offsetBNE rs,rt,offset compare to zero and BranchBLEZ rs, offsetBGTZ rs, offsetBLT <BGEZ >=BLTZAL if R[rs] < 0 then branch and link(to R31)

BGEZAL >=

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MIPS Jump, Bra nch Compare

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Software convent ions for Register

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EEEE EEE EEEE EE structi onSet

0 0R always = “ ” (even if u try to write) / EEE EEEE -+ 4 > 3 1 Imme arith and logical are extended

- EE EEE EEEE EEEEEE EE EE EEEE3 2- arith imme op are sign extend to 32 bits

data loaded by lb, lh extended- lbu, lhu are zero extended- lb, lh are sign extedned

Overflow occur in ADD, SUB, ADDI EEEEE EE ’ ADDU, SUBU, ADDIU, AND, OR, XOR, N

OR, SHIFT, MULT, MULTU, DIV, DIVU

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MIPS arithmetic 3Instruction has operands EEEEEEE EEEEE EE EEEEE

Pascal Code : a := b + c; MIPS Code :

0 1 2add $s , $s , $s

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MIPS Arithmetic Pascal Code : E EE: = + + ;

- e := f a; MIPS Code : 0 1 2add $t , $s , $s

00 3add$s ,$t ,$s 4 5 0sub $s , $s , $s

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Register & Memory Registers were used in Arithmetic In

- structions 32 registers

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Memory OrganiEEEEEE Memory is an index into the array Byte Addressing = points to a byte of

memory

1 8 bits of Data8 bits of Data8 bits of Data8 bits of Data8 bits of Data8 bits of Data8 bits of Data

234567

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Memory OrganiEEEEEE - 32 4For MIPS, a word is bit or by

EEE232 bytes with byte addresses fro

0 2m to -321

230 words with byte address from 0 4 6 2, , , …, -324

0 32 bits of Data32 bits of Data32 bits of Data32 bits of Data32 bits of Data32 bits of Data32 bits of Data

48

12162024

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MIPS Load/Stor e Instruction

Code : 8 8A[ ] = h + A[ ];

8 8 4 32A[ ] ==> x = (word alignment)

MIPS Code : lw $t0, 32(3); 0,2,0;

0sw $t , 32 3($s );

Arithmetic Operand is Register, not Memory!!

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Example : Swap (int v[], int k);

{ Int temp;

temp = v[k]; swap: muli $2, $5, 4

v[k] = v[k+1]; add $2,$4,$21v[k+ ]=temp; 15 0 2lw $ , [$ ]

} lw $16, 4[$2] sw $16, 0[$2] sw $15, 4[$2]

31jr $

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Meaning

EEE 2 4 2$ , $ , $ 2 4 2$ = $ + $ ;lw 16 0 2$ , [$ ]

16 0 2$ = Memory[ + $ ]sw 15 4 2$ , [$ ]

4 2 15Memory[ +$ ] = $

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Machine Language Instructions, like register & words of

32data are bits long.- 0 1 2add $t , $s , $s

- 0 9 1 17 2register : $t = , $s = , $s 18

Instruction Format

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Machine Language - I type for Data transfer instruction Example : lw $t0 , 3 2 ($s2 )

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Control Decision Making instructions MIPS conditional branch instructions:

- bne $t0, $t1, label- 0 1beq $t , $t , label

Example : if (i=j) h= i +j;EEE 0 1$s , $s , Labeladd 3 0 1$s , $s , $s

EEEEE E EEE

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Control MIPS unconditional Branch Example :

if ( i != j) beq $s4, $s5, label;h=i+j; add 345

else j lab2-h=i j; lab1: sub $s3, $s4, $s5

lab2: …

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Summarize :

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EEEEEEEE

Use MIPS Assembly to write program.

1. “Factorial Program” n is input, Example : if n=3,

3 3 2 1 6result = ! = x x =

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EEEEEEEE

Use MIPS Assembly to write program.

2 E EEEE EEEEEEE EEEE EEE E EEE EE E he MIPS instructions

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MIPS Instructio n Encoding

E EEEEE EEE E EEE EEEEEE EE EEE 3 18

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