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Bipolar transistor Logic Circuits-Surendra ShresthaDepartment of
Electronics and Computer EngineeringPulchowk Campus, Institute of
Engineering, T.U.2.1Types of Devices2.2Propagation Delays2.3Power
Dissipation2.4Fan-IN and Fan-OUT2.5Noise Margin
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Chip: miniature circuits on
the surface of a small piece of semiconductor material using
advance photolithographic process
Integrated Circuit (IC):The finished network is so small that
need a microscope to see the connection. Integral part of the chip
components are transistor, diodes, resistors
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Saturated family(IC are
driven between cut-off and saturation states, e.g. inverter)Bipolar
Logic Family:Uni-polar logic familyResistor Transistor Logic
(RTL)Direct Coupled Transistor Logic (DCTL)Integrated Injection
logic (I2L)Diode Transistor Logic (DTL)Transistor Transistor Logic
(TTL)High Threshold Logic (HTL)Schottky TTLEmitter Coupled Logic
(ECL)PMOS (p-channel) and NMOS (n-channel)CMOS (Complementary
MOS)(transistors are operated between cut-off and active
states)Non-saturated family
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Bipolar Logic Family:Based on
the number of transistors (BJT or MOSFET) Small Scale Integration
(SSI)- 0 to 10 Medium Scale Integration (MSI)- 10 to 100 Large
Scale Integration (LSI)- 100 to 1,000Very Large Scale Integration
(VLSI)- 1,000 to 10,000 or thousands gatesSuper-Large Scale
Integration (SLSI) - 10,000 and 100,000 transistorsUltra-Large
Scale Integration (ULSI) - more than 1 million transistors
transistors
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Speed of operation (propagation delay, tpLH and tpHL) power
dissipation (power consumption under static condition, 0,1; during
the switching intervals or dynamic conditions)Current and voltage
parameters (High level input and output voltages and low level
input and output voltages; IiH, IoH, IiL, IoL)Noise immunity
(measure of how much stray noise voltage the device can handle
without giving any error at the output level)Fan-out (No. of gates
that gate in HIGH output state can feed without voltage dropping by
more than the allowable noise margin (NM)H)Department of
Electronics and Computer EngineeringPulchowk Campus, Institute of
Engineering, T.U.Characterization of Digital ICsThe various
characteristics of digital ICs that can be used to compare their
performance are:
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Resistor Transistor Logic
(RTL):Resistor-transistor logic gates use Transistors to combine
multiple input signals, which also amplify and invert the resulting
combined signal. Often an additional transistor is included to
re-invert the output signal. This combination provides clean output
signals and either inversion or non-inversion as needed.A simple
N-input RTL NOR Gate
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Resistor Transistor Logic
(RTL) Advantages:- RTL gates are almost as simple as DL gates, and
remain inexpensive.- Using low power supply for each gate.- RTL
integrated circuits are sometimes used as inexpensive small-signal
amplifiers, or as interface devices between linear and digital
circuits.
Limitations:- RTL gates cannot switch at the high speeds used by
today's computers- These are not designed for linear operation- low
noise margin
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Resistor Transistor Logic
(RTL) Logical NOR Gate
VinAVinBVoLLHLHLHLLHHL
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Resistor Transistor Logic
(RTL) VinL = 0.2 (LOW input to both transistors)
Under this condition, both transistors will be cutoff, making
the output high. The circuit diagram with circuit models for the
cutoff transistors is shown in Figure. The output voltage then is
3.0 Volts. We will call this a no-load condition when there is no
load connected to the output.VoH = 3.0 Volts (No-Load)RTL gate with
both inputs low. The transistors are replaced by the cutoff
model.VinLmax = 0.5 Volts.IinL = 0
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Resistor Transistor Logic
(RTL) INPUT HIGH
In this case we want the transistor to be saturated. Either
transistor saturated will cause the output to go low, to 0.2 volts.
This case is shown in Figure. We show the circuit with one of the
transistors cutoff, although both saturated would produce the same
result.We start by determining the minimum input current that will
keep the transistor in saturation.RTL gate with one input highthe
minimum input voltage that will be guaranteed to be recognized as a
"high"
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Resistor Transistor Logic
(RTL) Any input voltage greater than or equal to 0.866 volts will
cause the transistor to be saturated, and thus be recognized as a
"high". We previously found VinLmax =0.5 volts. Any input voltage
between 0.5 and 0.866 is an invalid logic level and the
manufacturer assumes no responsibility if it provide an input
voltage in that range. For the gate with no load, the
relationshipsbetween input and output voltagesare presented
graphically in Figure.Noise Margins (High, H and Low, L) NMH and
NML.Graphical representation of inputvoltage ranges and output
voltages for the unloaded RTL gate.
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Resistor Transistor Logic
(RTL) Terminal specifications for the RTL Gateload requires a
minimum of 0.146 mA as input current,
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic
(DTL):By letting diodes perform the logical AND or OR function and
then amplifying the result with a transistor, we can avoid some of
the limitations of RTL. DTL takes diode logic gates and adds a
transistor to the output, in order to provide logic inversion and
to restore the signal to full logic levels.
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.the diode AND function on the
front end and the transistor NOT at the output end. The extra
resistors and diodes areused to maintain appropriate currents, to
maintain proper functioning, and to guaranteecertain noise
margins.
Digital NAND circuitDiode Transistor Logic (DTL): Diode logic
and truth tables
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.If all inputs are high,
(+5v), no current will come out of the input diodes at the input
and current will flow down through the first 5K resistor and
through the diodes D1and D2 toward the base of the transistor. Some
current will split off and go down through thelower 5K resistor to
ground. However, most of the current will go into the base of the
transistor causing it to saturate, pulling the output low, VO = 0.2
Volts. We will show this condition quantitatively shortly. If one
or more of the inputs to the gate are held low (0.2 V), then the
current down through the 5K resistor will go out the input diode,
away from the transistor base. Underthis condition, the transistor
will be cutoff and the output will be high with VO = 5 Volts.Diode
Transistor Logic (DTL):
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
DTL gate model with input lowFrom this circuit we can calculate all
voltages and currents and prove (or disprove) our assumptions about
the condition of each element.
The voltage at point P isVP = 0.2 + 0.70 = 0.90 Volts.
ANALYSIS WITH INPUT LOW
Quantitatively, we will start with one or more inputs held low,
at 0.2 Volts. From the logic function of the NAND gate, we know
that the output is supposed to be high. Therefore, the transistor
must be cutoff. To begin with, we will assume the two diodes D1 and
D2 in series will also be cutoff. All the current coming down
through the 5K resistor must all go out through the input diode,
causing it to be on. The circuit with the models indicated is shown
in Figure.
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
We need to show that this voltage is low enough that the two series
diodes and the transistor will be cutoff. The argument is that if
either diode carries current, then both must. Since 0.9 Volts is
not enough across the pair to maintain conduction, then
neitherconducts. Given that the diodes are off, then the voltage at
the base of the transistor is zero, and is also cutoff. We can
verify that the input diode is conducting by observing that current
I1 isI1 = (5-0.9)/5K = 0.82 mA.
This current leaves through the input diode, hence it is on. The
current entering the input terminal isIin = - I1 = -0.82 mAThe
negative sign occurs because the input current is defined as going
into the terminal.
We can now verify that the output voltage is 5 Volts because the
transistor has been shown to be cutoff. Thus,VO = 5.0 Volts
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
One other characteristic of the DTL gate that can be obtained at
this point is the range of input voltages that will be recognized
as a "low". From the logic function of the NAND gate, this can be
translated into the question of how high the input voltage may rise
and still keep the transistor cutoff.The transistor will remain
cutoff as long as the voltage at the base does not rise above 0.5
volts. At this voltage, there will be current down through the
lower 5K resistor to ground. This current must come from the +5
supply down through the upper 5K resistor and the diodes, D1 and
D2. Hence the diodes must be conducting. This current will be 0.1
mA. The voltage at point P will beVP = 0.5 + 0.7 + 0.7 = 1.9
VoltsThe current I1 isI1 = (5-1.9)/5K = 0.62 mAThe current going
out through the input diode will beIin = -(0.62 - 0.1) = -0.52
mA
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
indicating that the input diode is still conducting. Figure next
slide shows the resulting circuit with the circuit models included.
The maximum voltage at the input that is guaranteed to be
recognized as a low isVinLmax = 1.9 -0.7 =1.2 Volts.DTL circuit
model with Vin = VinLmax
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
ANALYSIS WITH ALL INPUTS HIGHWhen all inputs are high, all current
down through the upper 5K resistor will go toward the base of the
transistor, causing it to saturate. The series diodes will
obviously be conducting, and we will show that the input diodes are
cutoff. Figure shows the circuit with these models.DTL circuit
model with inputs highThe voltage at point P isVP = 0.8 + 0.7 + 0.7
= 2.2 voltsThus, I1 isI1 = (5-2.2)/5K = 0.56 mA
Current going down through the 5K resistor will beI2 = 0.8/5K =
0.16 mAThe base current then isIB = 0.56 - 0.16 = 0.4 mA
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
If the transistor is to be saturated, the maximum collector current
isICmax = IB = 30 * 0.4 mA = 12.00 mA
at saturation, the current coming down through the 2.2K
collector resistor isI3 = (5-0.2)/2.2K = 2.182 mAthis current is
much less than the maximum saturation current and we see that with
no load, the transistor will, indeed, be in saturation.
In fact, there is excess capacity in collector saturation
current. This excess capacity can be used to sink external load
current. This current is called Io or load current. The maximum
load current this gate can sink isIoLmax = 12.00 mA - 2.182 mA =
9.818 mANote that this current is entering the terminal of the
gate, hence, is positive.
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
CALCULATION OF FANOUTIf several load gates are connected to the
output terminal of the gate we are looking at, we need to look at
the current output drive capability compared to the input current
requirements of the load gates. Because the input current is zero
when high, an infinite number of load gates can be driven when
high. However, the DTL gate requires current when the input is low.
This situation is shown in Figure. IinLmax = - 0.82 mA. Negative
meaning that it is coming out of the input terminal. The output of
a gate can sink 9.818 mA when it is low. DTL driver gate with N
identical DTL load gatesComparison of Vout and Vin voltages for DTL
gate.
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Diode Transistor Logic (DTL):
Terminal Specification for the DTL GATE
VinLmax = 1.2 V VoL = 0.2 V
VinHmin = 1.6 V VoH = 5 (at IoH =0) = 1.6 (at IoH = max)
IinL = - 0.82 mA IoLmax = 9.818 mA
IinH = 0 IoHmax = -1.545 mA (at VoH=VinHmin)
Fanout = 11
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Other logical functions:DTL
AND-OR-INVERT gateDTL OR gateDTL AND gateDTL NOR gate
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.930 Series DTL (ca 1964
A.D.):One of the series diodes is replaced by Q1, providing more
base drive for Q2 and improving the fan-out (Nmax= 45)tPLH >>
tPHLtPLH = tS+tr /2
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Transistor Transistor Logic
(TTL): The DTL input uses a number of diodes which take up
considerable chip area.
In TTL, a single multi-emitter BJT replaces the input diodes,
resulting in a more area-efficient design.
- DTL was removed by faster TTL gatesby 1974.Why TTL?
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Transistor Transistor Logic
(TTL): - ALL INPUTS HIGH. Q1 is reverse active. Q3 is saturated.
VOL = VCES
- ANY INPUT LOW. Q1 is saturated. Q3 is cut off. VOH = VCCBasic
TTL NAND gateThe diode D2 from DTL circuit can be replaced by a
transistor whose collector is pulled up to the power supply;
transistor Q2 in Figure. The p-n junction of D2 is replaced by the
BE junction of Q2 and with the current gain of the transistor, the
current going into the base of Q3 is greatly increased, increasing
the fanout.Figure 1Figure 2
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Transistor Transistor Logic
(TTL): The input diodes and D1 are replaced by the multi-emitter
NPN transistor, Q1, and represented by the drawing in right Figure.
Later on, we will make additional modifications to this circuit to
improve its performance further.
The analysis of this circuit follows very much the same path as
the analysis of the DTL gate. For the most part, we will consider
the input transistor, Q1, to act just like two diodes. The
transistor Q2, however, will operate in all three regions. The
treatment of the output voltages and currents will be treated the
same as the DTL gate and Q3 will either be cutoff or saturated,
corresponding to an output high and an output low,
respectively.
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.ANALYSIS WITH ONE OR MORE
INPUTS LOWTTL circuit model with one input lowFigure 3Figure 4TTL
circuit model to determine VinLmax.
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.ANALYSIS WITH ONE OR MORE
INPUTS LOW With an input low, Q3 should be cutoff. We will assume
Q2 is cutoff and then check our assumption. If Q2 is cutoff, then
there can be no current coming out of the collector of Q1, hence
its base-collector junction can be modeled as an open circuit. The
base-emitter junction of Q1 will be conducting. The circuit with
these models substituted for the transistors is shown in Figure 3.
Note the similarity to the DTL circuit under the same conditions.
The two unused inputs are assumed to be high, and are thus, modeled
as open. From this case, we can see that VoH = 5 volts with no
load, and
IinL = -I1 = -(5-0.9)/4K = -1.025 mA
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.ANALYSIS WITH ONE OR MORE
INPUTS LOW We turn now to finding VInLmax. We will use the
criterion that Vin will be considered as a low as long as Q3 is
kept cutoff. If the base voltage for Q3 can be raised to 0.5 Volts
without turning it on, then there will be 0.5 mA current in the 1K
resistor. This current can only come from Q2, which means it must
be conducting. Even assuming all this 0.5 mA comes through the
collector of Q2, the voltage drop across the 1.4 K resistor will be
0.7 Volts, not enough to cause the transistor to saturate. Thus,
the active model for Q2 is appropriate as shown in Figure 4.If we
assume that =30, the base current in Q2 is
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.Because this current is
coming out of the collector of Q1, the base- collector junction of
Q1 is on, and is modeled as a diode in Figure 4.The voltage at B1,
the base of Q1, isVB1 = 0.5 + 0.7 + 0.7 = 1.9 Volts
The current coming down through the 4 K resistor, I1, isI1=
(5.0-1.9) / 4K = 0.775mA
This is considerably more than is going into the base of Q2,
therefore, the input BE junction of Q1 will also still be
conducting. The maximum voltage at the input isVinLmax = 1.9 - 0.7
= 1.2 VoltsANALYSIS WITH ONE OR MORE INPUTS LOW
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.The circuit model for the TTL
gate with all inputs high is shown in Figure 5. Both Q2 and Q3 are
modeled as saturated, an assumption that must be verified. With the
inputs high, Q1 is modeled as two diodes with the B-E diodes
cutoff, and B-C diode conducting.The voltage at the base of Q1
isVB1 = 0.8 + 0.8 + 0.7 = 2.3 Volts.CALCULATIONS WITH INPUT
HIGHFigure 5TTL gate circuit model with all inputs highThe current
down through the 4 K resistor, I1 is
I1 = (5.0-2.3) / 4K = 0.675mA
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.All this current goes into
the base of Q2.IB2 = 0.675 mA
If Q2 is saturated, voltage at its collector terminal isVC2 =
0.8 + 0.2 = 1.0 VoltsAnd the collector current isIC2 = I2 = (5.0
1.0) / 1.4K = 2.857mA
Clearly, if = 30, B2 > IC2 , and, therefore, Q2 is
saturated.
The current coming out of the emitter of Q2 is the sum of the
base and collector currents. Part of this current will go down
through the 1 K resistor to ground and the rest will enter the base
of Q3.IB3 = IB2 + IC2 - I3 = 0.675 + 2.857 - 0.8 = 2.732
mACALCULATIONS WITH INPUT HIGH
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.The maximum collector current
that Q3 can carry and still be in saturation is IB3 = 81.96 mA,
assuming =30. The maximum current the gate can sink when the output
is lowIoLmax = ICsatmax - I4 = 81.96 - 1.2 = 80.76 mA
Now let's turn our attention back to the input and determine
VinHmin and IinH . We will define the input voltage to be high as
long as no current goes out the input terminal.
Thus, all we have to do is keep the input voltage high enough so
that the B-E p-n junction of Q1 does not turn on. Thus,VinHmin =
2.3 - 0.6 = 1.7 VoltsCALCULATIONS WITH INPUT HIGH
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Department of Electronics and Computer EngineeringPulchowk
Campus, Institute of Engineering, T.U.As the designers of TTL gates
became more sophisticated, they developed modifications which would
provide special characteristics. The original series of TTL was
designated as 74XX, where the XX is replaced by logic function ( 00
is a quadruple 2-input NAND, 04 is a hex inverter, etc.) The 74LXX
series is a low power family. 74HXX is a high speed family. 74SXX
is a family based on Schottky diodes and transistors. 74LSXX is a
family of low power Schottky. A 54xXX is also provided as a
companion family to the 74xXX families. The 54... families are
identical to the 74... families, except for operating temperature
range and tolerance on power supply voltage.TTL FAMILIES
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Emitter Coupled Logic (ECL)
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ECL gates use differential amplifier configurations at the input
stage. A bias configuration supplies a constant voltage at the
midrange of the low and high logic levels to the differential
amplifier, so that the appropriate logical function of the input
voltages will control the amplifier and the base of the output
transistor. The propagation time for this arrangement can be less
than a nanosecond, making it for many years the fastest logic
family.
ECL family include the fact that the large current requirement
is approximately constant, and does not depend significantly on the
state of the circuit. This means that ECL circuits generate
relatively little power noise, unlike many other logic types which
typically draw far more current when switching than quiescent, for
which power noise can become problematic. In an ALU - where a lot
of switching occurs - ECL can draw lower mean current than CMOS.
Emitter Coupled Logic (ECL)
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The ECL circuits available on the open market usually operated
with negative power supplies (-5.2 volts), and logic levels
incompatible with other families (required additional interface
circuits). The fact that the high and low logic levels are
relatively close meant that ECL suffers from small noise margins,
which can be troublesome.
The drawbacks associated with ECL have meant that it has been
used mainly when high performance is a vital requirement.
Other families (particularly advanced CMOS variants) have
replaced ECL in many applications, even mainframe computers.
Uses:- Older high-end mainframe computers, such as the
Enterprise System/9000 members of IBM's ESA/390 computer family,
used ECL; current IBM mainframes use CMOS.
The equivalent of emitter-coupled logic made out of FETs is
called source-coupled FET logic (SCFL).Emitter Coupled Logic
(ECL)
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Integrated Injection Logic (IIL, I2L, or I2L) is a class of
digital circuits built with multiple collector bipolar junction
transistors (BJT). When introduced it had speed comparable to TTL
yet was almost as low power as CMOS, making it ideal for use in
VLSI (and larger) integrated circuits.
The logic voltage levels are very close (High: 0.7V, Low: 0.2V),
I2L has high noise immunity because it operates by current instead
of voltage.
I2L, sometimes also called Merged Transistor Logic (MTL), is
relatively new in concept as well as realization. This is quite
attractive for LSI/VLSI realization.Integrated Injection Logic
(I2L):
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OperationThe heart of an I2L circuit is the common emitter open
collector inverter. An inverter consists of an NPN transistor with
the emitter connected to ground and the base biased with a forward
current. The input is supplied to the base as either a current sink
(low logic level) or as a high-z floating condition (high logic
level). The output of an inverter is at the collector. Likewise, it
is either a current sink (low logic level) or a high-z floating
condition (high logic level).To understand how the inverter
operates, it is necessary to understand the current flow. If the
bias current is shunted to ground (low logic level), the transistor
turns off and the collector floats (high logic level). If the bias
current is not shunted to ground because the input is high-z (high
logic level), the bias current flows through the transistor to the
emitter, switching on the transistor, and allowing the collector to
sink current (low logic level). Because the output of the inverter
can sink current but cannot source current, it is safe to connect
the outputs of multiple inverters together to form a wired AND
gate. When the outputs of two inverters are wired together, the
result is a two-input NOR gate because the configuration (NOT A)
AND (NOT B) is equivalent to NOT (A OR B). This logical
relationship is known as De Morgan's Theorem.Integrated Injection
Logic (I2L)
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Integrated Injection Logic (I2L)
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Important features are:
The circuit uses BJTs, both pnp and npn. Therefore operating
speed is quite high.The circuit is similar to RTL, except that
there are no base resistors used. This minimizes the circuit area
and simplifies the circuit lay-out.All the gate transistors are
operated in the inverted mode. Not only does this facilitate the
use of low voltage supply for the circuit.The circuit requires no
isolation unlike the previous digital ICs. This facilitates higher
packing density and also reduces the fabrication cost, as fewer
masks (e.g. only four) are required for the complete
process.Parasitics in the circuit are greatly reduced. This also
improves the operating speed of the IC.Integrated Injection Logic
(I2L)