2012-2016 Microsystem Technology Strategy and Roadmapsitac.ca/uploads/events/2012/exec_forum_oct2012_tech_roadmap_cmc.pdf · 10/6/2012 · Technology Strategy • The core microsystem-enabling

CMC Microsystems and Canada’s National Design Network

2012-2016 Microsystem Technology Strategy and Roadmaps

© 2012, CMC Microsystems 1

October 6, 2012[Reference: MTSR rev2.37b]

© 2012 CMC Mirosystems – Proprietary and Confidential

© 2012, CMC Microsystems Strategy and Roadmap, Work in Progress 2

Content

• Objectives• Linking technologies and applications• Roadmap creation process• CMC’s microsystem technology priorities• Technology strategy and roadmaps

– Microelectronics– Photonics– Embedded systems

• Appendix I– CMC mission and vision– Canada science and technology R&D priority areas, STIC– 2009 roadmap– Technology Readiness Levels (TRL)– CMC Solutions – R&D Themes– References

• Appendix IIOther technology focuses and views:– MEMS– Microfluidics (uF)– Packaging and assembly (P&A)– Test and design-for-test– Nanotechnology


Context, Purpose, Objectives

• What is CMC’s Technology Roadmap? – Representation of technologies or capabilities relevant to NDN with

indication of a timeframe when the first elements (design, prototyping, test) of a technology are expected to be available or introduced.

– Drawn upon a number of sources including stakeholder feedback, market intelligence, technical reports, publications, other roadmaps, known availability of supply, etc..

• Purpose and Objectives– Identify and align stakeholder needs and technologies required to

satisfy those needs– Translate corporate objectives to technology targets, achieve

corporate mission– Support planning and guide resource deployment – a driver for

CMC’s operating plan


Roadmap Process

Roadmaps integrate commercial and technological knowledge (EIRMA, 1997)

Stakeholder feedback

Today we are here

September 2012

CMC SolutionsR&D Themes

Strategy

More Moore More than Moore

Emerging Technologies

Application Specific Technologies

Functions

Microsystems

Attributes

DesignPrototypingTest

Materials Devices Components

Software Algorithms

Systems Modules

© 2012 CMC Microsystems

Application Space: Biomedical, ICT, Automotive, Consumer, Portable, Aerospace, Defense, Environment, Energy, etc..

Technologies

5


Roadmap Process –Stakeholder Engagement• Initial phase

– Environmental scan– Straw-man roadmaps– Initial stakeholder feedback– Refinement

• Three Technology Advisory Committee meetings– Strategic Directions in Microelectronics, TAC13 July 2011– Strategic Directions in Photonics, TAC114 November 2011– Strategic Directions Enabling Embedded Systems R&D, TAC116 April 2012

• Four stakeholder roadmap sessions– Photonics North 2012, Ottawa June 2012– NEWCAS 2012, Montreal (2 sessions) June 2012– CMOSET 2012, Vancouver July 2012

• A number of individual stakeholder meetings and interactions took place seeking feedback on preliminary roadmaps

• Stakeholder outreach to date - more than 80 industry and academia members. Process ongoing!


2012-2016 CMC/NDN Microsystem Technology Priorities

• Technology focus: Integration– Multi-energy domain integration (electronics, photonics, MEMS, fluidics)– Hybrid integration as a primary integration approach– Functional diversification – Embedded software– Miniaturization

• Application focus: Sensors– Sensing technologies (transducers)– Signal conditioning / processing / actuation– Communication / wireless / networking– Embedded intelligence /programmability– Energy harvesting / generation / storage

• Applications: “General Purpose Technology”– Communications, Healthcare, Transportation– Energy, Environment, Security– Sector supply chain relevant

• Business perspective: Commercialization– Technology scalability– Technology industrial relevance

Application

Technology

Commercialization

Application Space / Market Segments


Embedded Systems• Embedded intelligence• Programmability

Photonics• Signal processing• Communication• Sensing• Energy generation

Microelectronics• Signal processing• Communication• Data storage / memory

MICROSYSTEMS

MEMS, Microfluidics, Nanotechnology

• Sensing• Actuation• Material property modification• Energy generation

Microsystems Technologies – Domains and Functions


Roadmap Structure

Silicon Semiconductor 28nm CMOS 22nm CMOS 14nm FD SOIFinFET model 20nm FD SOI 14nm FinFET

Imaging/Opto CMOS Imaging/Opto 0.13/0.18 CMOS Color filter / microlens imaging CMOS

HV CMOS HV CMOS library 0.18 HV CMOS0.13um 3D IC 90nm/65nm 3D IC Heterogenious 3D IC

Back‐to‐face 3D IC stackingHigh‐aspect ratio TSV (>20:1) Multi‐tier (2+) 3D IC

Compound Semiconductor GaN Field‐plate and low‐leakage GaN Through via GaN 0.25um GaN SiC SiCSiGe 200GHz 0.13um SiGe 300GHz 90nm SiGe

Hybrid Integration & Packaging SiP Multi‐die planar 2.5D SIP 3D SiP

Interposer Coarse pitched interposer (200 um) Interposer with COTS/KGD Fine pitched interposer (20um)

Low‐loss high‐frequency (>70GHz) Heat dissipation substrate Fine line substrate (trace/space 10um)Substrate with embedded functions

Flip‐chip (60um pitch) Solderless flip‐chip 1GHz+ RF Package Flip‐chip (35um pitch)Heavy‐duty wirebond High‐power device packaging Vacuum packaging

Fine‐pitch wirebond (35um) High temperature packaging (120‐350C) Packaging for flexible systems

Energy Generation and Storage Photovoltaic energy harvesting Super‐capacitor Kinetic/thermal energy harvesting Chemical energy harvesting

Bio‐compatible coating TSV on die Surface functionalization depositionDie thinning Transducer/sensor layer deposition

Monolithic Multi‐domain Integration Integrated CMOS/MEMS Integrated CMOS/MEMSIntegrated CMOS/Photonics Integrated CMOS/Photonics

New and Emerging Printable electronicsFlexible electronics

Nanoelectronics Nanoelectronics

2015 2016

Technologies 2012 2013 2014 2015 2016

3D IC

2012 2013 2014

Substrate

Packaging and Assembly

Compo

nent Techn

ologies

Integration

Postprocessing/Functionalization

Advanced CMOS

Printable/Flexible Electronics

Technology themes Roadmap itemsCategories

Com

pone

ntte

chno

logi

esIn

tegr

atio

nte

chno

logi

es

Newemerging

Focu

s ar

eas

Technology capability / features

Timeline


Embedded System Technology Strategy• Deliver programmable technologies to enable development of autonomous,

reactive systems that can be embedded in user environments, and that can provide capabilities such as system self-test and calibration, self-repair and in-field upgrades

• Use a programmable, platform-based approach for: – Accelerated microsystem development cycle – Enhanced usability and smoother transition between microsystem

instantiations (e.g., from benchtop demonstration to field trial), leading to increased commercialization potential

• Provide commercially-available (or commercially-developed) platforms, tools, IP; open-source or standards-based infrastructure; custom development targeting filling gaps or improving usability

• Strategic technology elements include parallel programming, sensor integration, model-based design, verification and reliability, energy-aware programming and code analysis, cyber-physical systems, software development and virtualization, and Application-specific Instruction-set Processors (ASIPs)


Design Methodology Multiprocessor virtual platform Heterogeneous multiprocessorAutomated code parallelization Dynamic code optimization

HW/SW Co‐design System‐level Power analysis/optimization Automated partitioning

Simulink‐based flow Authoring for certification/reliability

Verification Single‐processor static/dynamic code analysis Multiprocessor static/dynamic code analysis

Platform emulation

MEMS/Microfluidics Hardware‐in‐the‐loop Photonics Hardware‐in‐the‐loop "Bio‐in‐the‐loop"

Software Development 100k lines of code Real‐time Integrated debug instrumentation

Custom C Compiler generation C Compiler Designer/Optimization

25 software functions/program 50 software functions/program

Power trace debugging

Languages LabView UML

C/C++ OpenCL SystemC‐AMS Cross‐platform design language

OpenMP Synthesizable OpenCL

FPGA 2M Logic Cells 4M Logic Cells 8M Logic Cells 16M Logic Cells

Dual‐core embedded processor

Soft/firm processor

Partial reconfiguration

Quad‐core embedded processor

Processor 32‐bit 8‐core 64‐bit quad‐core 64‐bit 8‐core 64‐bit 16‐core

8k L1 cache SRAM Benchmarking cluster 16k L1 cache SRAM

ASIP Next generation memory (beyond flash)

Soft GPU

Operating Systems Single‐processor RTOS Mobile OS

Dynamic computational load balancing

Sensor/actuator library Heterogeneous multicore RTOS

Interconnect and Communications Electrical network on chip Optical switching fabricZigbee PCIe Gen 3 PCIe Gen 4

Bluetooth low energy Optical USB End‐to‐end, secure low‐power protocol

Cyber‐Physical Systems Sensor fusion Integer linear programming tools Closed loop microsensor control

Wearable computing

Time synchronization Power‐scavenging

2015 2016

2012 2013 2014 2015 2016

2012 2013 2014

Technologies and Strategic Elements

2012‐2016

Embedded Systems Technology Roadmap


Microelectronics Technology Strategy

• The core microsystem-enabling hardware technology

• Continuous emphasis on CMOS for providing essential functions of signal processing, conditioning, and data storage to the microsystems

• Focus on system integration and functional diversification through incorporation of other domain technologies (photonics, MEMS, microfluidics, nanotechnology processes)– Hybrid integration - a primary vehicle for system integration– Monolithic integration – addressing limited application space

• Addressing application-specific performance requirements through compound semiconductor, high-voltage, imaging and other technologies


2012‐2016

Microelectronics Technology Roadmap

Silicon Semiconductor 28nm CMOS 22nm CMOS 14nm FD SOIFinFET model 20nm FD SOI 14nm FinFET

Imaging/Opto CMOS Imaging/Opto 0.13/0.18 CMOS Color filter / microlens imaging CMOS

HV CMOS HV CMOS library 0.18 HV CMOS0.13um 3D IC 90nm/65nm 3D IC Heterogeneous 3D ICFace‐to‐face 3D IC stacking Back‐to‐face 3D IC stacking

High‐aspect ratio TSV (>20:1) Multi‐tier (2+) 3D ICCompound Semiconductor GaN Field‐plate and low‐leakage GaN Through via GaN 0.25um GaN

SiC SiCSiGe 200GHz 0.13um SiGe 300GHz 90nm SiGe

Hybrid Integration & Packaging SiP Multi‐die planar 2.5D SIP 3D SiP


Low‐loss high‐frequency (>70GHz) Heat dissipation substrate Fine line substrate (trace/space 10um)Substrate with embedded functions

Flip‐chip (60um pitch) Solderless flip‐chip RF Package Flip‐chip (35um pitch)Heavy‐duty wirebond High‐power device packaging Vacuum packaging

Fine‐pitch wirebond (35um) High temperature packaging (120‐350C) Packaging for flexible systems

Energy Generation and Storage Photovoltaic energy harvesting Super‐capacitor Kinetic energy harvesting Chemical energy harvesting

Bio‐compatible coating Die thinning TSV on dieSurface functionalization Transducer/sensor layer deposition

Monolithic Multi‐domain Integration Integrated Electronics/MEMS MEMS on GaN Integrated CMOS/MEMSIntegrated Electronics/Photonics Integrated CMOS/PhotonicsIntegrated Electronics/uF Digital uF ISFET/uF Integrated CMOS/uF

New and Emerging Printable electronicsFlexible electronics

Nanoelectronics Nanoelectronics

Printable/Flexible Electronics

Compo

nent Techn

ologies

Integration

2015 2016

Technologies 2012 2013 2014 2015 2016

3D IC

2012 2013 2014

Substrate

Packaging and Assembly


Advanced CMOS


Photonics Technology Strategy

• Photonics as a systems-enabling technology: focus on integration– More photonic functionality on the same chip (silicon

photonics, InP integration)– Integration of photonics and microelectronics

• Monolithic approaches (SOI+CMOS, InP)• Hybrid approaches– packaging & assembly

– Integration of photonics with microfluidics & MEMS

• Support some custom device fabrication

• Support some activity in new materials


Silicon Semiconductor SOI passive waveguiding structures with nanoscale features

Advanced SOI silicon waveguides integrated with heaters, silicon lasers?modulators, detectors

Etched facets�

Si3N4/Si/SiO2 Si3N4/SiO2 waveguides�

Compound Semiconductor InP‐based Quantum dot lasers at 1550nmSelective area epitaxy

GaAs‐based Epitaxy: quantum cascade structuresQuantum cascade lasers

III‐V integration platform InP integration platform Advanced integration platform

Hybrid Integration & Packaging Packaging & assembly CMOS + photonics Source/detector + photonicsInterconnects Fibre‐to‐chip coupling Fibre array to chip coupling with electrical I/Os

Surface functionalization AR/LR/HR coating Bio‐functionalizedoptical sensors

III‐V + silicon photonics integrated III‐V/Si devices

Monolithic Multi‐domain Integration Photonics + CMOS SOI + CMOS (130nm) monolithically integratedsilicon OEIC?

Photonics + microfluidics Si3N4 waveguide + microfluidics SOI nanophotonics + microfluidics Fluidic waveguides

Photonics + MEMS MEMS with embedded waveguides

New and Emerging New materials

Nanoplasmonics Nanoplasmonic waveguides Nanoplasmonic biosensors

Compo

nent Techn

ologies

Integration

2015 2016

Photonics Technologies 2012 2013 2014 2015 2016

2012 2013 2014

2012-2016

Photonics Technology Roadmap


Current Status and Next Steps

• Ongoing engagement with stakeholders - through September and October meetings are being planned with researchers and the industry (e.g., CMC Symposium)

• Final comments to be solicited in the October/November timeframe

• Once targets are defined, focus to be shifted on planning. Roadmaps to drive development of CMC’s 2013/2015 operating plan

• The roadmaps to be updated during the next refreshment cycle in 2014 (every two years).

• CMC Solutions R&D program is the primary vehicle for introducing new technologies - supported by the roadmap exercise (both technology or product and service roadmaps)


Appendix I

1. CMC vision and mission2. Canada R&D science and technology priority areas3. 2009 technology roadmap4. Current R&D themes5. Stakeholder feedback summary6. Technology readiness level7. References


CMC’s Vision and Mission

– Vision: CMC enables and enhances the competitiveness of Canadian industry and researchers through innovation in the development and application of microsystems.

– Mission: CMC enables and supports the creation and application of micro- and nano-system knowledge by providing a national infrastructure for excellence in research and a path to commercialization of related devices, components and systems.


Canadian Science and Technology R&D Priority Areas

Reference: State of The Nation 2008 - Canada's Science, Technology and Innovation System

Infrastructure Technology Roadmap 2009

2009 20112010 20132012 2014Roadmap Period of Interest: April 2009 to March 2015

Technology for Devices, Structures and Transducers (sensors and actuators)

Integrated Microsystem Architecture Attributes

Design Methodology

Test Methodology

Legend: Arrows indicate continuing enhancement or new options.

Kit: digital

Kit: RFKit: analog

Footprint: 10 cm3 (includes folded PCB)Stack: 5 layers, boardsPower: mWRF centre: 430MHz, 870MHz, 2.5GHz

Footprint: 1 cm3

Stack: TSV devicesPower: nW

Design-for-assembly (flow)

Interposer: embedded passives

Fixturing: microfluidics

GaN: 0.8µm Ft~ 20GHz CMOS: 800nm to 45nm

GaN: 0.4µm Ft~ 60GHz GaN: Ft~ 125GHzCMOS: 32nm

Substrate: LTCC

Power: battery Power: scavenging Power: scavenging/implantable

Coatings: bio-compatibleCoatings: organic

Fixturing: 600MHz digital

Interposer: embedded activeCoatings: inorganic

Power: PV/solar

Photonic crystals/SOI III-V Qdot lasers III-V Qwell intermixing Photonics/GaN III-V Qcascade structures

Si-photonics Si-fluidicsMicrofluidics MEMS

Standard, scalable system driver and test interface

High-speed clock and data recovery modules

Interfaces optimised for bench-top multi-sensor system prototyping

Substrate: RF signal optimised

Substrate: RF+ microfluidic optimised

Substrate: photonic+ microfluidic optimised

Si-other enhancements

Kit: MEMS Kit: microfluidics

Kit: Multi-tech prototyping flow

New baseline instrumentation cage and racked instruments

Extend rack options for select technologies (photonics/microfluidics)

Instrument signal sensitivity on femto-scale

100 GHz BERTPortable environmental test chambers

Fixturing: multi-technologyFixturing: photonics

Fixturing/assembly: small footprint optics

SiC substrate technologies

passive, COTS, chip-scale … Antenna …active, tunable, monolithically integrated

Hours/days .. Operating time … Years/indefinite 2 (accelerometer, temp) .. Add-in sensor options … 8

Programmability: small footprint flash, register setup

Programmability: SDR, reconfigurable hardware

SIP test interface

MEMS test module (optical, 20 KHz)

MEMS resonator

Visible λ test 100 Ghz Telecom test THz component test

Simulation: co-simulation methods and portfolio of point simulators on-demand

Embedded software debug and on-line lab.

Condition telemetry (hardware, software)

Nanotechnology region epi lift-off

Nano-scale wire interconnect

Near IR λ test

Multi-processor debug Code parallelization tools Kit: real-time operations Communications protocol stack tools

Mixed-signal FPGA

© 2012 CMC Microsystems 20


Technology Readiness Levels

TRL 1 Basic principles observed and reported.

TRL 2 Technology concept and/or application invented.

TRL 3 Active research and development is initiated.

TRL 4 Component and/or breadboard validation in laboratory environment.

TRL 5Component and/or breadboard

validation in basic technological relevant environment.

TRL 6 System/subsystem model or prototype demonstrated in a relevant environment.

TRL 7 System prototype demonstration in an operational environment.

TRL 8Actual system complete and purpose-qualified through test and demonstration.

TRL 9 Actual system “purpose-proven” through successful mission operations.

• CMC Microsystems micro-nanotechnology projects fit to Technology Readiness Levels TRL2 to TRL5

• DMT Microsystems engineering work fits TRL4 to TRL7


TRL1: Establishing Basic Principles: Basic Principles observed and reported; scientific research begins

TRL2: Conceptualization: Technology concept ans/pr application formulated; invention begins

TRL3: Partitioning and Characterization: Analytical and experimental laboratory studies are a critical function; active research and

development initiated

TRL 4: Trade-offs and Interfacing: Component and/or breadboard validation in lab environment; basic technological components are

integrated to establish that the pieces work well together

TRL 5: Simulated Environment Testing: componenet and/or breadboard validation in relevant environment; technological

components are integrated with reasonable realistic supporting …

TRL 6: Prototype Demonstration: System/subsystem model or prototype demonstration in a relevant environment; representative

model or prototype system is tested in a relevant environment, e.g. …

TRL 7: Operational Prototype Demonstration: System prototype demonstration in a operational environment; prototype at or near

operational system

TRL 8: Test and Demonstration: System completed and qualified through test and demonstration; technology has been proven to work

in its final form

TRL 9: Successful Shipment and/or Operations: System proven through successful operations; actual application of the technology is

in its final form

0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20%Distribution of Faculty Member TRL Activities

Technology Readiness Level – Client Activity652 Faculty Members Reporting in 2010


CMC Solutions – R&D ThemesJune 2012

1. Antenna Technologies for RF Microsystems2. Localized Bandgap Engineering3. Conditioning, Driver Circuits and IP Libraries4. Energy Sources & Management for Autonomous Microsystems

Prototypes5. Embedded Software for Microsystems Proof-of-Concept6. Photonic Integration in a III-V Material System7. Novel Interposer Designs for Microsystems8. Miniaturized Microsystem Prototypes, Modules and Packaging9. Photonic-Electronic Integration and Packaging10. System-level Modeling11. THz and sub-THz Related Technologies


1. State of The Nation 2008 - Canada's Science, Technology and Innovation System, STIC, 20082. State of the Nation 2010 — Canada’s Science, Technology and Innovation System, STIC, 20103. ITRS Roadmap, 20114. The next Step in Assembly and Packaging: System Level Integration in the package (SiP), ITRS white paper v9.0 5. iNEMI Roadmap, iNEMI, 20116. SiC and GaN Power Electronics. Yole Development 2009 http://www.apecconf.org/2010/images/PDF/2009/special_presentations/sp1.7b_sic_gan_power_electronics_for_diffusion.pdf7. 3D technology roadmap and status, Marchal, P. et al.; Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International, 2011 , Page(s): 1 – 38. Recent innovations in CMOS image sensors, Fontaine, R., Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI, 2011 , Page(s): 1 – 59. Energy scavenging for mobile and wireless electronics, Paradiso, J.A.; Starner, T. Pervasive Computing, IEEE Volume: 4 , Issue: 1, Publication Year: 2005 , Page(s): 18 - 2710. The Future of Integrated Circuits: A Survey of Nanoelectronics, Haselman, M.; Hauck, S. Proceedings of the IEEE Volume: 98 , Issue: 1, 2010 , Page(s): 11 - 3811. Trends in MEMS Manufacturing & Packaging, Yole Development, 201112. MEMS from Device to Function, Yole Development, 201113. Motion Sensors for Mobile and Consumer Applications Report, Yole Development, 201114. Emerging MEMS Technologies & Markets, Yole Development, 201015. MANCEF International Micro/Nano Roadmap, MANCEF, 200716. 3D Packaging Magzine on 3D IC, TSV, WLP & Embedded Die Technologies, Issue N 19, May 201117. Emerging Nanophotonics, PhOREMOST Network of Excellence, 200818. FlowMap: Microfluidics Roadmap for the Life Sciences (2004)19. The Origin and Future of Microfluidics: Nature (2006)20. Microfluidics: the Great Divide: Nature (2009)21. Microfluidics-based Diagnostics of Infectious Diseases in the Developing World, Nature Medicine (2011)22. Developing Optofluidic Technology through the Fusion of Microfuidics and Optics , Nature (2006)23. Optofluidic Microsystesm for Chemical and Biological Analysis, Nature Photonics (2011)24. Trends in Microfluidics: Review of Multi-Layer Soft Lithography, Department of Engineering Physics, The University of British Columbia http://www.phas.ubc.ca/~lamm/docs/CECppt.pdf25. Emerging Markets for Microfluidics, Yole (2011)26. Microfluidic Players Database, Yole (2010)27. POC Testing: Application of Microfluidic Technologies, Yole (2012)28. Making Light Work for Canada http://www.photonics.ca/Making%20Light%20Work%20for%20Canada_2008.pdf29. Photonics in Canada: Illuminating a World of Opportunity http://www.photonics.ca/Photonics_Opportunity%202008.pdf30. OIDA: Opportunities & Trends in Optoelectronic Manufacturing 201231. OIDA: Metrics for Aggregation and Data Center Networks 201232. OIDA Roadmap Workshop: Short-Distance High-Density Optical Interconnects 201133. OIDA Silicon Photonics Workshop Summary Paper 201134. Photonic Sensors: An OIDA Symposium Report 201135. Fabrication Challenges and Opportunities in Photonics: An OIDA Forum Report 201036. P. Coteus, J.Knickerbocker, C. Lam, and Y. Vlasov, “Technologies for Exascale systems” IBM Journ. R&D, 55, No.5, 201137. Yurii A. Vlasov “Silicon CMOS-Integrated Nano-Photonics for Computer and Data Communications Beyond 100G” IEEE Comm. Mag., February 201238. IBM: 2012 CLEO Plenary talk http://researcher.ibm.com/researcher/files/us-yvlasov/vlasov_CLEO_Plenary_05092012.pdf39. Leonid G. Kazovsky, She-Hwa Yen and Shing-Wa Wong, "Photonic devices for next-generation broadband fiber access networks", Proc. SPIE 7958, 795802 (2011); 40. Jing Wu and Min Gu, "Microfluidic sensing: state of the art fabrication and detection techniques", J. Biomed. Opt. 16, 080901 (Aug 04, 2011); 41. http://www.lionixbv.nl/technology/technology-integrated-optics.html42. L. Zhuang, D. Marpaung, M. Burla, W. Beeker, A. Leinse, and Chris Roeloffzen, "Low-loss, high-index-contrast Si3N4/SiO2 optical waveguides for optical delay lines in microwave photonics signal processing," Opt. Express 19, 23162-23170 (2011)43. JePPIX Roadmap http://www.jeppix.eu/document_store/JePPIX_Roadmap_2012.pdf44. State of the art on Photonics on CMOS, 3rd update http://www.helios-project.eu/content/download/415/2605/file/HELIOS_D010_public.pdf45. HELIOS roadmap first version http://www.helios-project.eu/content/download/286/1899/file/HELIOS_D101.pdf46. Sciancalepore, C. et al., "CMOS-Compatible Ultra-Compact 1.55- μ m Emitting VCSELs Using Double Photonic Crystal Mirrors," Photonics Technology Letters, IEEE , vol.24, no.6, pp.455-457, March15, 201247. Lamponi, M.; Keyvaninia et al., "Low-Threshold Heterogeneously Integrated InP/SOI Lasers With a Double Adiabatic Taper Coupler," Photonics Technology Letters, IEEE , vol.24, no.1, pp.76-78, Jan.1, 201248. Zhen Sheng, Liu Liu, Joost Brouckaert, Sailing He, and Dries Van Thourhout, "InGaAs PIN photodetectors integrated on silicon-on-insulator waveguides," Opt. Express 18, 1756-1761 (2010)49. Electronic-Photonic Heterogeneous Integration (E-PHI), Solicitation Number: DARPA-BAA-11-45 https://www.fbo.gov/index?s=opportunity&mode=form&id=d45ee2d532e605839ecc197640928052&tab=core&_cview=150. Alexandros Emboras et al. "MNOS stack for reliable, low optical loss, Cu based CMOS plasmonic devices," Opt. Express 20, 13612-13621 (2012)51. Delacour, C.; Grosse et al.."Metal-oxide-silicon nanophotonics: An efficient integration of plasmonic nano-slots with silicon waveguides," Group IV Photonics (GFP), 2010 7th IEEE International Conference on , vol., no., pp.34-36, 1-3 Sept. 201052. Volker J. Sorger et al. "Experimental demonstration of low-loss optical waveguiding at deep sub-wavelength scales", Nature Communications, Vol. 2, 331, 201153. Peng Zhang et al. "Plasmonic Airy beams with dynamically controlled trajectories," Opt. Lett. 36, 3191-3193 (2011) 54. Nanophotonics Foresight Report 2010 http://www.nanophotonicseurope.org/images/Documents/nea_foresight_report_2011.pdf

References:


Appendix II

Other Roadmap Views

The appended material represents an elaboration of a few selected topics:

1. MEMS2. Microfluidics3. Packaging and assembly4. Test, measurement, design-for-test


MEMS Technology Focus

• Focus on integratibility of MEMS with microelectronics, photonics, and microfluidics in a microsystem

• Use two main methods to integrate MEMS with microsystem technologies– Post-processing and monolithic integration (deposition, etching, surface

micromachining of a die or wafer, embedded waveguides, MEMS on CMOS, etc.)

– Conventional packaging & assembly (flip-chip, wirebonding, SiP, etc.)

• Support emerging silicon and new material based MEMS technologies for developing custom components targeting – RF MEMS– Energy Harvesting– Optical MEMS

• In addition to commercial sourcing, increased involvement with FACT (MNT labs) for delivering technologies for building customized MEMS devices or components


RFMEMS Gold‐based MEMS Diamond‐on‐Insulator (DOI)

Energy harvesting MEMS Piezoelectric energy harvesting Electrostatic energy harvesting

Optical MEMS Flat 1mm+ diameter single mirror Micro‐mirror array

Pakcaging and assembly Solderless flip chip Vaccum Packaging

Bio‐compatible coating Die thinning TSV on dieSurface functionalization deposition Transducer/sensor layer deposition

Integrated ME/MEMS MEMS on GaN Surface SiGe MEMS on 0.18um CMOSBulk MEMS on 0.18um CMOS

MEMS on multi‐layer substrate MEMS on LTCC

Integrated MEMS/Photonics MEMS with embedded waveguide

New and Emerging NEMS NEMS

Monolithic Multi‐domain Integration

Component

Technologies

Integration

2015 2016

2016

2012 2013 2014

Hybrid Integration & Packaging

Application SpecificTechnologies 2012 2013 2014 2015


2012-2016

MEMS View of the Roadmap


Microfluidics Technology Focus• Focus on integratibility of microfluidics with microelectronics, photonics, and

MEMS in a microsystem

• Use three main methods to integrate uF with microsystem technologies– Post-processing and monolithic integration (deposition, etching, surface

modification of a die or wafer, embedded waveguides, uF on CMOS, etc.)– Conventional packaging & assembly (flip-chip, wire bonding, laser bonding,

chip stacking etc.)– Emerging techniques (injection printing/3D printing, injection molding, etc.)

• Develop standardized interface modules to integrate uF with other domain technologies

• Focus on glass, silicon and polymer based microfluidics technologies for developing custom components

• In addition to commercial sourcing, increased involvement with FACT (MNT labs) for delivering technologies for building customized microfluidic devices such as PDMS and other polymer based technologies including hot embossing, injection molding, laser micromachining, and injection printing


Substrate Material Glass Laser based fabrication technology Multilayer device with inter layer metal connection

Polymer Rigid polymer fabrication Soft Litho (PDMS) Multilayer device Multilayer device with inter layer metal connections

Hybrid Integration & PackagingPackaging and interfacing Flip‐chip TSV TGV

Fiber Coupling Standard fluidic and optical interfacing Postprocessing/Functionalization

Bio‐compatible coating Surface functionalization

Monolithic Multi‐domain Integratio Integrated ME/Microfluidics Digital Microfluidics ISFET/Microfluidics Integrated CMOS image sensor/MicrofluidicsIntegrated Photonics/Microfluidics Si3N4 waveguide integration Si waveguide integration Fluidic waveguide Nanoplasmonics based biosensing

New and Emerging Printable Microfluidics Paper based microfluidicsNanofluidics Nanofluidics

2016

Technologies 2012 2013 2014 2015 2016

2012 2013 2014

Compo

nent

Integration

2015

2012-2016

Microfluidics View of the Roadmap


Packaging & Assembly Priorities

• Meet the evolving performance/functional requirements (form factor, power, speed, frequency, etc.) of various component technologies

• Provide custom packaging solutions and application-specific functionalities (embedded or integrated passive/active components, optical interface, biocompatible encapsulation, thermal management, etc.)

• Enable or enhance the integrability of microsystems(SiP, interposer, WLP, etc.)


Packaging and Assembly View of the Roadmap

Flip‐chip Flip chip (60um pitch) Solderless flip chip Flip‐chip (30um pitch)

Wirebond Heavy‐duty wirebond

Low‐loss high‐frequency (>70GHz) substraHeat dissipation substrate Fine line substrate (trace/space 10um)Substrate embedded functionalities (passives, waveguides) Thin core, high‐layer‐count substrate (20)

Fibre‐to‐chip coupling Fibre array to chip coupling with electrical I/OsCustom application‐specific packaging GHz RF Package

High temperature packaging (120‐350C)High‐power device packaging Packaging for flexible systemsMulti‐die planar 2.5D SIP 3D SiP

SiP CMOS driver IC + photonics Source/detector + photonics


Bio‐compatible coating TSV on dieDie thinning Transducer/sensor layer deposition

surface functionalization depositionWafer‐level packaging Wafer‐level chip‐scale packaging Wafer‐level multi‐component packaging

Printable packaging and assembly

Compo

nent P&A

Hybrid Packaging

Emerging

Post processing/Functionalization

2015 2016

2012 2013 2014 2015 2016

2012 2013 2014

Technologies

Substrate/carrier


Test, Measurement, Design-for-Test (DFT) PrioritiesFocus on provision of tools and methodologies aligned with testing and measurement required to support R&D involving microsystems and constituent technologies

– Verification, validation and characterization– Hardware, software, embedded systems, integrated systems

Themes are drawn from “parent” roadmaps, encompassing:

– Test capabilities driven by More Moore (speed, frequency, complexity, power)– Harsh environment (temperature, power, radiation, etc.) testing for components and systems– 3D linked TSV and other interconnect technologies for heterogeneous or hybrid integration;

DFT methodologies– Interconnect architectures (emerging standards) and smart fixtures to enable testability

(wafer level, advanced probing, manufacturing oriented, reconfigurable)

How:– CMC test equipment lending pool– Enabling access to test facilities. E.g. NMPTC, other university labs– System-level development platforms– Provision of CAD tools supporting DFT


Test, Measurement and DFTView of the Roadmap

Extended test capabilities driven by more moore Wide spectrum quantum efficiency coherent detection Potentiometerrate table High power test beds

design/process/test integration processing integrated with in‐line test data generationMS CAD tool integration increasingly heterogeneous

3D MS CAD/verification tools

Environmental testing, components and systems thermal test 85C environmental test chamber for packaged deviceshot spot test

Solar simulator uE environmental test to 400C

3D KG‐TSV? ubiquitous TSV?P1838 effective multi‐tier functional partitioning tools

embedded test access3D‐aware CAD environment increasingly heterogeneous

DFT technologies embedded test standards 1500, p1687Embedded test for MS systems e.g. for SerDes and PLL BIST

measurement capability for parameters that are too expensive/impractical to measure off‐chip DFT for MEMS automated access to embedded diagnositic test

portable DFT files for hybrid integration and system DFT

Interconnect and smart fixtures bare die test wafer level test, including MEMS and photonicedge coupling connector solutions wafer probe for TSV commercially available KGD w test wrappers

multi‐channel couplers wafer level test highly multiplexed optical I/O @ chip convergence on connector standards

Multi‐technology prototype test Benchtop prototyping environments Test‐infus system emulators incxreasingly multi‐technology

Virtual instrumentation Robotic‐based test beds.. E.g. Helicopters for control algotithm test, automotive guidance systemswireless add‐on JTAG‐like connectivity tests Protocol‐aware FPGA‐based test; VI librariesdesigning and integrating on‐board antenna structures test of chip antenna (radiation and receiver)

Embedded software test laboratory (emSYSCAN)

New test driven by emerging technologies

THz source extension freq conversion High power pulsed laser detection solutions (broadband coverage with high sensitivity while maintaining sufficient source power)Nanotech app notes, reference designs e.g. CNT test bio‐organic test fixtures and sample prep libraries of fixtures, interfaces

2012 2013 2014 2015 2016

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Nanotechnology Focus

• Exploration and development of nano-scale devices and material structures

• Access to nano-scale technologies to develop novel devices or to enhance various functions of microsystems (acceleration, pressure, flow, sensitivity, etc.)

• Access to nano-capabilities through micro/nano fabrication labs (“FACT lab”) – Deposition, e-beam patterning, characterization at nano-level

• CAD tools for exploration and development of materials and nano-scale structures and devices