1 UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Is Overlay Error More Important Than Interconnect Variations in Double Patterning Kwangok Jeong: ECE Dept., UC San Diego Andrew B. Kahng: ECE and CSE Dept., UC San Diego Rasit O. Topaloglu: GLOBALFOUNDRIES, Inc.
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1UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Is Overlay Error More Important Than Interconnect Variations in Double.
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1UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Is Overlay Error More Important Than Interconnect Variations
in Double Patterning
Kwangok Jeong: ECE Dept., UC San DiegoAndrew B. Kahng: ECE and CSE Dept., UC San DiegoRasit O. Topaloglu: GLOBALFOUNDRIES, Inc.
2UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Outline
• Traditional BEOL Variation and Process
• Double Patterning Lithography (DPL)
• Overlay Error in Double Patterning
• TCAD-Based Analysis
• Design-Level Analysis
• Conclusions
3UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Outline
• Traditional BEOL Variation and Process
• Double Patterning Lithography (DPL)
• Overlay Error in Double Patterning
• TCAD-Based Analysis
• Design-Level Analysis
• Conclusions
4UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Traditional BEOL Variation and Process• Sources of variation:
• Metal/dielectric density-
dependent, systematic• Random process variation
• Results of variation• Width (W) variation• Metal height (H) variation• Dielectric thickness (D) variation
• Traditional backend of the line (BEOL) Process
M+1
M-1
M W H
D
Mask
exposure
etch
DielectricResist
coating
STEPS:MATERIALS:
Cu fillingCopper
5UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Outline
• Traditional BEOL Variation and Process
• Double Patterning Lithography (DPL)
• Overlay Error in Double Patterning
• TCAD-Based Analysis
• Design-Level Analysis
• Conclusions
6UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
8UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Outline
• Traditional BEOL Variation and Process
• Double Patterning Lithography (DPL)
• Overlay Error in Double Patterning
• TCAD-Based Analysis
• Design-Level Analysis
• Conclusions
9UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Introduction to the Variability in DPL• Overlay error
• Causes: • mask misalignment, • material stress-impacted
deformations,• litho/etch-impacted
topography,• lens aberration, etc.
• Results in:• Width variation• Space (or pitch) variation
Capacitance variation
• Alignment metric
• Indirect: • Two DPL masks aligned to
a reference layer• Error:
• Direct: • Second DPL mask aligned
to the first DPL mask• Error:
SS
S
S
Indirectalignment
Cc
Cg
Directalignment
S2
S
Mask1
Mask2
Reference
10UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Overlay Error in Various DPL Options• Impact on interconnect parameter in DPL options
• P (pitch), W (width), W’ W W”, P’ P P’’
1 2 1 2 1
W W
P’ P’’
S S
1 2 1 2 1
W’’ W’
P P
S S
S/2
1 2 1 2 1
WW’’
P P
S S
1 2 1 2 1
W’ W’
P’’ P’
S S
Positive DE/DP SPACE Negative DE/DP WIDTH
Positive SDP WIDTH & SPACE Negative SDP WIDTH & SPACE
11UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Mask Coloring and Layout Examples in DPL• Mechanism of misalignment-induced variation
(a) DE and DP Process
(b) SDP Process
1
2
3
4
5
6 1
2
3
4
5
6 1
4
5
2
3
6
Original patterns
Original patterns
Coloring Patterns 1 Patterns 2
Coloring Spacer formation(Large spacer)
Trim & repair (dark gray)
S S
Narrow space
W
1
2
3
4
5
6
W”
Dummy for pattern 6
1
4
5
2
3 6
Spacer (gray) a b
12UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Outline
• Traditional BEOL Variation and Process
• Double Patterning Lithography (DPL)
• Overlay Error in Double Patterning
• TCAD-Based Analysis
• Design-Level Analysis
• Conclusions
13UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
TCAD-Based Analysis Setup• Test structure
• Design of experiments (DOE)• Full combinations of W, H,
D and S• For all DE/DP/SDP with
positive/negative-tone resist• 3 variation: We assume
20% of nominal value
M+1 layer
M-1 layer
M layer
D
WH
S D: dielectric heightW: line widthH: line heightS: overlay shift
1. for (i = -3 ; i 3 ; i=i+1) {2. for (j = -3 ; j 3 ; j=j+1) {3. for (k = -3 ; k 3 ; k=k+1) {4. for (l = -3 ; l 3 ; l=l+1) {5. W=Wnom + iW3
6. H= Hnom + jH3
7. D= Dnom + kD3
8. S = Snom + lS3
9. run field solver over parameterized structure}}}8.Find nominal and worst-case capacitance
14UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
TCAD-Based Analysis Results• Overlay vs. width vs. height
• Indirect alignment shown:
• Impact of overlay: 0 ~ 2.4% of C-total• Impact of width: -13% ~ 10% of C-total • Impact of height: -32% ~ 18% of C-total• Impact of indirect alignment ~ 2x direct alignment
0.0
50.0
100.0
150.0
200.0
250.0
300.0
min nom max min nom max min nom max min nom max
Cg-down Cg-top Cc C-total
Overlay Width Height
Cap
acita
nce
(aF
/um
)
15UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Outline
• Traditional BEOL Variation and Process
• Double Patterning Lithography (DPL)
• Overlay Error in Double Patterning
• TCAD-Based Analysis
• Design-Level Analysis
• Conclusion
16UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
19UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Impact on Crosstalk-Induced Delay• Maximum coupling induced delay change
• PrimeTime-SI (Synopsys) is used to find a net that is mostly affected due to crosstalk• Temporal/functional filtering is performed• Selected net structure
• A net with relatively small length (~17um) can have >10% delay changes due to overlay error
21UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Outline
• Traditional BEOL Variation and Process
• Double Patterning Lithography (DPL)
• Overlay Error in Double Patterning
• TCAD-Based Analysis
• Design-Level Analysis
• Conclusions
22UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Conclusions• We provide a variational interconnect analysis technique for
double patterning lithography• We analyze interconnect variations due to overlay error in DPL• We augment previous work by providing both interconnect and chip-level RC-
extraction framework reflecting interconnect variation in a 45nm DPL process • We compare the impact of overlay error with traditional interconnect variations
• Summary of observations• Indirect alignment results in higher variation than direct alignment• In most analysis, impact of traditional variation source (width) is larger than
that of overlay error, however, overlay error is additive and non-negligible• Overlay error can cause up to 10% capacitance variation and 13% increase of
crosstalk-induced delay
• Ongoing/Future Work• Impact in the presence of metal fills• More in-depth analysis or remaining DPL process options• Process sensitivity analysis
23UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
BACKUP
24UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009
Misalignment Under M1 Layer (Standard-Cell)• Standard cell structure
• Assumptions• There exist a reference coordinate to measure misalignment• 10nm misalignment is a maximum displaced distance from the reference coordinate
• Possible moves• Poly1: left 10nm (L) / 0nm (C) /right 10nm (R)• Poly2: left 10nm (L) / 0nm (C) /right 10nm (R)• M1: left 10nm (L) / 0nm (C) /right 10nm (R)• Contact: left 10nm (L) / 0nm (C) /right 10nm (R)
• All Combinations = 3*3*3*3 = 81 cases• Naming convention for each testcase
• P1{direction}_P2{direction}_C{direction}_M{direction}• E.g., “P1C_P2L_CC_MC” means even gates move lef t by 10nm
(a) (b)
Original MP1 P2 C BASE
25UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009