1 SDR 2009 1.Como utilizar botões (4 botões). 2.Como utilizar interruptores (8 interruptores). 3.Como utilizar LEDs (8 LEDs). 4.Como utilizar displays (4 displays).
1SDR 2009
1. Como utilizar botões (4 botões).2. Como utilizar interruptores (8 interruptores).3. Como utilizar LEDs (8 LEDs).4. Como utilizar displays (4 displays).
SDR 2009 2
NET "Clock50In" TNM_NET = "Clock50In";TIMESPEC "TS_Clock50In" = PERIOD "Clock50In" 50 MHz HIGH 50 %;#-------------------- Clock --------------------------------------------------#NET "Clock" LOC = "B8";#-------------------- Buttons ------------------------------------------------#NET "Buttons<3>" LOC = "H13";NET "Buttons<2>" LOC = "E18";NET "Buttons<1>" LOC = "D18";NET "Buttons<0>" LOC = "B18"; #-------------------- Switches -----------------------------------------------#NET "Sw<7>" LOC = "R17";NET "Sw<6>" LOC = "N17";NET "Sw<5>" LOC = "L13";NET "Sw<4>" LOC = "L14";NET "Sw<3>" LOC = "K17";NET "Sw<2>" LOC = "K18";NET "Sw<1>" LOC = "H18";NET "Sw<0>" LOC = "G18";#-------------------- Leds ---------------------------------------------------#NET "Led<7>" LOC = "R4"; # (Leftmost)NET "Led<6>" LOC = "F4";NET "Led<5>" LOC = "P15";NET "Led<4>" LOC = "E17";NET "Led<3>" LOC = "K14";NET "Led<2>" LOC = "K15";NET "Led<1>" LOC = "J15";NET "Led<0>" LOC = "J14"; # (Rightmost)
SDR 2009 3
#-------------------- 7 Segment Displays -------------------------------------##NET "Segments<6>" LOC = "L18"; # a aaaa#NET "Segments<5>" LOC = "F18"; # b f b#NET "Segments<4>" LOC = "D17"; # c f b#NET "Segments<3>" LOC = "D16"; # d gggg#NET "Segments<2>" LOC = "G14"; # e e c#NET "Segments<1>" LOC = "J17"; # f e c#NET "Segments<0>" LOC = "H14"; # g dddd dp#NET "Segments<7>" LOC = "C17"; # dp##NET "Displays<3>" LOC = "F15";#NET "Displays<2>" LOC = "C18";#NET "Displays<1>" LOC = "H17";#NET "Displays<0>" LOC = "F17";
# … Comentários
SDR 2009 4
#-------------------- PS2 (Single Device) ------------------------------------#NET "PS2Data" LOC = "P11";NET "PS2Clock" LOC = "R12";#-------------------- VGA Monitor --------------------------------------------#NET "VGARed<2>" LOC = "R8";NET "VGARed<1>" LOC = "T8";NET "VGARed<0>" LOC = "R9";NET "VGAGreen<2>" LOC = "P6";NET "VGAGreen<1>" LOC = "P8";NET "VGAGreen<0>" LOC = "N8";NET "VGABlue<1>" LOC = "U4";NET "VGABlue<0>" LOC = "U5";NET "HSync" LOC = "T4"; # Horizontal SynchronizationNET "VSync" LOC = "U3"; # Vertical Synchronization
SDR 2009 5
4 janelasficheiros do projecto
Janela para erros e avisos
WorkSpace – interface com múltiplos documentos
Menu
SDR 2009 6
janelas podem ser abertas ou fechadas
Pode também reestabelecer janelas por omissão
SDR 2009 7
1 2
SDR 2009 8
3
SDR 2009 9
4
SDR 2009 10
Esquemático
Diagrama de estados de uma MEF
Código VHDL
SDR 2009 11
User Constraints File
Adicionar um ficheiro que já existe
Adicionar um ficheiro que já existe e copiar este ficheiro para a pasta do projecto
SDR 2009 12
5
out
SDR 2009 13
6 library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ForFirstProject is Port ( LED : in STD_LOGIC_VECTOR (7 downto 0); Buttons : in STD_LOGIC_VECTOR (3 downto 0); Sw : in STD_LOGIC_VECTOR (7 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 0); Displays : out STD_LOGIC_VECTOR (3 downto 0); Clock : in STD_LOGIC);end ForFirstProject;
architecture Behavioral of ForFirstProject is
begin
end Behavioral;
SDR 2009 14
7 Preparar código VHDL Comportamentalou
Estruturalou
Misto
SDR 2009 15SW: 7 6 5 4 3 2 1 0 3 2 1 0 Buttons
LED: 7 6 5 4 3 2 1 0
Displays: 3 2 1 0
Displays(3) – F15Displays(2) – C18Displays(1) – H17Displays(0) – F17
Buttons(3) – H13Buttons(2) – E18Buttons(1) – D18Buttons(0) – B18
SW(7) – R17SW(6) – N17SW(5) – L13SW(4) – L14SW(3) – K17SW(2) – K18SW(1) – H18SW(0) – G18
LED(7) – R4LED(6) – F4LED(5) – P15LED(4) – E17LED(3) – K14LED(2) – K15LED(1) – J15LED(0) – J14
Clock 50 MHz- B8
Segments(6) - L18
Segments(1) - J17 Segments(5) - F18
Segments(2) - G14 Segments(4) - D17
Segments(3) - D16
Segments(0) – H14 Segments(7) - C17
SDR 2009 16
Buttons(0) – RESETButtons(1) – Display 0001Buttons(2) – Display 0002Buttons(3) – Display SW(7 downto 4) + SW(3 downto 0)
Quando Buttons(3 downto 0) = 0000Leds = SWDisplay(3) = SWDisplays(2 downto 0) = 000.
SDR 2009 17
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ForFirstProject is Port ( LED : out STD_LOGIC_VECTOR (7 downto 0); Buttons : in STD_LOGIC_VECTOR (3 downto 0); Sw : in STD_LOGIC_VECTOR (7 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 0); Displays : out STD_LOGIC_VECTOR (3 downto 0); clock : in STD_LOGIC);end ForFirstProject;
SDR 2009 18
architecture Behavioral of ForFirstProject is
signal WhichDisplay : std_logic_vector(1 downto 0);signal div : std_logic_vector(22 downto 0);
signal Sum : STD_LOGIC_VECTOR(4 downto 0);
type rom_type is array (0 to 99) of std_logic_vector (7 downto 0);
constant ROM : rom_type :=("00000000","00000001","00000010","00000011","00000100","00000101","00000110","00000111","00001000", "00001001", "00010000","00010001","00010010","00010011","00010100","00010101","00010110","00010111","00011000", "00011001", "00100000","00100001","00100010","00100011","00100100","00100101","00100110","00100111","00101000", "00101001", "00110000","00110001","00110010","00110011","00110100","00110101","00110110","00110111","00111000", "00111001", "01000000","01000001","01000010","01000011","01000100","01000101","01000110","01000111","01001000", "01001001", "01010000","01010001","01010010","01010011","01010100","01010101","01010110","01010111","01011000", "01011001", "01100000","01100001","01100010","01100011","01100100","01100101","01100110","01100111","01101000", "01101001", "01110000","01110001","01110010","01110011","01110100","01110101","01110110","01110111","01111000", "01111001", "10000000","10000001","10000010","10000011","10000100","10000101","10000110","10000111","10001000", "10001001", "10010000","10010001","10010010","10010011","10010100","10010101","10010110","10010111","10011000", "10011001"
);
type display_ROM is array (0 to 15) of std_logic_vector (7 downto 0);signal index : integer range 0 to 15;constant convert_to_segments : display_ROM :=
("10000001","11001111","10010010","10000110","11001100","10100100","10100000","10001111", "10000000","10000100","10001000","10000000","10110001","10000001","10110000","10111000");
SDR 2009 19
begin
LED <= SW;
Sum <= ('0'&Sw(3 downto 0)) + ('0'&Sw(7 downto 4));
div<= div + 1 when rising_edge(clock);
WhichDisplay <= div(16 downto 15);
process(WhichDisplay) begin if WhichDisplay ="00" then displays <= "1110"; elsif WhichDisplay ="01" then displays <= "1101"; elsif WhichDisplay ="10" then displays <= "1011"; else displays <= "0111"; end if;end process;
20
process(clock)begin
if rising_edge(clock) then--LEDs <= ascii(7 downto 0);if WhichDisplay ="11" then
case Buttons(3 downto 0) iswhen "0001" => segments <= convert_to_segments(0);when "0010" => segments <= convert_to_segments(0);when "0100" => segments <= convert_to_segments(0);when "1000" => segments <= convert_to_segments(0);
when others => segments <= SW; end case;
elsif WhichDisplay ="10" thencase Buttons(3 downto 0) iswhen "0001" => segments <= convert_to_segments(0);when "0010" => segments <= convert_to_segments(0);when "0100" => segments <= convert_to_segments(0);when "1000" => segments <= convert_to_segments(0);
when others => segments <= SW; end case;
elsif WhichDisplay ="01" thencase Buttons(3 downto 0) iswhen "0001" => segments <= convert_to_segments(0);when "0010" => segments <= convert_to_segments(0);when "0100" => segments <= convert_to_segments(0);when "1000" => segments <=
convert_to_segments(conv_integer(ROM(conv_integer(sum))(7 downto 4)));when others => segments <= SW; end case;
SDR 2009 21
elsecase Buttons(3 downto 0) iswhen "0001" => segments <= convert_to_segments(0);when "0010" => segments <= convert_to_segments(1);when "0100" => segments <= convert_to_segments(2);when "1000" =>
segments <= convert_to_segments(conv_integer(ROM(conv_integer(sum))(3 downto 0)));when others => segments <= SW;
end case; end if;
else null;end if;
end process;
end Behavioral;
SDR 2009 22
Tarefa 1. Projectar um circuito para fazer contas aritméticas:
R1 = Op1 + Op2;R2 = Op1 - Op2;R3 = Op1 * Op2;R4 = Op1 / Op2; Onde:Op1 tem tamanho de 4 bits (use interruptores 3 downto 0 da placa)Op2 tem tamanho de 4 bits (use interruptores 7 downto 4 da placa)R1 deve aparecer nos displays quando carregar no botão0 da placaR2 deve aparecer nos displays quando carregar no botão1 da placaR3 deve aparecer nos displays quando carregar no botão2 da placaR4 deve aparecer nos displays quando carregar no botão3 da placa
LED(7 downto 0) deve mostrar os resultados em código binário
SDR 2009 23
VHDL suporta 1) adição (+), subtracção (-) e multiplicação (*). VHDL não suporta a divisão (/). Para implementar a divisão Op1(4 bits)/Op2(4 bits) pode utilizar tabelas ou instruções condicionais do tipo if e case ou subtracção múltipla
Exemplos:sum <= ("0000"&(Op1(3 downto 0)))+("0000"&(Op2(3 downto 0)));difference <= ("0000"&(Op1(3 downto 0)))-("0000"&(Op2(3 downto 0)))
when ("0000"&(Op1(3 downto 0)))>=("0000"&(Op2(3 downto 0))) else("0000"&(Op2(3 downto 0)))-("0000"&(Op1(3 downto 0)));
sign <= std_logic_vector(to_unsigned(character'pos(' '), 8)) when ("0000"&(Op1(3 downto 0)))>=("0000"&(Op2(3 downto 0))) elsestd_logic_vector(to_unsigned(character'pos('-'), 8));
sumMSB <= "0011" & ROM(conv_integer(sum))(7 downto 4);sumLSB <= "0011" & ROM(conv_integer(sum))(3 downto 0);DifLSB <= "0011" & ROM(conv_integer(difference))(3 downto 0);
8 bits4 + 4 = 8 bits 4 + 4 = 8 bits
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