1ASM Algorithmic State Machines (ASM) part 1. ASM2 Algorithmic State Machine (ASM) Our design methodologies do not scale well to real-world problems.

1ASM

Algorithmic State Machines(ASM)

part 1

ASM 2

Algorithmic State Machine (ASM)

• Our design methodologies do not scale well to real-world problems. Take this:

ASM 3

Algorithmic State Machine (ASM)

• Procedure for implementing a problem with a given piece of equipment.

• Define digital algorithmic solutions for hardware.

• Resembles a conventional flow chart but interpreted differently:

– ASM described the sequence as well as the timing of events.

– Adapted to specify the control sequence and data processing operations.

ASM 4

Control and datapath

• A digital system can be split into two components:

• Datapath unit: Manipulates data according to the system requirements.

• Control unit: Generates the signals for sequencing the operations in the data processor.

Figure 8.2 Control and datapath interaction

ASM 5

State box

Figure 8.3 ASM chart state box

ASM 6

Decision box

Figure 8.4 ASM chart decision box

ASM 7

Conditional box

ASM 8

ASM block

• One entrance path

• Any number of exit paths

• Describes the state of the systems during one clock-pulse interval.

• The operations within the state and the conditional boxes are executed with a common clock pulse while the system is in state S_0.

ASM 9

ASM chart – State diagram

ASM 10

• All the following operations occur simultaneously:

– A A+1

– If E == 1 then R 0

– Depending on E and F, the state is changed to S_1, S_2 or S_3.

Timing

ASM 11

Design problem

• Design a digital system with two flip-flops, E and F, and one 4-bit binary counter, A. The individual flip-flops of A are denoted by A4,A3,A2, and A1, with A4 holding the MSB. A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A3 and A4 determine the sequence of operations:

– If A3 == 0, E is cleared to 0 and the count continues.

– If A3 == 1, E is set to 1; then if A4 == 0, the count continues, but if A4 == 1, F is set to 1 on the next clock pulse and the system stops counting.

ASM 12

• Design a digital system with two flip-flops, E and F, and one 4-bit binary counter, A. The individual flip-flops of A are denoted by A4,A3,A2, and A1, with A4 holding the MSB. A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A3 and A4 determine the sequence of operations:

– If A3 == 0, E is cleared to 0 and the count continues.

– If A3 == 1, E is set to 1; then if A4 == 0, the count continues, but if A4 == 1, F is set to 1 on the next clock pulse and the system stops counting.

ASM Chart

ASM 13

Sequence of operations

T0111011

T2011011

000011

001101

000101

001001

A3=0, A4=1

010001

011110

010110

011010

A3=1, A4=0

000010

001100

000100

001000

T1A3=0, A4=0

010000

StateConditions

FEA1A2A3A4

Flip-flopsCounter

L1, L3 L2

L1

L2

L3

ASM 14

Sequence of operations

T0111011

T2011011

000011

001101

000101

001001

A3=0, A4=1

010001

011110

010110

011010

A3=1, A4=0

000010

00 1100

000100

001000

T1A3=0, A4=0

010000

StateConditions

FEA1A2A3A4

Flip-flopsCounter

ASM 15

The datapath

ASM 16

State diagram for control

ASM 17

State table

10000XXX11T2

0101111X10T1

0101001X10T1

01010X0X10T1

00110XX100T0

00100XX000T0

T2T1T0G1G0A4A3SG1G0

Present state

symbol

OutputsNextstate

InputsPresent state

ASM 18

State table

10000XXX11T2

0101111X10T1

0101001X10T1

01010X0X10T1

00110XX100T0

00100XX000T0

T2T1T0G0G1A4A3SG0G1

Present state

symbol

OutputsNextstate

InputsPresent state

• DG1 = T1 A3 A4

• DG0 = T0 S + T1

• T0 = G0’

• T1 = G1’ G0

• T2 = G1

ASM 19

20ASM

Algorithmic State Machines(ASM)

part 2

ASM 21

Binary multiplier

• How do we do multiplication by hand? In binary?

product101011011

---------------------------------

11101

00000

00000

11101

11101

---------------------------------

multiplier11001

multiplicand11101

ASM 22

Datapath for binary multiplier

• Sum only two binary numbers accumulating the partial sums in Register Q.

• Instead of shifting the multiplicand to the left, shift the product to the right

ASM 23

• P: the number of bits in the registers

ASM for binary multiplier

ASM 24

Initial state

Register B

Register A Register QC

10111

00000 100110

101

P

=1

Z=0

ASM 25

Q0 = 1; add B – first partial product

Register B


10111

10111 100110

100

P

=1

Z=0

10111 00000+------0 10111

ASM 26

Shift right CAQ

Register B


10111

01011 110010

100

P

=1

Z=0

ASM 27

Q0=1; add B – second partial product

Register B


10111

00010 110011

011

P

=1

Z=0

10111 01011+------1 00010

ASM 28

Shift right CAQ

Register B


10111

10001 011001

011

P

=1

Z=0

ASM 29

Q0=0; Shift right CAQ

Register B


10111

01000 101100

010

P

=0

Z=0

ASM 30

Q0=0; Shift right CAQ

Register B


10111

00100 010110

001

P

=0

Z=0

ASM 31

Q0=1; add B – fifth partial product

Register B


10111

11011 010110

000

P

=1

Z=0

10111 00100+------0 11011

ASM 32

Shift right CAQ

Register B


10111

01101 101010

000

P

=1

Z=1

ASM 33

Trace of the binary multiplication

Final product in AQ = 0110110101

10101011010Shift right CAQ

000110110Fifth partial product

10111Q0=1; add B

00101011001000Q0=0; shift right CAQ

01010110010000Q0=0; shift right CAQ


011000101Second partial product

10111Q0=1; add B


100101110First partial product

10111Q0 = 1; add B

10110011000000Multiplier in Q

PQACInitial conditions : B=10111

ASM 34

Control Logic

• Signals to be generated:– T0-T3– L (The Load signal for Register A, that allows the loading of the

output of the binary adder.

ASM 35

Control Circuit implemented with D flip-flops + Dec

ASM 36

Making the design of the control logic easier

Z=0

ASM 37

One FF per state

• T0 = T0 S’ + T3 Z• T1 = T0 S• T2 = T1 + T3 Z’• T3 = T2

Z=0

ASM 38

ASM with four control inputs

• Operations are left blank.

• We are interested in the design of the control part only.

• Four control inputs: w, x, y, z

• Four states: T0-T3 needs 2 flip-flops.

ASM 39

Using MUX’es to implement the control logic

• Two D flip-flops encode the state.

• The state is decoded into state signals T0-T3 by a decoder.

• The current state multiplexes the next state.

• Challenge: how to set the inputs of the MUX’es?

ASM 40

Multiplexer inputs

G2G2

y’z’1111

Y0111

y’z+y’z’

= y’

y+y’z’ = y+z’

y’z1011

yz1101

yz’0101

yzyz’+yz = y

y’0001

x’1110

x’1x0110

w1000

w0w’0000

MUX2MUX1G1G1

Multiplexer inputs

Input condition

s

Next State

Present state

ASM 41

The complete circuit

ASM 42

Count-of-Ones

• The system consists of two registers R1 and R2 and a flip-flop E.

• The system counts the number of 1’s in the number loaded into R1 and set R2 to that number.

• Shift one bit from R1 into E.• If E == 1 then R2++

• If Z = = 1 (that is R1 == 0) then stop.

• R2 is initialized to all 1’s. Why?

ASM 43

Datapath for Count-of-Ones

ASM 44

Multiplexer inputs

G2G2

E’1011

EE’E0111

11None1101

Z’0110

0Z’Z0010

S1000

S0S’0000

MUX2MUX1G1G1

Multiplexer inputs

Input condition

s

Next State

Present state

ASM 45

Control logic for Count-of-Ones

1ASM Algorithmic State Machines (ASM) part 1. ASM2 Algorithmic State Machine (ASM) Our design methodologies do not scale well to real-world problems.

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