High Electron Mobility Transistors (HEMTs) Active Region Source Drain Gate S. I. Buffer L g W g Active Region Source Drain Gate S. I. Buffer L g W g 0 2 4 6 8 10 12 14 16 0 200 400 600 800 1000 g m = 200 mS/mm Δ Δ ΔV G = 1 V V G = 2 V I D (mA/mm) V DS (V) Open channel Pinch off Similar to normally-on MOSFETs but no substrate doping. For accurate formula, refer to Sze: Physics of Semiconductor Devices d
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High Electron Mobility Transistors (HEMTs)
Active Region
Source DrainGate
S. I. Buffer
Lg
Wg
Active Region
Source DrainGate
S. I. Buffer
Lg
Wg
0 2 4 6 8 10 12 14 16
0
200
400
600
800
1000
gm = 200 mS/mm
∆∆∆∆VG = 1 V
VG = 2 V
I D (
mA
/mm
)
VDS
(V)
Open channel
Pinch off
Similar to normally-on MOSFETs but no substrate doping. For accurate formula, refer to Sze: Physics of Semiconductor Devices
d
Output Power Calculation (AC, not DC)
Minimize Vknee
Maximize Vbreakdown
Maximize Imax
Maximize nsµ or nsvs
14 (32 highest reported)1.4 Pout, max (W/mm)
1.2 (over 2 reported)0.6Imax (A/mm)
100 (over 200 reported for
small Lgd)
20Vbreakdown (V)
5 (~ Vpinchoff)1Vknee (V)
AlGaN/GaN HEMTGaAs pHEMT
Vbreakdown
Imax
IDS
VDSV
knee
BIAS POINT
A
B
Q
VSWING
I SWING
DSV
BIAS POINT
DSV
BIAS POINT
V
BIAS POINT Pout, max =8
VSWING ISWINGlinear
Slide # 3
Sample power calculations• Let Vknee be 4 V, and Vbd be 120 V, and Iswing be 120 mA for a 100
micron gate width device. Calculate the maximum output power in
dBm and in W/mm
– Solution: Total maximum output power = 1/8 (120 – 4) 120 mW
= 1740 mW. So output power in dBm = 10 log1740 = 32.405
dBm. Output power density is 1740 mW/100 micron = 17400
mW/mm = 17.4 W/mm.
• If the gain is 15 dB, what is the input power?
– Solution: 10 log (Pout/Pin) = 15 ⇒ Pout = Pin x 101.5 = Pin x 31.62
⇒Pin = 17.4/31.62 = 0.5502 W/mm.
• If the dc input power is also given then the Power-Added
Efficiency (PAE) can be calculated as (Pout – Pin)/Pdc
Slide # 4
Performance criteria for microwave transistors
• Output Power: Total microwave power available (W/mm)
• Gain: G = Pout/Pin, log G = Log Pout – Log Pin (Gain usually measured in dB, but Pin and Pout are in dBm)
• Ft : Maximum frequency of oscillation or the frequency at which the short circuit current gain is 1
• Fmax: The frequency at which the power gain is 1 for a perfectly matched load
• Power added efficiency (P.A.E): (Pout – Pin)/Pdc, Pin = input microwave power, Pdc = total dc power in at the gate and drain terminals.
• Linearity: The measure of gain against input signal level. High linearity means lower harmonic content in the output signal
• Noise Figure: SNRin/SNRout (usually expressed in dBm by taking the log)
• Stability: long term and short term operational stability
• Too much Si doping results in free electrons in graded layer, leading to parallel conduction
• Too little Si doping is not enough to remove holes• ~80% compensation puts fermi level in the middle of bandgap
holes
parallel conduction
Slide # 26
Design rules for AlGaN/GaN HEMTs:
Materials perspective• Thickness of the barrier layer: affects 2DEG
concentration and vertical gate field (which controls gate leakage current, VD, breakdown, and can also affect device degradation)
• Al composition of the barrier layer: affects 2DEG concentration and ∆EC, which confines the 2DEG
• Nucleation and buffer layer: affects dislocation density, and surface morphology (both affect mobility, one by charged line scattering and other by interface roughness scattering) and parasitic conduction.
• Substrate for epitaxial growth: affects the heat conductivity and ultimate output power performance as well as defect density, and parasitics.
Slide # 27
Transistor fabrication layout
Submicron Ni/Au
mushroom gate
defined by e-beamCl2 based ECR
mesa isolation
Air-bridge to connect
isolated source pads
1
2
34
Ti/Al/Ti/Au ohmic
contact annealed at
800˚C (0.3 to 0.6 Ω-mm)SEM photo showing air-bridge
over the gate metal (T-layout)SEM image of a submicron mushroom gate
Slide # 28
Design rules for AlGaN/GaN HEMTs:
Fabrication perspective
• The gate footprint and the cross-sectional area and width controls the frequency response
– Lg lower means fT goes up
– Cross-section and gate width control gate resistance (this is why mushroom gates are used)
• The gate drain spacing as well as gate footprint determines the breakdown voltage– Lg lower means VBR down
– Gate-drain spacing up means VBR up
• The geometry of the device also plays a role– The U-geometry device has 10 – 15 % lower gm, Idss due to self heating
2 x 125 µm U-gate
G
S
D
S
2 x 75 µm T-gate
S S
D
G
Slide # 29
Large periphery devices
• Larger periphery devices used for higher actual output power NOTpower density (usually more than 1 mm gate finger width)
• The fabrication processes are complicated as this involves air-bridging the source or the drain.
• Large periphery design issues: electrical and thermal
Parallel fingers Fishbone
Parallel fingers or fishbone layout for 12 x 125 µm devices:
Air bridges
Slide # 30
Design issues for large periphery devices
Electrical issues:
• The voltage drop along the gate length causes lower PAE
• Phase difference at the gate fingers reduce overall PAE
• Finite Ron reduces PAE. This becomes severe in presence of
trapping as Ron increases
Thermal issues:
• Device heating is a problem at higher output power, since
power wasted is also larger
• The maximum possible output power depends on the
conductivity of the substrates. SiC substrates are commonly
used. Thinned sapphire substrates have also been used.
• The number of gate fingers as well as the gate finger pitch
determine the maximum temperature rise in a device.
Slide # 31
DC characteristics of AlGaN/GaN HEMTs
• The negative slope in the dc characteristics of sapphire is either due to heating or trapping
• The dc characteristics are better for HEMTs fabricated on SiCthan on sapphire possibly because of reduced dislocation densityand increased thermal conductivity