A 14bit Low Power Capacitive SAR ADC for Bio-medical Application Ashish Soni 15210023 Under the Guidance of Prof. Nihar Ranjan Mohapatra Indian Institute of Technology Gandhinagar 07/05/2022 1
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
05/0
2/20
23
A 14bit Low Power Capacitive SAR ADC for
Bio-medical Application
Ashish Soni 15210023Under the Guidance of
Prof. Nihar Ranjan MohapatraIndian Institute of Technology Gandhinagar
1
05/0
2/20
23
Summary Specifications Introduction to ADC and its components Completed Work Future Work References
2
05/0
2/20
23
SpecificationsParameter Value
Number of Bits 14
Sampling Speed 0.5-5 kS/s
Power required 1-10 micro watt
Signal Swing 2v p-p (differential)
DNL (Differential Non Linearity) <0.5* LSB
INL (integral Non Linearity ) <LSB
Technology Node SCL 180nm
Power Supply 1.8V
Effective Number of Bits 14
SNR 86.04 dB (maximum)
3
05/0
2/20
23
Block Diagram of SAR ADC
4
05/0
2/20
23
Block Diagram of SAR ADC
Input and output pins in 14 bit SAR ADC5
05/0
2/20
23
Conventional SAR ADC At sampling phase, top plate of capacitors are charged to VCM and bottom
plates are charged to Vip and Vin. Comparison happens and MSB bit is set or reset depending on the
comparison. This repeats till end of conversion.
6
05/0
2/20
23
Conventional SAR ADC with 2 part splitting
This is the modified version of conventional ADC. In the same way we can split the DAC in to three parts to get power benefits.
Block Diagram of SAR ADC with 2 part splitting and a bridge capacitor
7
05/0
2/20
23
Monotonic switching based SAR ADC
Once the capacitor is charged using top plate sampling, no switching is required to make first comparison.
For each bit cycle, only one capacitor switching is required so minimum energy is required.
8
05/0
2/20
23
Sampling Switch• NMOS, PMOS, Transmission or Boot strapped switch can be used.• NMOS passes logic “zero” and PMOS passes logic “one” well but still there is
finite amount of charge injection in off state. • Transmission switch with proper sizing passes bot logic properly but charge
injection still exist. • A dummy capacitor with proper sizing can reduce the injection up to great
extent. • Linearity is important in all the above switches otherwise they will inject
some charge in off state. • The “On” state resistance limits the bandwidth of switch so we need switch
with less on resistance and less injection for high sampling rates. • Boot strapped switch can be used for high speed sampling with improved
linearity.
9
05/0
2/20
23
Variation of On resistance with Voltage in Transmission switch
10
05/0
2/20
23
Dynamic Latch Comparator• Latched Comparator without Pre-Amplifier popularly used for high speed and
moderate resolution requirements.• CLK Low, then VX+, VX-, VOUT+ and VOUT- are pre-charged to VDD. Which is used
to reset the comparator and this time both VOUT+ and VOUT- are at VDD.• CLK High, then VX+ and VX- starts decreasing and then VOUT+ and VOUT- starts
to fall by a rate depending on the magnitude of differential input.
11
05/0
2/20
23
Simulation Results of Latch Comparator
12
05/0
2/20
23
SAR Control Logic• The implemented SAR logic consist of a shift register and code register which is
implemented by two array of D-flip-flops (15+15=30).• Sample signal is an asynchronous set signal to the flip-flop to make MSB high at the start of the conversion cycle. In each clock cycle, one of the outputs in the shift register sets a flip flop in the code register.• The output of Flip Flop (Code Register) which is set by the shift register is used as the clock signal for the previous FF.
13
05/0
2/20
23
Simulation Result for SAR Logic
14
Comp output- 10011101100111
05/0
2/20
23
The Work completed till now Fully functional SAR ADC with 2 part split DAC has been implemented. Circuit has been tested for several test vectors. Managed to achieve power dissipation for worst case is around 2.5 micro
watt. Monotonic switching based SAR ADC is under development. The power dissipation in SAR ADC with 3 part split DAC is around 1.5 micro
watt.
15
05/0
2/20
23
The implemented circuit in Cadence Virtuoso
16
05/0
2/20
23
Timing analysis Sampling Interval = 200usec (5KS/sec) Resolution = 1/(2^13) = 122.04 uV
Vin+ = 900.13mv Vin- = 899.87mv ADC o/p= 10000000000001 (i/p is +ve so D13 is 1 and i/p difference is > 1 LSB so D0 is high)
17
05/0
2/20
23
Results Circuit Power (micro watt)
Digital Circuits (including clock generator)
0.397
DAC circuit 2.07
Digital SAR Logic 0.172
Comparator 0.0287
Total 2.667
18
05/0
2/20
23
Work to be done !!!!!! Signal to Noise ratio analysis of completed 2 part split DAC. DNL and INL analysis of SAR ADC with 2 part split DAC circuit. Looking for more power reduction without compromising the resolution. SAR ADC with 3 part split DAC is to be implemented for power benefits. Layout of 2 part split DAC is to be completed. Implementation of SAR ADC using Monotonic Capacitive DAC for reduced
power. (81% power saving was reported in the literature as compare to conventional SAR ADC).
19
05/0
2/20
23
References Design and analysis of an ultra-low-power double-tail latched comparator
for bio-medical applications Parvin Bahmanyar, Mohammad Maymandi-Nejad,Saied Hosseini-Khayat,Mladen Berekovic2.
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010.
Energy-efficient charge-recovery switching scheme for dual-capacitive arrays SAR ADC . Y. Li, Z. Zhang and Y. Lian, ELECTRONICS LETTERS 28th February 2013 Vol. 49 No. 5
Improved dual-capacitive arrays DAC architecture for SAR ADC Dong Li, Qiao Meng and Fei Li.
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC , IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007.
20