Swift and Roosta 1 144_C4 / MAPLD04 Tradeoffs in Flight-Design Upset Mitigation in State- of-the-Art FPGAs Hardened By Design vs. Design-Level Hardening Gary M. Swift and Ramin Roosta Jet Propulsion Laboratory / California Institute of Technology The research done in this paper was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under contract with the National Aeronautics and Space Administration (NASA) and was partially sponsored by the NASA Electronic Parts and Packaging Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology.
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144_C4 / MAPLD04Swift and Roosta1 Tradeoffs in Flight-Design Upset Mitigation in State-of-the-Art FPGAs Hardened By Design vs. Design-Level Hardening Gary.
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Swift and Roosta 1 144_C4 / MAPLD04
Tradeoffs in Flight-Design Upset Mitigation in State-of-the-Art FPGAs
Hardened By Designvs.
Design-Level Hardening
Gary M. Swift and Ramin RoostaJet Propulsion Laboratory / California Institute of Technology
The research done in this paper was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under contract with the National Aeronautics and Space Administration (NASA) and was partially sponsored by the NASA Electronic Parts and Packaging Program.
Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology.
Swift and Roosta 2 144_C4 / MAPLD04
In the beginning was Actel …
• Leveraging from a commercial product line ONO anti-fuse based one-time programmable
(OTP)
• “beginning” = 1993 Reference:
Katz, R.; Barto, R.; McKerracher, P.; Carkhuff, B.; Koga, R.; “SEU hardening of field programmable gate arrays (FPGAs) for space applications and device characterization,” IEEE Transactions on Nuclear Science, Dec. 1994
Swift and Roosta 3 144_C4 / MAPLD04
Later, Xilinx
Leveraging from a commercial product line SRAM based reconfigurable
• ATMR upsets from: Transients that are clocked into storage Clock tree hits
• Xilinx FPGAs have a small susceptibility to two types of SEFIs Reset (sometimes only partial) Disable scrub port
• XTMR in combination with scrubbing can lower system upset rates below the SEFI rate
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Rate Comparison
GCR = Galactic Cosmic Ray background (interplanetary space)
almost identical to geosynchronous orbit
• Actel• Dominated by transients
• Roughly one system error per thousand years (GCRmin)
• Xilinx• Dominated by SEFI rate
• Expect one SEFI per ~65 years in GCRmin
• Expect one system error ~5-20x less often
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CONCLUSIONSFor the present –
Both can achieve very acceptable radiation tolerance
Actel wins on:▫ Less burden on the designer▫ No auxiliary components▫ Lower SEFI susceptibility
Xilinx wins on:▫ Designer control of the resources vs. hardness tradeoff▫ On-chip feature set▫ Re-configurability
Competition is good.
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AcronymsFPGA - Field Programmable Gate Array ASIC - Application Specific Integrated CircuitSEU - Single Event UpsetSEFI - Single Event Functionality InterruptTMR - Triple Modular RedundancyATMR - Actel-style TMRXTMR - Xilinx-style TMRLET - Linear Energy Transfer (proportional to deposited
charge per micron for a heavy ion strike on an active node)
GCRmin - Galactic Cosmic Ray background (highest during “solar minimum” period of ~11-yr cycle of
sunspots)MER - Mars Exploration Rovers
(i.e., Spirit and Opportunity)
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Additional References
[1] J.J. Wang, W. Wong, S. Wolday, B. Cronquist, J. McCollum, R. Katz, I. Kleyner, “Single event upset and hardening in 0.15 antifuse-based field programmable gate array,” IEEE Transactions on Nuclear Science, Dec. 2003
[2] Jih-Jong Wang, R.B. Katz, F. Dhaoui, J.L. McCollum, W. Wong, B.E. Cronquist, R.T. Lambertson, E. Hamdy, I. Kleyner, W. Parker, “Clock buffer circuit soft errors in antifuse-based field programmable gate arrays,” IEEE Transactions on Nuclear Science, Dec. 2000
[3] R. Katz, J.J. Wang, R. Koga, K.A. LaBel, J. McCollum, R. Brown, R.A. Reed, B. Cronquist, S. Crain, T. Scott, W. Paolini, B. Sin, “Current radiation issues for programmable elements and devices,” IEEE Transactions on Nuclear Science, Dec. 1998