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2.1 Embedded Systems

An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, often with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. Embedded systems control many of the common devices in use today.

Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economics of scale. Physically, embedded systems range from portable devices such as digital watches and mp4 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power stations. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure.

In general, "embedded system" is not an exactly defined term, as many systems have some element of programmability. For example, handheld computers share some elements with embedded systems — such as the operating systems and microprocessors which power them — but are not truly embedded systems, because they allow different applications to be loaded and peripherals to be connected

2.2 Characteristics

1. Embedded systems are designed to do some specific task, rather than be a general-purpose computer for multiple tasks. Some also have real-time performance constraints that must be met, for reasons such as safety and usability; others may have low or no performance requirements, allowing the system hardware to be simplified to reduce costs.



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2. Embedded systems are not always standalone devices. Many embedded systems consist of small, computerized parts within a larger device that serves a more general purpose. For example, the features an embedded system for tuning the strings, but the overall purpose of the Robot Guitar is, of course, to play music. Similarly, an embedded system in automobiles provides a specific function as a subsystem of the car itself.

3. The program instructions written for embedded systems are referred to as firmware, and are stored in read-only memory or flash memory chips. They run with limited computer hardware resources: little memory, small or non-existent keyboard and/or screen.

Figure 2.1 A typical embedded system block diagram

2.3 Micro Controllers

The micro controller, nowadays, is an indispensable device for electrical/electronic engineers and also

for technicians in the area, because of its versatility and its enormous application. .Born of parallel

developments in computer architecture and integrated circuit fabrication ,the microprocessor or

computer on chip first becomes a commercial reality in 1971.with the introduction of the 4 bit 4004 by a

small, unknown company by the name of Intel corporation. Other, well established, semiconductor firms

soon followed Intel’s pioneering technology so that by the late 1970’s we could choose from a half

dozen or so micro processor typThe 1970s also saw the growth of the number of personal computer

users from a Handful of hobbyists and hackers to millions of business, industrial, governmental, defense,

and educational and private users now enjoying the advantages of inexpensive computing.

A bye product of microprocessor development was the micro controller. The same fabrication

techniques and programming concepts that make possible general-purpose microprocessor also yielded

the micro controller.

Among the applications of a micro controller we can mention industrial automation, mobile

telephones, radios, microwave ovens and VCRs. Besides, the present trend in digital electronics is

toward restricting to micro controllers and chips that concentrate a great quantity of logical circuits, like

PLDs (Programmable Logic Devices) and GALs (Gate Array Logic). In dedicated systems, the micro

controller is the best solution, because it is cheap and easy to manage.

2.6 Communication:

Communication refers to the sending, receiving and processing of information by electric

means. As such, it started with wire telegraphy in the early 80’s, developing with telephony and radio

some decades later. Radio communication became the most widely used and refined through the

invention of and use of transistor, integrated circuit, and other semi-conductor devices. Most recently,

the use of satellites and fiber optics has made communication even more wide spread, with an

increasing emphasis on computer and other data communications.

A modern communications system is first concerned with the sorting, processing and storing of

information before its transmission. The actual transmission then follows, with further processing and

the filtering of noise. Finally we have reception, which may include processing steps such as decoding,

storage and interpretation. In this context, forms of communications include radio, telephony and

telegraphy, broadcast, point to point and mobile communications (commercial and military), computer

communications, radar, radio telemetry and radio aids to navigation. It is also important to consider the

human factors influencing a particular system, since they can always affect its design, planning and use.

Wireless communication has become an important feature for commercial products and a

popular research topic within the last ten years. There are now more mobile phone subscriptions than

wired-line subscriptions. Lately, one area of commercial interest has been low-cost, low-power, and

short-distance wireless communication used for personal wireless networks." Technology advancements

are providing smaller and more cost effective devices for integrating computational processing, wireless

communication, and a host of other functionalities. These embedded communications devices will be

integrated into applications ranging from homeland security to industry automation and monitoring.

They will also enable custom tailored engineering solutions, creating a revolutionary way of

disseminating and processing information. With new technologies and devices come new business

activities, and the need for employees in these technological areas. Engineers who have knowledge of

embedded systems and wireless communications will be in high demand. Unfortunately, there are few

adorable environments available for development and classroom use, so students often do not learn

about these technologies during hands-on lab exercises. The communication mediums were twisted

pair, optical fiber, infrared, and generally wireless radio.

2.7 IR Remote Theory

The cheapest way to remotely control a device within a visible range is via Infra-Red light. Almost all audio and video equipment can be controlled this way nowadays. Due to this wide spread use the required components are quite cheap, thus making it ideal for us hobbyists to use IR control for our own projects.

IR sensor is the combination of IR LED with PHOTO DIODE. After this combination we are connecting the DARLINGTON PAIR TRANSISTOR. End of the IR sensor we have to connect a NOT gate for the inverting purpose means low input have corresponding low output. At last this entire connector is connected to any one external interrupt to generating the interruption of the main program.

Infra-Red actually is normal light with a particular colour. We humans can't see this

colour because its wave length of 950nm is below the visible spectrum. That's one of the

reasons why IR is chosen for remote control purposes, we want to use it but we're not

interested in seeing it. Another reason is because IR LEDs are quite easy to make, and therefore

can be very cheap.

IR LED wave length range 1.6m to 2.4m. Materials used for IR LED are InSB, Ge,Si, GaAs, CdSe .

These IR s are not visible range for observation purpose we have to connect LED s are not.

Problem formulation

The problem with the traffic system is that for every minute the vehicles at the 4-way road will be heavy and the traffic lights shall be changed to each side for some fixed time. Even though there are no vehicles at particular side, the traffic signals will glow for given fixed time.Due to that there is time waste process. Due to this other side vehicles have to wait for the time to complete the process. So to reduce the wastage of time, we can implement the system that controls the traffic based on the heavy flow of vehicles at any particular side. With this system, we shall count the number of vehicles at each side at the junction and give th path to the particular side which has heavy flow of vehicles and keep remaining stop position. So that for this to count the number of vehicles at side of the junction, we shall use IR technology.

System Specification

4.1 89S52 Micro Controller

Features:

• Compatible with MCS-51® Products

• 8K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 1000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-

system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile

memory technology and is compatible with the industry- standard 80C51 instruction set and pin out.

The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional

nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable

Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-

flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32

I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level

interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the

AT89S52 is designed with static logic for operation down to zero frequency and supports two software

selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,

serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM

contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware

reset.

Pin Description

VCC: Pin 40 provides supply voltage to the chip. The voltage source is + 5V.

GND: Pin 20 provides ground.

Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL

inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.

Port 0 can also be configured to be the multiplexed low order address/data bus during accesses

to external program and data memory. In this mode, P0 has internal pull ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes

during program verification. External pull ups are required during program verification.

Port 1:Port 1 is an 8-bit bidirectional I/O port with internal pull ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull

ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source

current (IIL) because of the internal pull ups.

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input

(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following

table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2:Port 2 is an 8-bit bidirectional I/O port with internal pull ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-


current (IIL) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and

during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application,

Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that

uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash

programming and verification.

Port 3:Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-


current (IIL) because of the pull-ups.

Port 3 also serves the functions of various special features of the AT89S52, as shown in the

following table.

Port 3 also receives some control signals for Flash programming and verification.

RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the

device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR

AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET

HIGH out feature is enabled.

ALE/PROG:Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG) during flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may

be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during

each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting

the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN:Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52

is executing code from external program memory, PSEN is activated twice each machine cycle, except

that two PSEN activations are skipped during each access to external data memory.

EA/VPP:External access enable. EA must be strapped to GND in order to enable the device to fetch code

from external program memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should

be strapped to VCC for internal program executions. This pin also receives the 12-volt programming

enable voltage (VPP) during Flash programming.

XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2:Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be

implemented on the chip. Read accesses to these addresses will in general return random data, and

write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future

products to invoke new features. In that case, the reset or inactive values of the new bits will always be

0.

Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and

T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) is the Capture/Reload

registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set

for each of the six interrupt sources in the IP register.

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks

of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-

85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the

DPS bit to the appropriate value before accessing the respective Data Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1”

during power up. It can be set and rest under software control and is not affected by reset.

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes

each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the

AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to

internal memory and fetches to addresses 2000H through FFFFH are to external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel

address space to the Special Function Registers. This means that the upper 128 bytes have the same

addresses as the SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used in

the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space.

Instructions which use direct addressing access of the SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H

(which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the

following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address

0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data

RAM are available as stack space.

Watchdog Timer

(One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR.

The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and

0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will

increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on

the external clock frequency. There is no way to disable the WDT except through reset (either hardware

reset or WDT overflow (reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST

pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR

location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to

WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this

will reset the device. When the WDT is enabled, it will increment every machine cycle while the

oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To

reset the WDT the user must write 01EH and 0E1H to WDTRST. DTRST is a write-only register. The WDT

counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the

RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it

should be serviced in those sections of code that will periodically be executed within the time required

to prevent a WDT reset.

WDT during Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-

down mode, the user does not need to service the WDT. There are two methods of exiting Power-down

mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering

Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur

as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly

different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is

brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt

pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be

reset during the interrupt service for the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best

to reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the

WDT continues to count if enabled. The WDT keeps counting during IDLE WDIDLE bit = 0) as the default

state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set

up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit

enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

UART

Serial data communication uses two methods, asynchronous and synchronous. The synchronous

method transfers a block of data (characters ) at a time, while the asynchronous method transfers a

single byte at a time. It is possible to write software to use either of these methods, but programs can be

tedious and long. For this reason, there are special IC chips made by the manufacturers for the serial

data communications. These chips are commonly referred to as UART ( universal asynchronous receiver-

transmitter) and USART ( universal synchronous receiver-transmitter). The 8052 has built-in UART.

Timer 0

The 16-bit register of timer 0 is accessed as low byte and high byte. The low byte register is called TL0

( Timer 0 low byte) and the high byte register is referred to as TH0 ( Timer 0 high byte). These registers

can be accessed like any other registers , such as A,B,R0,R1,R2 etc. for example the instruction “MOV

TL0,#4FH” moves the value 4FH into TL0, the low byte of Timer 0. These registers can also be read like

any other register. For example, “MOV R5,TH0” saves TH0 ( high byte of Timer 0) in R5.

Timer1

Timer 1 is also 16 bits and its 16-bit register is split into two bytes, referred to as TL1 (Timer 1 low byte )

and TH1 ( Timer 1 high byte). These registers are accessible in the same way as the registers of Timer 0.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The

type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three

operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are

selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In

the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists

of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

In the Counter function, the register is incremented in esponse to a 1-to-0 transition at its corresponding

external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle.

When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The

new count value appears in the register during S3P1 of the cycle following the one in which the

transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-

to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level

is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a

16-bit timer or counter which upon overflow sets bit TF2 in T2CON.

This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation,

but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be

captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in

T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in

Figure 5.

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload

mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see

Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set,

Timer 2 can count up or down, depending on the value of the T2EX pin.

options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the

TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value

in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by

software. If EXEN2 = 1, a 16-bit reload can be Figure 6 shows Timer 2 automatically counting up when

DCEN=0. In this mode, two triggered either by an overflow or by a 1-to-0 transition at external input

T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if

enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 6. In this mode,

the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will

overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and

RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer

2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L.

The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers .The EXF2 bit

toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this

operating mode, EXF2 does not flag an interrupt.

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2).

Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or

transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its

baud rate generator mode, as shown in Figure 8. The baud rate generator mode is similar to the auto-

reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value

in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are

determined by Timer 2’s overflow rate according to the following equation.

The Timer can be configured for either timer or counter operation. In most applications, it is

configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as

a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator

frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator

frequency). The baud rate formula is given below.

Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned

integer. Timer 2 as a baud rate generator is shown in Figure 8. This figure is valid only if RCLK or TCLK = 1

in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that

if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H,

RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an

extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate

generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is

incremented every state time, and the results of a read or write may not be accurate. The RCAP2

registers may be read but should not be written to; because a write might overlap a reload and cause

write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or

RCAP2 registers.

Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three

timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in

Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a

bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at

once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5

is also unimplemented. User software should not write 1s to these bit positions, since they may be used

in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register

T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the

service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and

that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2

of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.

However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer

overflows.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured

for use as an on-chip oscillator, as shown in Figure 11. Either a quartz

crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2

should be left unconnected while XTAL1 is driven, as shown in Figure 12. There are no requirements on

the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a

divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be

observed. Oscillator connections

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is

invoked by software. The content of the on-chip RAM and all the special

functions registers remain unchanged during this mode. The idle mode can be terminated by any

enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset,

the device normally resumes program execution from where it left off, up to two machine cycles before

the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this

event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to

a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle

mode should not write to a port pin or to external memory.

Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the

last instruction executed. The on-chip RAM and Special Function Registers

retain their values until the Power-down mode is terminated. Exit from Power-down mode can be

initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but

does not change the on-chip RAM. The reset should not be activated before VCC is restored to its

normal operating level and must be held active long enough to allow the oscillator to restart and

stabilize.

Status of External Pins during Idle and Power-down Modes

4. MAX 232

RS 232 CONVERTER (MAX 232N) Serial Port:

This is the device, which is used to convert TTL/RS232 vice versa.

RS-232Protocol

In telecommunications, RS-232 is a standard for serial binary data interconnection

between a DTE (Data terminal equipment) and a DCE (Data Circuit-terminating Equipment). It

is commonly used in computer serial ports. The RS-232 standard defines the voltage levels that

correspond to logical one and logical zero levels. Valid signals are plus or minus 3 to 15 volts.

The range near zero volts is not a valid RS-232 level; logic one is defined as a negative voltage,

the signal condition is called marking, and has the functional significance of OFF.

RS-232 was created for one purpose, to interface between Data Terminal Equipment

(DTE) and Data Communications Equipment (DCE) employing serial binary data interchange.

So as stated the DTE is the terminal or computer and the DCE is the modem or other

communications device.

RS-232 pin-outs for IBM compatible computers are shown below. There are two

configurations that are typically used: one for a 9-pin connector and the other for a 25-pin

connector.

Fig. 4.1 Pin Description of MAX 232

Logic Diagram (Positive Logic)

Fig. 4.2 Logic Diagram of MAX232

Fig. 4.3 Operating Characteristics

Vital role of MAX232 is to convert RS232 logic to TTL logic and vice versa.

2. TECHNOLOGY USED

2.1 GSM modem (900/1800 MHz):Semens GSM/GPRS smart modem is a multi-functional, ready to use, rugged unit that

can be embedded or plugged into any application. The smart modem can be controlled and

customized to various levels by using the standard AT commands. The modem is fully type-

approved, it can speed up the operational time with full range of voice, data, fax and short

messages (point to point and cell broadcast), the modem also supports GPRS (class 2*) for

spontaneous data transfer.

LED Status Indicator

The LED will indicate different status of the modem:

OFF Modem Switched off

ON Modem is connecting to the network

Flashing Slowly Modem is in idle mode

Flashing rapidly Modem is in transmission/communication

(GSM only)

2.1.1 History of GSMDuring the early 1980s, analog cellular telephone systems were experiencing rapid

growth in Europe, particularly in Scandinavia and the United Kingdom, but also in France and

Germany. Each country developed its own system, which was incompatible with everyone else's

in equipment and operation. This was an undesirable situation, because not only was the mobile

equipment limited to operation within national boundaries, which in a unified Europe were

increasingly unimportant, but there was also a very limited market for each type of equipment,

so economies of scale and the subsequent savings could not be realized.

The Europeans realized this early on, and in 1982 the Conference of European Posts and

Telegraphs (CEPT) formed a study group called the Group Special Mobile (GSM) to study and

develop a pan-European public land mobile system. The proposed system had to meet certain

criteria:

Good subjective speech quality

Low terminal and service cost

Support for international roaming

Ability to support handheld terminals

Support for range of new services and facilities

Spectral efficiency

ISDN compatibility

In 1989, GSM responsibility was transferred to the European Telecommunication

Standards Institute (ETSI), and phase I of the GSM specifications were published in 1990.

Commercial service was started in mid-1991, and by 1993 there were 36 GSM networks in 22

countries. Although standardized in Europe, GSM is not only a European standard. Over 200

GSM networks (including DCS1800 and PCS1900) are operational in 110 countries around the

world. In the beginning of 1994, there were 1.3 million subscribers worldwide, which had grown

to more than 55 million by October 1997. With North America making a delayed entry into the

GSM field with a derivative of GSM called PCS1900, GSM systems exist on every continent,

and the acronym GSM now aptly stands for Global System for Mobile communications.

The developers of GSM chose an unproven (at the time) digital system, as opposed to the

then-standard analog cellular systems like AMPS in the United States and TACS in the United

Kingdom. They had faith that advancements in compression algorithms and digital signal

processors would allow the fulfillment of the original criteria and the continual improvement of

the system in terms of quality and cost. The over 8000 pages of GSM recommendations try to

allow flexibility and competitive innovation among suppliers, but provide enough

standardization to guarantee proper inter-working between the components of the system. This is

done by providing functional and interface descriptions for each of the functional entities

defined in the system.

2.1.2 Services provided by GSMFrom the beginning, the planners of GSM wanted ISDN compatibility in terms of the

services offered and the control signalling used. However, radio transmission limitations, in

terms of bandwidth and cost, do not allow the standard ISDN B-channel bit rate of 64 kbps to be

practically achieved.

Using the ITU-T definitions, telecommunication services can be divided into bearer

services, teleservices, and supplementary services. The most basic teleservice supported by GSM

is telephony. As with all other communications, speech is digitally encoded and transmitted

through the GSM network as a digital stream. There is also an emergency service, where the

nearest emergency-service provider is notified by dialing three digits (similar to 911).

A variety of data services is offered. GSM users can send and receive data, at rates up to

9600 bps, to users on POTS (Plain Old Telephone Service), ISDN, Packet Switched Public Data

Networks, and Circuit Switched Public Data Networks using a variety of access methods and

protocols, such as X.25 or X.32. Since GSM is a digital network, a modem is not required

between the user and GSM network, although an audio modem is required inside the GSM

network to interwork with POTS.

Other data services include Group 3 facsimile, as described in ITU-T recommendation

T.30, which is supported by use of an appropriate fax adaptor. A unique feature of GSM, not

found in older analog systems, is the Short Message Service (SMS). Short Message Service

(SMS)

Short Message Service (SMS) is popular among mobile phone users as a cheap and

convenient method of communicating. Therefore, SMS technology is a common feature with all

mobile network service providers. They provide many information and services via SMS such as

latest news updates, stock information, and various entertaining applications stuffs. Some

common examples are

1. Send and receive confidential information of bank accounts,

2. Enhance security in households and vehicles,

3. Monitoring physical quantities remotely,

4. Transfer data between remote locations,

5. Alerting method, and

6. Information distributing system and many more...

In order to use SMS for various applications it is necessary to understand their data

communication methods and protocols since several unnecessary information needed to be

filtered out. Filtering and manipulating hardware assistance is very important and this could be

performed using a microcontroller.

Since the use of SMS technology is a cheap, convenient and flexible way of conveying

data, researchers are trying to apply this technology in many different areas that were not

provided by service providers at present. One of such areas that the SMS technology could be

used as a cost effective and more flexible way will be remote monitoring and controlling.

SMS is a bidirectional service for short alphanumeric (up to 160 bytes) messages.

Messages are transported in a store-and-forward fashion. For point-to-point SMS, a message can

be sent to another subscriber to the service, and an acknowledgement of receipt is provided to the

sender. SMS can also be used in a cell-broadcast mode, for sending messages such as traffic

updates or news updates. Messages can also be stored in the SIM card for later retrieval.

Supplementary services are provided on top of tele-services or bearer services. In the

current (Phase I) specifications, they include several forms of call forward (such as call

forwarding when the mobile subscriber is unreachable by the network), and call barring of

outgoing or incoming calls, for example when roaming in another country. Many additional

supplementary services will be provided in the Phase 2 specifications, such as caller

identification, call waiting, multi-party conversations.

2.1.3 AT Commands Used:SIM Insertion, SIM Removal

SIM card Insertion and Removal procedures are supported. There are software functions

relying on positive reading of the hardware SIM detect pin. This pin state (open/closed) is

permanently monitored. When the SIM detect pin indicates that a card is present in the SIM

connector, the product tries to set up a logical SIM session. The logical SIM session will be set

up or not depending on whether the detected card is a SIM Card or not. The AT+CPIN?

Command delivers the following responses:

If the SIM detect pin indicates “absent”, the response to AT+CPIN? is “+CME ERROR

10” (SIM not inserted).

If the SIM detect pin indicates “present”, and the inserted Card is a SIM Card, the

response to AT+CPIN? is “+CPIN: xxx” depending on SIM PIN state.

If the SIM detect pin indicates “present”, and the inserted Card is not a SIM Card, the

response to AT+CPIN? is CME ERROR 10.

These last two states are not given immediately due to background initialization.

Between the hardware SIM detect pin indicating “present” and the previous results the

AT+CPIN? sends “+CME ERROR: 515” (Please wait, init in progress).

When the SIM detect pin indicates card absence, and if a SIM Card was previously

inserted, an IMSI detach procedure is performed, all user data is removed from the product

(Phonebooks, SMS etc.). The product then switches to emergency mode.

Call Control commands Dial command D

Description:

The ATD command is used to set a voice, data or fax call. As per GSM 02.30, the dial

command also controls supplementary services. For a data or a fax call, the application sends the

following ASCII string to the product (the bearer must be previously selected with the +CBST

command):

ATD<nb> where <nb> is the destination phone number.

For a voice call, the application sends the following ASCII string to the product: (the

bearer may be selected previously, if not a default bearer is used).

ATD<nb>; where <nb> is the destination phone number.

Please note that for an international number, the local international prefix does not need

to be set (usually 00) but does need to be replaced by the ‘+’ character.

Example: to set up a voice call to Wavecom offices from another country, the AT

command is: “ATD+33146290800;”

Note that some countries may have specific numbering rules for their GSM handset

numbering.

The response to the ATD command is one of the following:

Verbose result code Numeric code Description with ATV0 set

Ok 0 If the call succeeds, for

voice call only

CONNECT <speed> 10, 11, 12, If the call succeeds, for data

calls only,

13, 14, 15 <speed> takes the value

negotiated by the product.

Busy 7 If the called party I is

Already in communication

NO ANSWER 8 If no hang up is detected

after a fixed network time-

out

NO CARRIER 3 Call setup failed or remote

user release

Echo EDescription:

This command is used to determine whether or not the modem echoes characters

received by an external application (DTE).

Syntax:Command Syntax: ATE

COMMAND POSSIBLE RESPONSES

ATE0

Note: Characters are not echoed

OK

Note: Done

ATE1

Note: Characters are echoed

OK

Note: Done

Select message service +CSMS

Description:

The supported services are originated (SMS-MO) and terminated short message

(SMSMT) + Cell Broadcast Message (SMS-CB) services.

Syntax:

Command Syntax: AT+CSMS=<service>


AT+CSMS=0 +CSMS: 1,1,1

OK

AT+CSMS=1 +CSMS: 1,1,1

Preferred Message Format +CMGF

Description:

The message formats supported are text mode and PDU mode. In PDU mode, a complete

SMS Message including all header information is given as a binary string (in hexadecimal

format). Therefore, only the following set of characters is allowed:

{‘0’,’1’,’2’,’3’,’4’,’5’,’6’,’7’,’8’,’9’, ‘A’, ‘B’,’C’,’D’,’E’,’F’}. Each pair or characters is

converted to a byte (e.g.: ‘41’ is converted to the ASCII character ‘A’, whose ASCII code is0x41

or 65). In Text mode, all commands and responses are in ASCII characters.

Syntax:

Command Syntax: AT+CMGF


AT+CMGF=0

Set PDU mode

OK

AT+CMGF=1

Set TEXT mode

OK

New message indication +CNMI

Description:

This command selects the procedure for message reception from the network.

Syntax:

Command Syntax: AT+CNMI=<mode>,<mt>,<bm>,<ds>,<bfr>


AT+CNMI=2,1,0,0,0 OK

AT+CMTI : “SM”,1 Note: message received

AT+CNMI=2,2,0,0,0

+CMT“123456”,”98/10/01,

12:3000+00”,129,4,32,240,

“15379”,129,5<CR><LF>

OK

READ MESSAGE +CMGR

Description:

This command allows the application to read stored messages.

Syntax:

Command Syntax: AT+CMGR=<index>

A message read with status “REC UNREAD” will be updated in memory with the status

“REC READ”.

Send message +CMGS

Description:

The <address> field is the address of the terminal to which the message is sent. To send

he message, simply type, <ctrl-Z> character (ASCII 26). The text can contain all existing

characters except <ctrl-Z> and <ESC> (ASCII 27).

This command can be aborted using the <ESC> character when entering text. In PDU

mode, only hexadecimal characters are used (‘0’…’9’,’A’…’F’).

Syntax:

Command syntax in text mode:

AT+CMGS= <da> [ ,<toda> ] <CR> text is entered <ctrl-Z / ESC >


AT+CMGS=”+33146290800”<CR>

Please call me soon, Fred. <ctrl-Z>

Note: Send a message in text mode

+CMGS: <mr>

OK

Note: Successful transmission

The message reference, <mr>, which is returned to the application is allocated by the

product. This number begins with 0 and is incremented by one for each outgoing

message(successful and failure cases); it is cyclic on one byte (0 follows 255).

Vital role of GSM modem in ‘vehicle position tracking using GPS and GSM receiver

with license’ is used to transmit and receive the SMS.

REGULATOR: Voltage regulator ICs is available with fixed (typically 5, 12 and 15V) or variable output

voltages. The maximum current they can pass also rates them. Negative voltage regulators are available,

mainly for use in dual supplies. Most regulators include some automatic protection from excessive

current ('overload protection') and overheating ('thermal protection'). Many of the fixed voltage

regulators ICs have 3 leads and look like power transistors, such as the 7805 +5V 1A regulator shown on

the right. The LM7805 is simple to use. You simply connect the positive lead of your unregulated DC

power supply (anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the

Common pin and then when you turn on the power, you get a 5 volt supply from the output pin.

Fig 6.1.6 A Three Terminal Voltage Regulator

78XX:

The Bay Linear LM78XX is integrated linear positive regulator with three terminals. The LM78XX

offer several fixed output voltages making them useful in wide range of applications. When used as a

zener diode/resistor combination replacement, the LM78XX usually results in an effective output

impedance improvement of two orders of magnitude, lower quiescent current. The LM78XX is available

in the TO-252, TO-220 & TO-263packages,

Features:

• Output Current of 1.5A

• Output Voltage Tolerance of 5%

• Internal thermal overload protection

• Internal Short-Circuit Limited

• Output Voltage 5.0V, 6V, 8V, 9V, 10V, 12V, 15V, 18V, 24V.

LCD Unit

A liquid crystal display (LCD) is a thin, flat display device made up of any number of color or

monochrome pixels arrayed in front of a light source or reflector. It is prized by engineers

because it uses very small amounts of electric power, and is therefore suitable for use in

battery-powered electronic devices.

Each pixel consists of a column of liquid crystal molecules suspended between two

transparent electrodes, and two polarizing filters, the axes of polarity of which are

perpendicular to each other. Without the liquid crystals between them, light passing through

one would be blocked by the other. The liquid crystal twists the polarization of light entering

one filter to allow it to pass through the other.

The molecules of the liquid crystal have electric charges on them. By applying small electrical

charges to transparent electrodes over each pixel or sub pixel, the molecules are twisted by

electrostatic forces. This changes the twist of the light passing through the molecules, and

allows varying degrees of light to pass (or not to pass) through the polarizing filters. Before

applying an electrical charge, the liquid crystal molecules are in a relaxed state. Charges on the

molecules cause these molecules to align themselves in a helical structure, or twist (the

"crystal"). In some LCDs, the electrode may have a chemical surface that seeds the crystal, so it

crystallizes at the needed angle. Light passing through one filter is rotated as it passes through

the liquid crystal, allowing it to pass through the second polarized filter. A small amount of light

is absorbed by the polarizing filters, but otherwise the entire assembly is transparent.

When an electrical charge is applied to the electrodes, the molecules of the liquid crystal

align themselves parallel to the electric field, thus limiting the rotation of entering light. If the

liquid crystals are completely untwisted, light passing through them will be polarized

perpendicular to the second filter, and thus be completely blocked. The pixel will appear unlit.

By controlling the twist of the liquid crystals in each pixel, light can be allowed to pass though in

varying amounts, correspondingly illuminating the pixel.

Figure 4.10 LCD Display

4.5.1 Pin description of LCD

PIN SYMBOL

I/O

DESCRIPTIONS

1 VSS

--------

GROUND

2 VCC

--------

+5V POWER SUPPLY

3 VEE

---------

POWER SUPPLY TO CONTROL CONTRAST

4 RS I RS=O TO SELECT COMMAND REGISTER

RS=1 TO SELECT DATA REGISTER

5 R/W I R/W=0 FOR WRITE,R/W=1 FOR READ

6 E I/O ENABLE

8TO 14 DB0 TO DB14 I/O 8 BIT DATA BUSES

Table 4.3 Pin description of LCD

4.5.2 LCD COMMAND CODES

1. 80 Force cursor to beginning to 1st line

2. C0 Force cursor to beginning to 2nd line

3. 38 2 lines and 5x7 matrix

4. 1C Shift the entire display to the right

5. 18 Shift the entire display to the left

6. 14 Shift cursor position to right

7. 10 Shift cursor position to left

8. F Display on, cursor blinking

9. E Display on, cursor blinking

10. C Display on, cursor off

11. A Display off, cursor on

12. 8 Display off, cursor off

13. 7 Shift display left

14. 5 Shift display right

15. 6 Increment cursor (shift cursor to right)

16. 4 Decrement cursor (shift cursor to left)

17. 2 Return home

18. 1 Clear display screen

IR TRANSMITTER, IR RECEIVER

This is an IR transmitting circuit which can be used in many projects (I designed this to try to make

my 3D glasses wireless). This IR transmitter sends 40 kHz (frequency can be adjusted using R2) carrier under

computer control (computer can turn the IR transmission on and off). IR carriers at around 40 kHz carrier

frequencies are widely used in TV remote controlling and ICs for receiving these signals are quite easily

available. The 555 timer integrated circuit (IC) has become a mainstay in electronics design. A 555 timer will

produce a pulse when a trigger signal is applied to it. The pulse length is determined by charging then

discharging a capacitor connected to a 555 timer. A 555 timer can be used to debounce switches, modulate

signals, create accurate clock signals, create pulse width modulated (PWM) signals, etc. A 555 timer can be

obtained from various manufacturers including Fairchild Semiconductor and National Semiconductor.

4.3 IR RECEIVERSInfrared receivers pick up infrared signals within line-of-sight, and within 30 feet or so, and turn the

signal into electrical impulses. These electrical impulses can be carried around the home on wires, and then

turned back into infrared signals by emitters. Due to their complexity and sensitivity, infrared receivers tend

to be the most expensive part of an infrared distribution system.

FIGURE 4.6: IR RECEIVER

140917606 data2

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