12.8Gbps HX Card - SWTest.org

27 May 2008

Page 1

Keynote Presentation

June 8-11, 2008San Diego, CA USA

Debbora AhlgrenVice President and Chief Marketing Officer

27 May 2008

Page 2

Where will that take us?

Consumers in the Drivers’ Seats

27 May 2008

Page 3

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

1980 1990 2000 2010 2020

The Global Electronics Industry

Communications26%

Consumer15%

Computer23%

Automotive4%

Military19%

Industrial/Medical

13%

$247B

1982

$TSource: Prismark

China, 34%

Asia, 17%

America, Europe, Japan, 49%

2/3 of the Industryis based on Networked

CommunicationsCommunications

25.2%

Consumer11.4%

Computer35.3%

Automotive6.3%

Military8.7%

Industrial/Medical 13.1%

$1,190B

2006 Production

21.9%

15.4%

62.7%

27 May 2008

Page 4

The Pervasiveness of Semiconductors

Semiconductors underpin all business sectors

End products’ ever-growing dependence on semiconductors

Semi-conductor

content (% of end

product value)

World GDP

Electronic Equipment

Semiconductors

Investment: Materials & Equipment

$ 36,000 bn

$ 1,240 bn

$ 246 bn

$ 45 bn

Source: Medea+

27 May 2008

Page 5

The Prevailing Laws – Moore

More than Moore: Application-Driven Process Diversification

Analog/RF Passives HV Power BiochipsSensorsActuators

Moo

re’s

Law

: Sc

alin

g

CPU

Mem

ory

Logi

c

90nm

65nm

45nm

32nm

22nm

130nm

.

.

.

Digital DataProcessing & Storage

Interfacing &Interacting withEnvironment

Source: ITRS, IntelCombination

Higher Value Systems

27 May 2008

Page 6

65nm2005

45nm2007

90nm2003

22nm2011

Roadmap

32nm2009

25 nm

15nm

• New technology generation every 2 years• R&D technologies drive this pace well into

the next decade

16nm2013 11nm

2015 8nm2017

Research

Source: Intel

Silicon Future

2005 - 2012 2013 - 2017

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Page 7

Increasing Throughput through Parallelism

12 Cores 48 Cores 144 Cores

Parallel Speed-Up=1/(Serial% + (1-

Serial%)/N)

N= number of cores

The Prevailing Laws – Amdahl

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Page 8

Nano-scale Semiconductor Devices

Source: Samsung

27 May 2008

Page 9

Cache

Big Core

CacheCache

Big CoreBig Core

1

2

3

4

Power

11

22

33

44

Power

2

1

Performance

22

11

PerformanceCache

SmallCore 1 1

Power = ¼Performance = 1/2

Cache

SmallCore

CacheCache

SmallCoreSmallCore 11 11

Power = ¼Performance = 1/2

Homogeneous Array of CoresFixed Function UnitsGlobal Coherency Hardware

1

2

3

4

Power

11

22

33

44

Power

Cache

C1 C2

C3 C4

Cache

C1 C2

C3 C4

Performance

1

2

3

4

11

22

33

44

Multi-Core is more power-efficientPower ~ Area

Single-Thread Performance ~ Area *.5

Source: Intel, www.intel.com

MPU to Multi-Core SoC Trend

Scalable FabricReconfigurable Cache

High Bandwidth Memory

Power Delivery & Management

Core

Core

Core

Core

Core

Core

Core

Core Core Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core Core CoreCore CoreCore Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Fixed Function Units

Scalable FabricReconfigurable Cache

High Bandwidth Memory

Power Delivery & Management

Scalable FabricReconfigurable Cache

High Bandwidth Memory

Power Delivery & Management

Core

Core

Core

Core

Core

Core

Core

Core Core Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core Core CoreCore Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

Core

CoreCore

Core

CoreCore

Core

Core

CoreCore

CoreCore

Core

Core

Core

Fixed Function Units

27 May 2008

Page 10

More than Moore

More than Moore: Application-Driven Process Diversification

Analog/RF Passives HV Power BiochipsSensorsActuators

Moo

re’s

Law

: Sc

alin

g

CPU

Mem

ory

Logi

c

90nm

65nm

45nm

32nm

22nm

130nm

.

.

.

Digital DataProcessing & Storage

Interfacing &Interacting withEnvironment

Source: ITRS, IntelCombination

Higher Value Systems

27 May 2008

Page 11

Qualcomm vs. Intel

Source: Core Logic 2008

27 May 2008

Page 12

3 Imperatives For Mobile Internet

Source: XOHM

1Innovation in Distribution:• Chipsets: Single chip WiFi + WiMAX• Devices: Embed chipsets in mass

market laptops and consumer electronic devices

• Distribution: Leverage consumer electronics sales distribution channels

2Innovation Multimedia Solutions:Visual Centric, Interactive, Personal Broadband

Affordable Service:Pay as You Go, Pre-paid, or Monthly Subscription3

27 May 2008

Page 13

The WiMAX Ecosystem

27 May 2008

Page 14

System Performance Bottleneck

1x

4x

CPUDRAMHDD

Source: Samsung 2007

1980 1985 1990 1995 2000 2005 2010

Sp

eed

/Th

rou

gh

pu

t

1GHz

10MHz

100MHz

10GHz

1982: 286, 6MHz

2005: P5, 3.8GHz

2003: P4 3GHz

1999: PIII, 500MHz

1989: 486, 25MHz

1993: P, 66MHz

1997: PII, 300MHz

1985: 386, 16MHz

1985: FP, 13MHz

1993: EDO, 33MHz

1997: SDR,133MHz

1994: SDR, 66MHz

2001: DDR286

2004: DDR-533

2007: DDR1066

2010: Future, 1600

1996: ATA21998: ATA4

2002: ATA62003: SATA 1.5G

2005: SATA 3G

2008: SATA 6G

Performance gap between DRAM and Storage is 4X greater than between DRAM and CPU

2000: P4 1.5GHz

27 May 2008

Page 15

System-in-a-Package vs System-on-a-Chip

• Lower cost• Smaller size• Lighter weight• Time-to-market

• Higher reliability• Lower noise• Multipurpose• Lower power• Better heat dissipation

Mobilization

Higher Performance

System-in-Package

• Lower NRE

• Building block Si

• Multiple sourcing

• Simple IP integration

• Faster time-to- market

• Yield management system

System-on-a-Chip

• Highest performance

• Lower cost in high volume

• Smallest size

• Higher NRE

• Process integration limitation

• Longer incubation time

Market Forces Requirements Integration Solutions

Source: STATS ChipPAC

27 May 2008

Page 16

Increasing Memory Bandwidth (BW) to Keep Pace

Package

DRAMDRAMCPUCPU

Heat-Sink

Power and IO Signals Go Through DRAM to CPU

Thin DRAM Die

Through DRAM Vias

3D Memory StackingBW (GB/sec) Under 2W

0.1

1

10

100

1980 1990 2000 2010 2020

Memory BWConstrainedby Power

3D MemoryHigher BW withinPower Envelope

Source: Intel

27 May 2008

Page 17

3D-IC Market and Roadmap

Source: YOLE Développement 2007

27 May 2008

Page 18

Motivation!!

0%

100%

Single Layer (Die) Yield

Sta

ckYi e

l d

95%

1 layer2 layers4 layers8 layers16 layers

95%

90%

81%

66%

44%

81%81%81%81%81%

Source: Lewis and Lee 2007

27 May 2008

Page 19

The Evolution of SoC Platform

• System-level design for faster time to market and efficiency• Development of standard platform solution with flexible architecture• Ideal core development

Source: Core Logic 2008

27 May 2008

Page 20

DFT Provides Access to the Combinational Logic Using the State Logic

Clock

Scan In

Scan Out

State Logic I/O

Combinational Logic

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Page 21

Post-Fault Simulation – Works OK for Combinational logic

Clock

State Logic

Scan In

Scan Out

I/OCombinational

Logic

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Page 22

But What Do You Do When the Fault is in the State Logic?

Clock

Scan In

Scan Out

State Logic I/O

Combinational Logic

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Page 23

Evolution of the Tester

SL CL I/O

Pass/Fail

Pass/Fail

Post Analysis

Offline is NOTAvailable!

Functional

Structural

HVM/Failure AnalysisISOLATE FAILURES

INTERACTIVE, LOCATE FAILURES

SL CL I/O

SL CL I/O

SL CL I/O

27 May 2008

Page 24

Encounter Test True-Time ATPG

Generate test patterns

High coverage testsfor sub 90nm defects

V93000 Environment

Capture failure data

Zero overhead data logsfor hundreds of failures

YieldVision

Triage failing die

Efficient data analysis to harvest mostrepresentative failures

Encounter Diagnostics

Volume analysis

Identify systematic sources of yield loss (logical & physical)

Encounter Diagnostics

Encounter Diagnostics

Physical correlation

Identify layout feature causing yield loss

PFA

Highest probability die with X-Y locationsconfirms diagnosis

Source: Cadence, Verigy

Precision analysis

Identify most representativedie causing yield loss (logical)

Integrated Solution for Accelerated Yield Ramp Linking Design to Silicon

27 May 2008

Page 25

DRAM Test Cost vs. Parallelism

4TD SquareNormalized $1.00 CoT/die

4TD Skip Row$0.84 CoT/die

2TD Skip Row$0.62 CoT/die

1TD – Full Wafer$0.42 CoT/die

27 May 2008

Page 26

DRAM Test Cell Cost Breakdown – 1990s – 2000s

1997Parallelism ~32 die/touchdown

Source: Verigy, Micron Marketing

2010EParallelism ~512 die/touchdown

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Page 27

Overall Challenge to the Industry

Our future has a critical need for innovation and collaboration – across the boundaries of design, test and fabrication – to support the “faster”, “more” and “cheaper” that are the requisites of the consumer economy.

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Page 28

THANK YOU!

27 May 2008

Page 29

Back Up Slides

27 May 2008

Page 30

Rapid Technology Change & Consumerization

1st Generation

2nd Generation3rd Generation

Source: STATS ChipPAC

27 May 2008

Page 31

Rapid Technology Change & Consumerization

Ph1 Evolution

Ph2 EvolutionPh3 Evolution

Source: STATS ChipPAC