Recent Development of Recent Development of FinFET Technology for CMOS FinFET Technology for CMOS Logic and Memory Logic and Memory Chung Chung - - Hsun Lin Hsun Lin EECS Department EECS Department University of California at Berkeley University of California at Berkeley
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Recent Development of Recent Development of FinFET Technology for CMOS FinFET Technology for CMOS
Logic and MemoryLogic and Memory
ChungChung--Hsun LinHsun Lin
EECS DepartmentEECS DepartmentUniversity of California at BerkeleyUniversity of California at Berkeley
NTUEE Seminar 2006/04/29NTUEE Seminar 2006/04/29 Chung-Hsun Lin - 2
OutlineOutlineWhy FinFETWhy FinFET
FinFET processFinFET processUnique features of FinFETUnique features of FinFET
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Short Channel BehaviorShort Channel Behavior
MG device with sharp corner shows better short channel behavior than the rounded corner
0 200 400 600 800 10000
20
40
60
80
100
D
IBL
(mV
/V)
Gate Length (nm)
R=0nm R=15nm
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DoubleDouble--humps induced by cap transistorhumps induced by cap transistor
30x30nm structure, Tox=3nm, Lg=1mm, Nsub=5e18cm-3
Cap transistor induced lower Vt is very significant.It may attribute to thicker Tox, and more partial depleted.
0.3 0.6 0.9 1.2 1.5 1.80.0
1.0x10-6
2.0x10-6
3.0x10-6
4.0x10-6
dGm
/dV
g
Gate Voltage (V)
30x30nmLg=1μm, Tox=3nmNsub=5e18cm-3
0.0 0.5 1.0 1.5 2.01E-17
1E-15
1E-13
1E-11
1E-9
1E-7
1E-5
Dra
in C
urre
nt (A
)
Gate Voltage (V)
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Volume Inversion [1]Volume Inversion [1]
eDensity
6.1E+13
5.3E+13
4.5E+13
3.6E+13
2.8E+13
2.0E+13
Gate Gate Gate Gate
Oxide Oxide
eDensity
6.1E+13
5.3E+13
4.5E+13
3.6E+13
2.8E+13
2.0E+13
N sub =10 15 cm -3 N sub =10 18 cm -3
T si T si
The electron density distribution from the 3-D ISE device simulator. Volume inversion is significant in intrinsic channel SDG (left).
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Volume Inversion [2]Volume Inversion [2]
0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6 Nsub = 1015 cm-3
ϕs0, 10nm ϕs, 10nm ϕs0, 20nm ϕs, 20nm
Elec
tric
Pot
entia
l (V)
Gate Voltage (V)
For intrinsic channel doping, volume inversion is valid and the potential through the Si film is flat in the subthreshold region. The inversion charge (current) in the subthreshold region is proportional to Tsi.
0.0 0.2 0.4 0.6 0.8 1.01E-15
1E-13
1E-11
1E-9
1E-7
1E-5
Tsi
Nsub = 1015 cm-3
Tsi = 10 nm Tsi = 20 nm
Inve
rsio
n ch
arge
she
et d
ensi
ty (C
/cm
2 )
Gate Voltage (V)
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Issue of Fin FormationIssue of Fin Formation
Neutral beam etching can accomplish damage (defect) free fabrication of high aspect ratio fin.Higher mobility is obtained in NB device due to atomically-flat surface
K. Endo et al., IEDM 2005
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Sidewall Spacer Transfer (SWT) ProcessSidewall Spacer Transfer (SWT) Process
Both gate and fin are formed by SWTSiN is selected as hard mask material for Si RIE on top of fin
Can be used as the CMP stopper during poly gate planarization (important for gate SWT)Suppress the agglomeration of Si fin during selective Si epiPrevent the leakage of the top cornerUsed as RIE stopper in the gate RIE process
A. Kaneko et al., IEDM 2005
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SWT ProcessSWT Process
The threshold voltage uniformities for SWT FinFETs of 15nm fin and 15nm gate length over the wafer is better than ArF and EB lithography
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DRAM application of Bulk FinFETDRAM application of Bulk FinFET
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DRAM application of Bulk FinFETDRAM application of Bulk FinFET
Negative word line bias is introduced due to lower VT
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NWL SchemeNWL Scheme
Lower VT (doping concentration) FinFET combined with NWL scheme can provide lower leakage and higher performanceNWL bias is critical to refresh fail bit
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SONOS Application of FinFETSONOS Application of FinFET
High Performance FinFET SONOS flash cells with gate length of 20nm is demonstrated.Program/erase window of 2V with high P/E speed (Tp=10ms, TE=1ms)
J. Hwang et al., TSMC 2005
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SONOS Application of FinFETSONOS Application of FinFET
Excellent endurance: up to 10K P/E cyclesGood retention: 1.5V after 10years retention time
J. Hwang et al., TSMC 2005
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FinFETs based 6FinFETs based 6--T SRAMsT SRAMs
Large fraction of the total chip area will be memory1
Leakage problem
Limited by impact of variations
WL
BL
VDD
M5M6
M4
M1
M2
M3
BL
VRVL
pulldown
access
load
FinFETs offer good control of short channel effects
1Source : Ranganathan, 2000
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Static Noise MarginStatic Noise Margin
• The minimum noise voltage at the storage node needed to flip the state
• Large SNM is desirable
Make pulldown device stronger relative to access transistor
Source: Bhavnagarwala, 2001
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SNM spread with variationsSNM spread with variationsThicker Si body better
Higher performance due to Rs limitations
Greater noise immunity (SNM)
Lesser spread in SNM
0
0.05
0.1
0.15
0.2
0.25
0.3
0.1 0.15 0.2 0.25SNM (V)
Prob
abili
ty
Tsi = 11nmTsi = 15nm
Taurus Device Simulation
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SNM spread with variationsSNM spread with variations
To improve SNMa) Wpulldown ↑ - 2 fins
b) Laccess ↑
c) μeff, pulldown>μeff, access
(100)pulldown device
(110) access device
0
0.1
0.2
0.3
0.1 0.15 0.2 0.25SNM (V)
Prob
abili
ty
(100)/1fin
(100 )/ 2 fins
(110) / 1finTSi = 15nm
Taurus Device Simulation
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FinFET based CMOS and memory cells are FinFET based CMOS and memory cells are very promising for subvery promising for sub--32 technology 32 technology node.node.
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Thank you very much Thank you very much for your attentionfor your attention