12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 1 A low-power delta-sigma modulator using dynamic-source-follower integrators Ryoto.

12/14/2010 Sophia University 　　　　 Solid –State Circuits & Devices Laboratory 1

A low-power delta-sigma modulatorA low-power delta-sigma modulatorusing dynamic-source-follower integratorsusing dynamic-source-follower integrators

Ryoto Yaguchi, Fumiyuki Adachi, Waho TakaoRyoto Yaguchi, Fumiyuki Adachi, Waho Takao

Department of Information and Communication SciencesDepartment of Information and Communication SciencesSophia UniversitySophia University

12/14/2010 Sophia University 　　　　　　 Solid –State Circuits & Devices Laboratory2

OutlineOutline

IntroductionIntroduction

Background & MotivationBackground & Motivation

Our ApproachOur Approach

Proposed Integrator (DSFI)Proposed Integrator (DSFI)

Output SamplingOutput Sampling

Circuit SimulationCircuit Simulation

ModulatorsModulators

11stst-Order -Order Modulator Modulator

22ndnd-Order -Order Modulator Modulator

Performance ComparisonPerformance Comparison

ConclusionConclusion


OutlineOutline


Background & Motivation Background & Motivation



OutputOutput SamplingSampling


Modulators

11stst-Order -Order Modulator

22ndnd-Order -Order Modulator

Performance Comparison




SAR ADCLow power

operationLimited

resolution

ADCHigh resolutionHigher power

ADC(Opamp)

SAR ADC(Opamp-less)

Future communication applications need low power and high resolution ADCs.

Res

olut

ion

1/Power


Z - 1

DA C

IN O U T

Approach Approach

Opamp-less IntegratorOpamp-less Integrator

Modulator

Low Power Low Power ModulatorModulator

Analog IN Digital Out

We proposed a We proposed a Dynamic Source Follower IntegratorDynamic Source Follower Integrator


OutlineOutline







Modulators






Dynamic Source-Follower Amplifier (MDAC)Dynamic Source-Follower Amplifier (MDAC)1 ． Sampling Phase

2 ． Amplification Phase

Redistributing charges

Sampling Vin and Vref

J. Hu, et al., JSSC ‘09


Proposed IntegratorProposed IntegratorDynamic Source-Follower Dynamic Source-Follower

AmplifierAmplifier （（ MDAC)MDAC)

Dynamic Source-FollowerDynamic Source-Follower 　　 IntegratorIntegrator

Previous work

Proposed

Input Sampling


Proposed IntegratorProposed IntegratorDynamic Source-Follower Dynamic Source-Follower

AmplifierAmplifier （（ MDAC)MDAC)

Dynamic Source-FollowerDynamic Source-Follower 　　 IntegratorIntegrator

Previous work

Proposed

Feedback path


Output SamplingOutput Sampling

Output Sampling Charge Redistributing

Two capacitors for charge redistributing and output sampling, indepandently.

C2a C2b

Feedback pathFeedback path

12/14/2010 Sophia University 　　　　　　 Solid –State Circuits & Devices Laboratory

N

k

kinn

kinp

Noutn

Noutp VVVV

0

11

11

Whole Circuit of DSFIWhole Circuit of DSFI


Simulation of DSFISimulation of DSFI

Bode PlotInput Frequency = 20kHzSampling Frequency = 0.5MHz

Successful integrator operation

Inpu

t [V

]In

put

[V]

Out

put

[V]

Out

put

[V]

Gai

n [d

B]

Gai

n [d

B]

Pha

se [

deg]

Pha

se [

deg]

Time [Time [s]s] Input Frequency[Hz]Input Frequency[Hz]

Input Frequency[Hz]Input Frequency[Hz]

-10-5051015202530

0.1k 1k 10k 100k

Input　Frequency[Hz]

Gain

-100

-80

-60

-40

-20

0

0.1k 1k 10k 100k

Phase

-15-10-5051015202530

0.1k 1k 10k 100k

-100

-80

-60

-40

-20

0

0.1k 1k 10k 100k

0.2

0

-0.21.0

-1.0

0

800 850 900 950 1000

0

10

20

30

-10

0.1k 1k 10k 100k

-45

-90

0.1k 1k 10k 100k

0


OutlineOutline







Modulators






1st-Order 1st-Order Modulator Modulator

DS F I

V inp V O U T p

DA C

V inn V O U T n

Vdacn

VdacpIn

pu

t [V

]In

pu

t [V

]O

utp

ut [

V]

Ou

tpu

t [V

]Time [Time [s]s]

0.3

-0.3

0

0

2

1

800 850 900 950 1000

Vinp

Vinn

Vdacn

Vdacp

Voutp

Voutn

Vinn

Vinp

Voutp

Voutn

VDD


1st-Order 1st-Order Modulator Spectrum Modulator Spectrum

1st-order noise shaping characteristics are obtained!!

PS

D[d

B]

PS

D[d

B]

Frequency [Hz]Frequency [Hz]

20dB/dec

1k 10k 100k 1M 10M-100

-80

-60

-40

-20

0

Input Frequency [kHz] 20Sampling rate [MS/ s] 5.285

Point 8192

FFT Condition

SNR [dB] 59.57ENOB [bit] 9.60Power [μW] 12.9

FOM [pJ / conv] 0.415

FFT Result


Comparator decisionDS F I

V inp V O U T p

DA C 1

V inn V O U T nDS F I

DA C 2

2nd-Order 2nd-Order Modulator Modulator

Charging　capacitors　before　comparator　decision

To 1st DFSI Voutp

To 1st DFSI Voutn

Redistribution

Charging

Charging

Vinp

Vinn

Tim

e

11stst DSFI DSFI

22ndnd DSFI DSFI


2nd-Order 2nd-Order Modulator Spectrum Modulator SpectrumP

SD

[dB

]P

SD

[dB

]

Frequency [Hz]Frequency [Hz]

2nd-order noise shaping characteristics are obtained!!

40dB

/dec

Input Frequency [kHz] 20Sampling rate [MS/ s] 5.285

Point 8192

FFT Condition

1k 10k 100k 1M 10M-100

-80

-60

-40

-20

0

SNR [dB] 73.75ENOB [bit] 11.96Power [μW] 27.38

FOM [pJ / conv] 0.172

FFT Result


Performance ComparisonPerformance Comparison　

Proposed 0.18-m, 2nd-order modulator has a good power efficiency comparable with those obtained by using 0.13-m

technologies.

2009 2009 2009 2009 2008



We proposed a dynamic source-follower integrator (DSFI), and applied it to opamp-less modulators.

Operation of proposed 1st and 2nd order modulators designed by using a 0.18-m CMOS technology successfully was confirmed by transistor-level circuit simulation.

The designed 20-kHz BW, 73.8dB SNR, 2nd-order modulator has a good power efficiency comparable with those obtained by using 0.13-m technologies.




Output Common-mode Voltage

Output Common-mode Voltage VCM[V] ENOB [bit]

Calculating / Matlab 0.9 14.36

Pass Transistor 0.826 11.96

Ideal Switch 0.881 12.37


CMRR at DSFI

)(2

1)( VVAVVAV CMdout

)/log(20 CMd AACMRR

・Output　equation　　of　typical　differential　amplifier :

・ CMRR：

Inp

ut

p [

V]

Inp

ut

p [

V]

Ou

tpu

t [V

]O

utp

ut

[V]

Inp

ut

n [

V]

Inp

ut

n [

V]

Inp

ut

p [

V]

Inp

ut

p [

V]

Ou

tpu

t [V

]O

utp

ut

[V]

Inp

ut

n [

V]

Inp

ut

n [

V]

Time [s]Time [s]Time [s]Time [s]

VV+++V+V--=0=0 VV++-V-V--=0=0

CMRR is very good!!


Clock Generators

Non-overlap clock generator TFF-clock generator

Ou

tpu

tO

utp

ut

TimeTime TimeTime

Ou

tpu

tO

utp

ut

Inp

ut

Inp

ut

Inp

ut

Inp

ut

Generate φ1,φ2 Generate φ2a,φ2b

Q:Q: For example, what about any digital circuits you needed to control switches?


modulator power consumptionmodulator power consumption

22ndnd DSFI DSFI47.1%47.1%11stst DSFI DSFI

41.6%41.6%

Comparator 3.7%Comparator 3.7%

Clock Generators 7.1%Clock Generators 7.1%

Others 0.5%Others 0.5%Q:Q: In your power consumption estimation, what kinds of circuits are included?

*)Without the referential voltage generators


Comparison FairnessComparison Fairness

We have to examine the comparison on experimental measurement, hereafter!!

Q: Q: You compared your simulation results with the experimental results. Is this a fair comparison?

22ndnd-order DSM-order DSM

2nd-DSFI2nd-DSFI1st-DSFI1st-DSFI

Clock GeneratorClock Generator

ComparatorComparator

2.5mm2.5mm

12/14/2010Sophia University Solid –State Circuits & Devices Laboratory 1 A low-power delta-sigma modulator using dynamic-source-follower integrators Ryoto.

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