12/10/2004EE 42 fall 2004 lecture 421 Lecture #42: Transistors, digital This week we will be reviewing the material learned during the course Today: review.

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Lecture #42: Transistors, digital

• This week we will be reviewing the material learned during the course

• Today: review– CMOS transistors – Digital logic

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Review Session

• When:  Thursday, Dec. 16th; 3-6pm

• Where: Evans 0009

• Format: Open, bring questions

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Final Exam

Date/Time: • SATURDAY, DECEMBER 18, 2004   • 5-8PMLocation: 150 GSPP(Goldman School of Public Policy) Format:• Closed book• One page, (two sides) of notes

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n

P

oxide insulatorn

drain

- +

source

gate

MOS transistorBelow threshold

VGS < Vt

Below threshold, there are no electrons under the gate oxide, and the holes in the substrate are blocked from carrying current by reverse biased diode junctions

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n

P

oxide insulatorn

drain

- +

source

gate

NMOS in the linear (Triode) region

VGS > Vt

If the gate voltage is above threshold, but the source to drain voltage is small, the charge under the gate is uniform, and carries current much like a resistor

The electrons move under the influence of the

Electric field at a velocity: ν=μE where E=volts/distance

And they must travel a distance L to cross the gate

Since the total charge is Q=CVgs, we will have a current

Id=μCgateVds (Vgs-Vth)/L2= μ(εox/dox)Vds (Vgs-Vth)W/L

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n

P

oxide insulatorn

drain

- +

source

gate

NMOS with increasing Vds

VGS > Vt

As the voltage from the source to the drain is increased, the current increases, but not by as much because the charge is attracted out from under the oxide, beginning to pinch off the channel

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Saturation

• As the Source-Drain voltage is increased, there will be a significant change in the charge at different distances along the gate

• When the voltage across the device at the drain end goes below threshold, the current is pinched off.

• If there is no current out the drain end, however, the current due to the carriers which are available from the source cause the voltage to be closer to that of the source.

• These two effects cause a small region to form near the drain which limits the current. This is called saturation

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A little more MOS “Theory”

We have two regions: the resistive region at smaller VDS and the saturation region at higher VDS .

ID

VDS

VGS

In the resistive region we start out like a simple resistor between source and drain (whose value depends on gate voltage) and gradually the curve “bends over” as we approach saturation

In the saturation we have a small gradual increase of I with VDS

VGS

SG

VDS

iD+ +-

D

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Basic CMOS Inverter

Inverter

IN OUT

VDD p-ch

VDD

OUT

IN

n-ch

CMOS Inverter

GROUND

IN

OUT

VDD

N-WELL

NMOS Gate

PMOS Gate

Al “wires”

GROUND

IN

OUT

VDD

N-WELL

NMOS Gate

PMOS Gate

Al “wires”

Example layout of CMOS Inverter

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GROUND

IN

OUT

VDD

N-WELL

NMOS Gate

PMOS Gate

Al “wires”

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n-typemetal metaloxide insulator

metal

p-type

metal

gate

source

drain

n-type

- +

VGS

- +

VDS

IDIG

G

DS

ID

IG

- VDS +

+

VGS_

NMOS Transistor

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G

DS

ID

IG

- VDS +

+

VGS_

NMOS I-V Characteristic

• Since the transistor is a 3-terminal device, there is no single I-V characteristic.

• Note that because of the insulator, IG = 0 A.

• We typically define the MOS I-V characteristic as

ID vs. VDS for a fixed VGS.

• The I-V characteristic changes as VGS changes.

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triode mode

cutoff mode (when VGS < VTH(N))

saturation mode

VDS

ID

VGS = 3 V

VGS = 2 V

VGS = 1 V

VDS = VGS - VTH(n)

NMOS I-V Curves

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Saturation in a MOS transistor• At low Source to drain voltages, a MOS transistor looks

like a resistor which is “turned on” by the gate voltage• If a more voltage is applied to the drain to pull more

current through, the amount of current which flows stops increasing→ an effect called pinch-off.

• Think of water being sucked through a flexible wall tube. Dropping the pressure at the end in order to try to get more water to come through just collapses the tube.

• The current flow then just depends on the flow at the input: VGS

• This is often the desired operating range for a MOS transistor (in a linear circuit), as it gives a current source at the drain as a function of the voltage from the gate to the source.

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NAND gate

A B A B A B

Making a NAND gate: (NMOS pulls “down”, PMOS “up”)

NMOS portion: both inputs need to be high for output to be low series

CMOS DIGITAL LOGIC

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

PMOS portion: either input can be low for output to be high parallel

C=

B

C

A

VDD

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These are circuits that accomplish a given logic function such as “OR”. We will shortly see how such circuits are constructed. Each of the basic logic gates has a unique symbol, and there are several additional logic gates that are regarded as important enough to have their own symbol. The set is: AND, OR, NOT, NAND, NOR, and EXCLUSIVE OR.

Logic Gates

A

BC=A·BAND C =

A

BNAND BA

C = NORA

BBA

NOTA A

ORA

BC=A+B

EXCLUSIVE OR

A

BBAC

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Transistor Inverter ExampleIt may be simpler to just think of PMOS and NMOS transistors instead

of a general 3 terminal pull-up or pull-down devices or networks.

VIN-D

Pull-Down Network VOUT

IOUT

Output

VDD

Pull-Up Network

VIN-U

VIN-D

VIN-U

VOUT

IOUT

Output

VDD

p-type MOSTransistor(PMOS)

n-type MOSTransistor(NMOS)

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Complementary Networks

• If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS.

• The reverse is also true.• Determining the logic function from CMOS circuit is

not hard:– Look at the NMOS half. It will tell you when the output is

logic zero.– Parallel transistors: “like or”– Series transistors: “like and”

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Some Useful Theorems

1)

2)

3)

4)

5)

6)

7)

8)

9)

1 AA

0 AA

C)(BACABA

ABC CBA

AB BA

BABA

BABA } de Morgan’s Laws

ABC CBA

AB BA

Each of these can be proved by writing out truth tables

Communicative

Associative

Distributive

Defined from

truth tables

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Evaluation of Logical Expressions with “Truth Tables”

The Truth Table completely describes a logic expression

In fact, we will use the Truth Table as the fundamental meaning of a logic expression.

Two logic expressions are equal if their truth tables are the same

A truth table can be turned into a sum-of-products by writing each row which results in a “1” output as an “and” (the product), and then ORing them together (the sum)

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Going from a Boolean expression to gates

Simply expand the Boolean expression into a SUM-OF-PRODUCTS expression:

Y = ABC+DEF

Then rewrite it by “inverting” with De Morgan:

NAND GATE SYNTHESIS. Using De Morgan’s theorem we can turn any Boolean expression into NAND gates.

The NAND realization, while based on DeMorgan’s theorem, is in fact much simpler: just look at the sum of products expression and use one NAND for each term and one to combine the terms.

(DEF) (ABC)Y

AB

YC

DE

F

Clearly this expression is realized with three NAND gates: one three-input NAND for , one for

, and one two-input gate to combine them:(ABC)

(DEF)

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Synthesis

Designing the combinatorial logic circuit, con’t

Two Examples of SUM-OF-PRODUCTS expressions:

Method 3: NAND GATE SYNTHESIS (CONTINUED).

BABA X (X-OR function)

A

X

B

(No connection)

CBAABCY

A

Y

B C

We could make the drawings simpler by just using a circle for the NOT function rather than showing a one-input NAND gate

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NMOS switches in series from output to ground; PMOS switches in parallel from output to the supply (Here we left out the A-A and B-B connection for clarity)

CMOS NAND GATE

vA

vB

vOUT

VDD

vA vB

Behaves like 2 Rn’s in series

when both A and B are high

NAND: If either output is low then one of the bottom (pull down) series switches is open and one of the upper (pull up) switches are closed.

Thus the output is pulled high.

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NAND Gate Pull-Up Model*

vOUT

VDD

vA vB

vA

vB

pR pR

CGpGn CCC

= RC = RpC )CC(R GpGnp

One or both switches closed (worse case: one switch)

Output is loaded by the gate capacitance of the next stage: C= CGn+CGp

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B

F

A

VDD

C

F

A

VDD

B

NAND Gates with more inputs

2-input NAND

Each input loads with CGN +CGP

Output drives with 2RDN or RDP

3-input NAND

Each input loads with CGN +CGP

Output drives with 3RDN or RDP

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NOR function (two inputs)

A B A +B C=A +B

Output is low if either input is high

NMOS switches (between ground and the output) in parallel

CMOS NOR GATE

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

BAOutput is high only if both inputs are low

PMOS switches (between the supply and the output) in series

VDD

A

BC

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“Complementary” configuration to the NAND gate

CMOS NOR GATE

vOUT

VDD

vA

vB

vOUT

VDD

vA

vB

NOR NAND

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Definition of Fanout

Fanout = number of gates that are connected to the driver

Fanout leads to increased capacitive load (and higher delay)

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Clocked logic

• If we put two latches into every feedback path, and make sure both latches are never open at the same time, we can insure predicable results.

A

B

C Outputs

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Edge trigger

• If we use an edge trigger, then a single phase clock can be used. An edge triggered flip flop will only change at a rising or falling edge of the clock, so that the new state will not feedback to its own value

A

B

C Outputs

trigger edge

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Sequential logic

• The timing rules for sequential logic can be summarized:

• Only one transition of the latches are allowed per clock cycle, the change from one clock is not allowed to circulate back through the logic to effect itself.

• The clock speed will be limited by the slowest path

• The fastest path must not be allowed to change the state before changes have been latched out