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Add, Subtract, Compare, ALU
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Menu• Other MSI Circuit:• Adders
>Binary, Half & Full• Canonical forms• Binary Subtraction• Full-Subtractor• Magnitude Comparators
>See Lam: Fig 4.8• ALU
Look into my ...
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• Suppose we want to add two 2-bit numbers
Sum Carry
10 1 1
+0 1 01 0 1
Carry
Sum = /X Y + X /Y = XYCarry = X Y
Binary Adder
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• If we add two 4-bit numbers, what must we do bit by bit? __c3 c2 c1 c0 = 0 ci = carry bitx3 x2 x1 x0 xi = 1st number y3 y2 y1 y0 yi = 2nd number
This circuit is called
a Half-Adder
Notation: A 4-bit number is represented by b3b2b1b0.
Thus, we get bits b0~bN-1 where N = # of bits.
c4 s3 s2 s1 s0 si = sum
• For the circuit with no carry in, we implement as follows:
si = xi yi
ci+1 = xi yi
xi
yisi
ci+1
Notation for Binary Addition
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Let us include a carry input (cin) in the design:
Sum = /x*/y* cin + /x* y*/cin +x*/y*/cin + x* y* cin
• When cin = 0, Sumcin=0 = xy• When cin = 1, Sumcin=1 = /(xy)• Sum = Sumcin=1•cin + Sumcin=0•/cin
• Sum = /(xy)•cin + (xy)•/cin
• Let W= xy• Then Sum = /W•cin + W•/cin = Wcin
• Sum = xycin
Adder with Carry Input
Sum
cout
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Let’s do Cout:
cout
This circuit is called
a Full-Adder
XOR of all inputs
Sum=xycin
Sum of all possible pairs
cout = x y + x cin + y cin
xy
cinxyxcin
ycin
cout
Sum
Sum = si
cin = ci & cout = ci+1
Canonical.cct
Q: Is the order important?
Q: Why?
Carry Out of Full Adder
si
ci+1FA
xi
yi
ci
s
co
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• Actually, we could replace FA0 with a half-adder• 74’283 is a 4-bit look-ahead carry adder
FA3 FA2 FA1
FA0 (C0=0)
C4 S3
Y3 X3 C3
C3
C2 C1
C1
C0=0Y2 Y0Y1 X0X1X2
S0S2
• Thus, to add two 4-bit numbers we need 4 Full-Adders as follows:
C2 S1
ORHA (no C0)
Ripple-Carry Adders
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What if you don’t have XOR gates?Two level logic
If you need 3-input adder (and 3-input XOR), then:
Four level logic......Why ?
XY = /X Y + X /Y
XY
/XYX/Y
XYCi
XYCi
Levels of Logic
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• But from K-map (or truth table) we can implement as sum of 4 minterms.
• What if you only have NAND gates?
Sum = /x*/y* cin + /x* y*/cin +x*/y*/cin + x* y* cin
= x y cinAND-OR
NAND-NAND
Canonical.cct
Sum Circuit
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• MSOP = Minimum Sum of Product = An OR of AND terms
“bad” (P-logic) form“good” (mixed-logic) form
Canonical.cct
Canonical Forms: AND-OR = NAND-NAND
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• Example: Let cout = x y + x cin + y cin
• Similarly, MPOS: OR-AND = NOR-NOR
coutx
cin
xy
xcin cout
xcin
xy
ycin
“good” (mixed-logic) form
coutx
cin
xy
ycin
“bad” (P-logic) form
“bad” (P-logic) form“good” (mixed-
logic) form
Canonical.cct
Addition Example
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• If we subtract two 4-bit numbers, what must we do bit by bit?
b3 b2 b1 b0 = 0 bi = borrow inm3 m2 m1 m0 mi = minuends3 s2 s1 s0 si = subtrahend
b4 d3 d2 d1 d0 di = difference
• Consider the following unsigned 4-bit numbers:Bi 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0Mi 1 1 1 1 1 0 0 0 1 0 1 0Si -1 0 1 0 -0 1 0 1 -1 1 0 1Di 0 1 0 1 0 0 1 1 1 1 0 1
-24+ 23+22+20=-3
di
bi+1FS
mi
si
bi
Binary Subtraction
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Subtraction Equations
di = mi si bi
bi+1 = /mi si + /mi bi + si bi
di bi+1
For a full adder we had previously:
si = xi yi ci ci+1 = xi yi + xi ci + yi ci
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Full Subtractor using Full Adder
Suppose we let xi=/mi in the Full Adder equation
then
then
Same!
si = xi yi ci
ci+1 = xi yi + xi ci + yi ci
si = /mi yi ci
ci+1 = /mi yi + /mi ci + yi ci
/si = mi yi ci
thendi = /si = mi si bi
bi+1 = /mi si + /mi bi + si bi
bi+1
FAsi
bi
mi disi
ci+1
di
bi+1
FSmi
si
bi
si
ci+1
yi si
ci bi
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FS using FA and K-maps
sum
/diff
/diff
carry
borrow
K-maps for a FS for /di and bi+1
• Can also derive the same result using K-maps:>Let ai=/mi , bi=si & ci=bi
di
bi+1
FSmi
si
bi
si
ci+1
bi+1
FAmi
si
bi
disi
ci+1
xi
yi
ci
Alternative: Change mi and di to active-low
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Magnitude Comparators
Lam: Fig. 4.7
2A
B 2
A>BA=BA<B
• We want a device to compare two binary numbers A & B and tell us:
> (1) if A > B> (2) if A < B> (3) if A=B
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Magnitude Comparator K-Map
Lam: Fig. 4.7
2A
B 2
A>BA=BA<B
• We want a device to compare two binary numbers A & B and tell us:
> (1) if A > B (2) if A < B (3) if A=B
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2-bit Magnitude Comparator Realization
Lam: Fig. 4.7
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• Suppose A & B are 4 bit numbers. What is the corresponding size of the K-Map ? ___________
A = a3a2a1a0 B = b3b2b1b0
Hence, 8 inputs! 8-variable K-Map is a mess!
4-bit Magnitude Comparators
(A=B) = /(A>B) • /(A<B)(A>B) = /(A=B) • /(A<B)(A<B) = /(A>B) • /(A=B)
It takes 2 independent outputs and we can get the third from the 2.
Note: A = B cannot be simplified. A>B or A<B seem (and are) rotations/reflections of the same map.
4A
B 4
A>BA=BA<B
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4-bit Mag Comparator (74’85)
• Cascading comparators
4 A
B4
(A>B)OUT
(A=B)OUT
(A<B)OUT
(A>B)IN
(A=B)IN
(A<B)IN
See Lam: Fig 4.8
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4-bit Mag Comparator (74’85)
4 A
B4
(A>B)OUT
(A=B)OUT
(A<B)OUT
(A>B)IN
(A=B)IN
(A<B)IN
See Lam: Fig 4.8
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Arithmetic-Logic Units (ALU’s)
[Example] Let a computer instruction to complement the A register be COMA.The instruction COMA must do the following 3 things:(a) Connect the output of the A register to the A input of the ALU.(b) Present the ALU with control signals:
M = H, S0 = L, S1 = L, S2 = L, and S3 = L.(c) Wait an appropriate delay and connect the output of the ALU (F3-F0)
to the input of the A register to reload the A register.
• ALU’s are at the heart of CPU’s - They are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See figures on next 2 pages
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ALU (74’181)Active-High
ViewLam Fig 6.1
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ALU (74’181)Active-Low
ViewLam Fig 6.1
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Arithmetic-Logic Units (ALU’s)
[Example] Let a computer instruction to complement the A register be COMA.The instruction COMA must do the following 3 things:(a) Connect the output of the A register to the A input of the ALU.(b) Present the ALU with control signals:
M = H, S0 = L, S1 = L, S2 = L, and S3 = L.(c) Wait an appropriate delay and connect the output of the ALU (F3-F0)
to the input of the A register to reload the A register.
• ALU’s are at the heart of CPU’s - They are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See figures on previous 2 pages
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ALU Lab• During development, you can use a functional
compile or simulation or otherwise, you can let Quartus choose the device
>This will allow you to add extra outputs to aid in debugging
– If you let Quartus choose the device, compiling will take a LONG time. So do NOT do it!But you could pick a bigger device during development
• Make a table of instructions for each of the prelab requirements
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The End!