11-1 4446 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology I/O System Design.

11-1

4446 Design of Microprocessor-Based Systems

Dr. Esam Al_QarallehCE Department

Princess Sumaya University for Technology

I/O System Design

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65,536 possible I/O ports

Data transfer between ports and the processor is over data bus

8088 uses address bus A[15:0] to locate an I/O port

AL (or AX) is the processor register that takes input data (or provide output data)

I/O I/O I/O

Data bus

Address bus A[15:0]

AL

AX

8088

Introduction (cont’d)

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Introduction

• I/O devices serve two main purposes– To communicate with outside world– To store data

• I/O controller acts as an interface between the systems bus and I/O device– Relieves the processor of low-level details– Takes care of electrical interface

• I/O controllers have three types of registers– Data– Command– Status

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Introduction (cont’d)

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Introduction (cont’d)• To communicate with an I/O device, we need

– Access to various registers (data, status,…)• This access depends on I/O mapping

– Two basic ways

» Memory-mapped I/O

» Isolated I/O

– A protocol to communicate (to send data, …)• Three types

– Programmed I/O

– Direct memory access (DMA)

– Interrupt-driven I/O

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Accessing I/O Devices• I/O address mapping

– Memory-mapped I/O• Reading and writing are similar to memory read/write • Uses same memory read and write signals• Most processors use this I/O mapping

– Isolated I/O• Separate I/O address space• Separate I/O read and write signals are needed• Pentium supports isolated I/O

– 64 KB address space» Can be any combination of 8-, 16- and 32-bit I/O ports

– Also supports memory-mapped I/O

Memoryaddressingspace I/O

addressingspace

I/O

Memory addressingspace

00000

FFFFF

0000

FFFF

00000

FFFFF

Direct I/O Memory-mapped I/O

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Accessing I/O Devices (cont’d)• Accessing I/O ports in 80x86

– Register I/O instructionsin accumulator, port8 ; direct format

– Useful to access first 256 ports

in accumulator,DX ; indirect format– DX gives the port address

– Block I/O instructions• ins and outs

– Both take no operands---as in string instructions

• ins: port address in DX, memory address in ES:(E)DI• outs: port address in DX, memory address in ES:(E)SI

• We can use rep prefix for block transfer of data

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8088 Port Addressing Space

Addressing Space

FFFF

0000

00F8

00FF

Accessed directly byinstructions

Accessed throughDX

Accessing directly by instructions

IN AL, 80HIN AX, 6HOUT 3CH, ALOUT 0A0H, AX

Accessing through DX

IN AL, DXIN AX, DXOUT DX, ALOUT DX, AX

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Input Port Implementation

8088

Data Bus

Address busDecoder

InputGating device

Other control signals

— The outputs of the gating device are high impedance when the processor is not accessing the input port

— When the processor is accessing the input port, the gating device transfers input data to CPU data bus

— The decoding circuit controls when the gating device has high impedance output and when it transfers input data to data bus

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Input Port Implementation

Circuit Implementation

— Assume that the address of the input port is 9CH

Data bus Input dataTri-statebuffer

CE

RD IO/M

A7A6A5A4A3A2A1A0

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Input Port Implementation

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Output Port Implementation

Circuit Implementation

— Assume that the address of the output port is 9CH

Data bus Output dataLatch

CLK

WR IO/M

A7A6A5A4A3A2A1A0

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Output Port Implementation

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A Reconfigurable Port Decoder1 Vcc

A3A2

A1

A0

B3B2

B1

B0

A=B

A=B

A3A2

A1

A0

B3B2

B1

B0

A=B

A=B

A7

A6A5

A4

A3

A2A1

A0

R

RD or WR

IO/M

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An Example I/O Device

• Keyboard– Keyboard controller scans and reports

– Key depressions and releases

• Supplies key identity as a scan code– Scan code is like a sequence number of the key

» Key’s scan code depends on its position on the keyboard

» No relation to the ASCII value of the key

– Interfaced through an 8-bit parallel I/O port• Originally supported by 8255 programmable peripheral

interface chip (PPI)

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An Example I/O Device (cont’d)

• 8255 PPI has three 8-bit registers• Port A (PA)

• Port B (PB)

• Port C (PC)

– These ports are mapped as follows8255 register Port address

PA (input port) 60H

PB (output port) 61H

PC (input port) 62H

Command register 63H

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An Example I/O Device (cont’d)Mapping of 8255 I/O ports

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An Example I/O Device (cont’d)

• Mapping I/O ports is similar to mapping memory– Partial mapping

– Full mapping

• Keyboard scan code and status can be read from port 60H– 7-bit scan code is available from

• PA0 – PA6

– Key status is available from PA7• PA7 = 0 – key depressed

• PA0 = 1 – key released

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I/O Data Transfer• Data transfer involves two phases

– A data transfer phase• It can be done either by

– Programmed I/O– DMA

– An end-notification phase• Programmed I/O• Interrupt

• Three basic techniques– Programmed I/O– DMA– Interrupt-driven I/O

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I/O Data Transfer (cont’d)

• Programmed I/O– Done by busy-waiting

• This process is called polling

• Example– Reading a key from the keyboard involves

• Waiting for PA7 bit to go low – Indicates that a key is pressed

• Reading the key scan code• Translating it to the ASCII value• Waiting until the key is released

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8255 Programmable Peripheral Interface

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8255 Programmable Peripheral Interface

Data bus

8088

D[7:0]

A0A1

RDWR

RESET

CS

Control port

PA[7:0]

PB[7:0]

PC[7:0]

A7A6A5A4A3A2

IO/MA1 A0 Port

0 00 11 01 1

PAPBPCControl

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8255 Programmable Peripheral Interface

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Programming 8255

8255 has three operation modes: mode 0, mode 1, and mode 2

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Programming 8255

Mode 0:

— Ports A, B, and C can be individually programmed as input or output ports— Port C is divided into two 4-bit ports which are independent from each other

Mode 1:

— Ports A and B are programmed as input or output ports— Port C is used for handshaking

PA[7:0]

STBA

IBFA

INTRAPC3PC5PC4

PB[7:0]

STBB

IBFB

INTRBPC0PC1PC2

PC6, 7

8255

PA[7:0]

OBFA

ACKA

INTRAPC3PC6PC7

PB[7:0]

OBFB

ACKB

INTRBPC0PC1PC2

PC4, 5

8255

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Programming 8255 Mode 2:

— Port A is programmed to be bi-directional— Port C is for handshaking— Port B can be either input or output in mode 0 or mode 1

PA[7:0]

OBFA

ACKA

INTRA

PC4

PC6PC7

STBA

IBFA

PC0

PC3PC58255

PC0

PC0

PB[7:0]

In Out In OutIn Out

Mode 0

STBB OBFB IBFB ACKB

INTRB INTRB

Mode 1

1. Can you design a decoder for an 8255 chip such that its base address is 40H?2. Write the instructions that set 8255 into mode 0, port A as input, port B as output,

PC0-PC3 as input, PC4-PC7 as output ?

Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1 Strobed Output Timing diagrams.

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Example: Mode 1 Input

• BIT5 EQU 20H• PORTC EQU 22H• PORTA EQU 20H

• READ PROC NEAR• Read:

– IN AL, PORTC ; read portc– TEST AL, BIT5 ;test IBF– JZ Read ;if IBF=0– IN AL, PORTA ;Read Data

• READ ENDP

keyboard

PA0

PA7

STBPC4 DAV

8255

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Example: Mode 1 output

Printer

PB0

PB7

ACKPC2 ACK

8255

PC4 DS

Data Strobe : to tell the printer to latch the incoming data. Generated Externally

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BIT1 EQU 2PORTC EQU 62HPORTB EQU 61HCMD EQU 63HPRINT PROC NEAR

; check printer ready?IN AL, PORTC ;get OBFTEST AL, BIT1 ;test OBFJZ PRINT ;if OBF=0 buffer is

full

;send character to printerMOV AL, AH ;get dataOUT PORTB, AL ;print data; send data strobe to printerMOV AL, 8 ;clear DSOUT CMD, ALMOV AL, 9 ;clear DSOUT CMD, AL;rising the data at the positive

edge of DSRET

PRINT ENDP

Example: Mode 1 output

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Keyboard example 1/2

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Keyboard example 2/2

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Bouncing Problem

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Bouncing

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Software Solution

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De-bouncing Circuitry

Two asynchronous flip-flop solutions are given below

• The basic idea is that these flip-flops store the values even if the D/D nodes both float

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Another Solution

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External Interface• Two ways of interfacing I/O devices

– Serial • Cheaper

• Slower

– Parallel• Faster

• Data skew

• Limited to small distances

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External Interface (cont’d)Two basic modes of data transmission

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External Interface (cont’d)• Serial transmission

– Asynchronous• Each byte is encoded for transmission

– Start and stop bits

• No need for sender and receiver synchronization

– Synchronous• Sender and receiver must synchronize

– Done in hardware using phase locked loops (PLLs)

• Block of data can be sent

• More efficient– Less overhead than asynchronous transmission

• Expensive

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External Interface (cont’d)

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External Interface (cont’d)Asynchronous transmission

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External Interface (cont’d)

• EIA-232 serial interface– Low-speed serial transmission

– Adopted by Electronics Industry Association (EIA)

• Popularly known by its predecessor RS-232

– It uses a 9-pin connector DB-9• Uses 8 signals

– Typically used to connect a modem to a computer

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External Interface (cont’d)• Transmission protocol uses three phases

– Connection setup• Computer A asserts DTE (Data Terminal Equipment) Ready

– Transmits phone# via Transmit Data line (pin 2)

• Modem B alerts its computer via Ring Indicator (pin 9)– Computer B asserts DTE Ready (pin 4)– Modem B generates carrier and turns its DCE (Data Communication

Equipment) Ready

• Modem A detects the carrier signal from modem B– Modem A alters its computer via Carrier Detect (pin 1)– Turns its DCE Ready

– Data transmission• Done by handshaking using

– request-to-send (RTS) and clear-to-send (CTS) signals– Connection termination

• Done by deactivating RTS

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External Interface (cont’d)• Parallel printer interface

– A simple parallel interface

– Uses 25-pin DB-25• 8 data signals

– Latched by strobe (pin 1)

• Data transfer uses simple handshaking– Uses acknowledge (CK) signal

» After each byte, computer waits for ACK

• 5 lines for printer status– Busy, out-of-paper, online/offline, autofeed, and fault

• Can be initialized with INIT– Clears the printer buffer and resets the printer

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External Interface (cont’d)

11-49

Serial Data Transfer Asynchronous v.s. Synchronous

— Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication — Synchronous transfer does not transfer extra bits. However, it requires clock signal

Frame

Startbit B0 B1 B2 B3 B4 B5 B6

ParityStop bits

AsynchronousData transfer

SynchronousData transfer

clk

data

B0 B1 B2 B3 B4 B5

data

Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).

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8251 USART Interface

A7A6A5A4A3A2A1

IO/M

D[7:0]

RD RD

WR WRA0 C/D

CLK CLKTxC

RxC

TxD

RxD

8251 RS232

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11-52

Programming 8251

8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Stop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Parity0: odd1: even

Parity enable0: disable1: enable

Character length

00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate

00: Syn. Mode01: x1 clock10: x16 clock11: x64 clock

11-53

Programming 8251

8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enableDTR: data terminal ready, DTR pin will be lowRxE: receiver enableSBPRK: send break character, TxD pin will be lowER: error resetRTS: request to send, CTS pin will be lowIR: internal resetEH: enter hunt mode

11-54

Programming 8251

8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

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Simple Serial I/O Procedures

Read

start

Check RxRDY

Is it logic 1?

Read data register*

end

Yes

No

* This clears RxRDY

Write

start

Check TxRDY

Is it logic 1?

Write data register*

end

Yes

No

* This clears TxRDY

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Errors

– Parity error: Received data has wrong error -- transmission bit flip due to noise.

– Framing error: Start and stop bits not in their proper places.

• This usually results if the receiver is receiving data at the incorrect baud rate.  

– Overrun error: Data has overrun the internal receiver FIFO buffer.

• Software is failing to read the data from the FIFO.

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Programmable Timer 8254

11-58

8254 Programming

11-59

8254 Programming

• Each counter may be programmed with a count of 1 to FFFFH. – Minimum count is 1 all modes except 2 and 3

with minimum count of 2.

• Each counter has a program control word used to select the way the counter operates. – If two bytes are programmed, then the first byte

(LSB) stops the count, and the second byte (MSB) starts the counter with the new count.

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8254 Read Back Command

8254 Read Back Command

1 1 COUNT STATUS CNT2 CNT1 CNT0 0

NULL COUNT: goes low when the new count written to a counter is actually loaded into the counter

8254 status word format

OUTPUTNULL

COUNT RW1 RW0 M2 M1 M0 BCD

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8254 Modes

• Mode 0: An events counter enabled with G. – The output becomes a logic 0 when the control word is written and

remains there until N plus the number of programmed counts.

Mode 1: One-shot mode. – The G input triggers the counter to output a 0 pulse for `count' clocks. – Counter reloaded if G is pulsed again.

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8254 Modes

• Mode 2: Counter generates a series of pulses 1 clock pulse wide. – The seperation between pulses is determined by the count. – The cycle is repeated until reprogrammed or G pin set to 0.

– Mode 3: Generates a continuous square-wave with G set to 1. • If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.

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8254 Modes

• Mode 4: Software triggered one-shot – (G must be 1).

• Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

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Motor Control

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Motor Control

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DMA• Direct memory access (DMA)

– Problems with programmed I/O• Processor wastes time polling

– In our example

» Waiting for a key to be pressed,

» Waiting for it to be released

• May not satisfy timing constraints associated with some devices

– Disk read or write

– DMA• Frees the processor of the data transfer responsibility

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DMA Example• A hard disk data transfer rate of 5MB/s

– One byte every 200 ns !!

• A microprocessor hardly can execute even one instruction in 200 ns.– Multiple instructions would be required to

accomplish data transfer• read the byte from the hard disk• place it in memory• increment a memory pointer• test for another byte to read

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DMA

11-70

DMA

• DMA is implemented using a DMA controller– DMA controller

• Acts as slave to processor

• Receives instructions from processor

• Example: Reading from an I/O device– Processor gives details to the DMA controller

» I/O device number

» Main memory buffer address

» Number of bytes to transfer

» Direction of transfer (memory I/O device, or vice versa)

11-71

DMA• Steps in a DMA operation

– Processor initiates the DMA controller • Gives device number, memory buffer pointer, …

– Called channel initialization• Once initialized, it is ready for data transfer

– When ready, I/O device informs the DMA controller• DMA controller starts the data transfer process

– Obtains bus by going through bus arbitration– Places memory address and appropriate control signals– Completes transfer and releases the bus– Updates memory address and count value– If more to read, loops back to repeat the process

– Notify the processor when done• Typically uses an interrupt

11-72

I/O Data Transfer (cont’d)

DMA controller details