10/1/2014 Memory and I/O subsystem Reference: Introduction to Digital System by Ercegovac, Lang & Moreno, Wiley Publisher.

04/11/23

Memory and I/O subsystem

Reference: Introduction to Digital System by Ercegovac, Lang & Moreno, Wiley Publisher

04/11/23

Basic components of a computer

• PROCESSOR;

• MEMORY SUBSYSTEM;

• INPUT/OUTPUT (I/O) SUBSYSTEM

04/11/23

Memory hierarchy

04/11/23

Specification of a simple processor System

04/11/23

Memory Subsystem

04/11/23

Entity Declaration of memory Subsystem

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE WORK.comp_pkg.ALL;

ENTITY Memory IS

PORT (Addr : IN MAddrT ; -- memory address bus

Length : IN STD_LOGIC; -- byte/word operand

Rd, Wr : IN STD_LOGIC; -- access control signals

Enable : IN STD_LOGIC; -- enable signal

Rdy : OUT STD_LOGIC; -- access completion signal

Data : INOUT WordT ); -- memory data bus

END Memory;

04/11/23

I/O subsystem

04/11/23

Entity Declaration of I/O subsystem

LIBRARY ieee;USE ieee.std_logic_1164.all;USE WORK.comp_pkg.ALL;ENTITY IO ISPORT (Addr : IN IOAddrT ; -- I/O address busLength : IN STD_LOGIC; -- byte/word controlRd, Wr : IN STD_LOGIC; -- I/O access controlEnable : IN STD_LOGIC; -- I/O enable controlRdy : OUT STD_LOGIC; -- I/O completion signalData : INOUT WordT ); -- I/O data busEND IO;

04/11/23

PROCESSOR

• Processor state• 32 general-purpose registers (32-

bits wide), called R0, R1, ..., R31;• a 24-bit Program Counter register

(PC);• a 4-bit Condition Register (CR); and• a 32-bit Instruction Register (IR).

04/11/23

Processor State

04/11/23

Behavior of Processor

04/11/23

Behavior of Instruction

04/11/23

INSTRUCTION SEQUENCING

• SEQUENTIAL UNLESS– 1. UNCONDITIONAL BRANCH– 2. CONDITIONAL BRANCH

04/11/23

Instruction Format

04/11/23

Instruction Set

04/11/23

Instruction set (cont.)

04/11/23

Instruction set (cont.)