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1005AS ^AORMI 01 DIDRMOAMSX5PRa December 20-21, 2005, Johor
Bahru, Johor, MALAYSIA
Tunable Level-Shifter / Buffer for Dual Supply Systems and
Low-PowerClock-tree Design in Deep-Submicron Application
Sajedur Rahman', Abu Baker', Magdy Bayoumil, and Hussein Bin
Ahmed2
'The Center for Advanced Computer StudiesUniversity of Louisiana
at Lafayette, USA
2University Technology MalaysiaSkudai, JB, Malaysia
Abstract - A new architecture for Analog tunablelevel-shifter is
introduced in the 130nm CMOSprocess. As the transistor keeps on
shrinking, lowpower design becomes more challenging. Dualsupplies
are used for many low-power applications andneeds level-shifter
between the low Vdd and High Vddcritical path. Similarly, although
the die sizes areshrinking but the high speed VOs are relatively
largerand hence use higher Vdd supply, and hence
needslevel-shifters in between the core and the /O circuits.Also
the clock trees are major source for powerdissipation in present
day high-speed design. Reducingthe clock swings within the tree and
the branches canhelp reduce the overall power dissipation for the
chip.The new tunable - Level shifter takes in different
inputvoltages and shifts it to 1.2V-I.5V outputs. The inputvoltage
can range from 0.45V to Vdd, while thethreshold for the shifter is
tuned using a reference-voltage, thus controlling the current
through the level-shifter/buffer. Modification has been done to
thecircuit for low-power application with minimaldegradation to the
performance.
1. Introduction
The exponential growth in the number of devicesper chip combined
with another increase in theiroperating frequencies results in a
dramatic growth ofoverall power consumption. For
example,extrapolating the trends in power dissipation for theIntel
processor family shows that by the year 2008, aprocessor would
consume 18kW of power [1]. As aresult, power management
increasingly becomes theprimary design objective for enabling
higher chipintegration levels. The use of multiple supply
voltagesat the gate level is an effective technique to limitdynamic
power consumption while preserving therequired performance [2]. As
we know that energyconsumption in CMOS circuits is proportional to
thesquare of the supply voltage. This makes dual supplyvoltage
usage popular for energy reduction. Since the
speed of a gate decreases with decreasing supplyvoltage, dual
supply voltage techniques put low-voltage gates on the noncritical
paths and high-voltagegates on the critical paths. This reduces the
energyconsumption in the low voltage gates while keepingthe circuit
delay unchanged.
While system busses found are typically 3.5V, thebreakdown
voltages in new process are typically onthe order of 2.5V, 1.8V,
and lower. Therefore, theinterconnection of these new circuits with
existinginfrastructures requires the application of low voltage(LV)
to high voltage (HV) level shifters. Along withcircuit integration,
the control of high voltage systems,such as MEMS, power converters,
and otherelectromechanical systems can be readily implementedin LV
logic with LV to HV level shifters. Therefore,level shifters can
provide an increased amount offlexibility to the designer for
specific applications,while at the same time, allowing for standard
modulesto be built that can be applied to broader
applications.Here, this flexibility is realized through
constructingthe level shifters entirely from the LV process.
Assuch, data inputs, logic operations, and controloperations can be
performed in efficient LV logic,while its output signal is at the
natural HV level of thesystem being interfaced to.
On the other hand, as technology advances,systems are operating
at very high frequencies. Thisleads to much more power consumption
and muchshorter signal transition time. As a result, power
andtransition time becomes the key objectives of clocknetwork
design. Therefore, the primary objective ofclock tree design is to
minimize the signal skew atsinks. In another word, reducing the
clock swingswithin the tree and the branches can help reduce
theoverall power dissipation for the chip.
The paper is organized as follows: Section 2describes the
circuit schematic for the level Shifterwith Low Power Mode
Transistor Stacking. Section 3gives the simulation set up and power
analysis withleakage issues. Section 4 describes the summary.
0-7803-9431-3/05/$20.00 02005 IEEE. 311
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2. Circuit Schematic for the Level Shifterwith Low Power Mode
Transistor Stacking
When using two supply voltages, the circuitrequires level
converters (LCs) at the interface of highVDD gates and low VDD
gates to block the staticcurrent which occurs if a low VDD gate
drives a highVDD gate. In this paper we have proposed the
levelconverter through differential pair circuit.
The basic MOS differential pair has been used toimplement the
level shifter. It consists of two-matchedenhancement MOSFETs MO and
M5, biased withconstant-current source through M4. Figure 1
depictsthe schematic for the proposed level converter design.
Figure 1: Circuit Schematic for the Level Shifter with lowpower
mode transistor stacking and the control switch M34.
The load PMOS with diode connected currentmirror tries to
maintain the constant and same currentthrough the two 'legs- the
pair ofNMOS and PMOS'on the left and right. For a specific Vref it
causescertain amout of current to flow through the left leg(pair of
NMOS and PMOS). Due to the left PMOScurrent mirror it tries to
force same current through theright leg or pair ofNMOS and PMOS on
the right side.If the vinput to the other leg is less than the vref
i.e.logic 'zero' then it allows less current to flow throughthe
right pair. This in tum forces the additional currentdue to the
current mirror to flow out into the inverter atthe output of OTA.
This cufrent flowing out of theOTA makes high voltage at the input
of inverter andhence causes the output of the buffer to be
zero.
Similarly if the vinput is greater than the specific vrefi.e.
logic '1' then it causes the more current to flow onthe right hand
pair compared to the current due to thecurrent mirror. Hence the
additonal current comesfrom the current flowing from the capacitors
at theinput of the inverter. Thus the voltage at the input ofthe
inverter goes to zero and thus forcing Vdd or Highat the output.
Thus by setting the different vrefwe canset the switching voltage
of the buffer and allow thelow input voltage to be shifted as
higher voltage at theout put of the buffer by the inverter.
The PMOS switch M34 in the diagram is used forcontrolling the
voltage to the current source M4transistor of the buffer. We can
also use NMOSinstead of the PMOS for controlling the bias
current.We can completely shut off the buffer using the Vrefinput
signal when it is not in use for power savingusing logic '1' and
vice versa if we are using theNMOS switch. The reason for using the
PMOS insteadof the NMOS is that, in the case where the Vref is
verylow e.g. 0.45v or lower the NMOS would tend to shutdown and
choke the current source and the rise and falltime perfornance at
lower voltage would tend todegrade. On the other hand using the
PMOS has theproblem of higher power dissipation at shut down
statecompared to the NMOS at can be seen from theleakage analysis
table below.
Figure 2: The Schematic for the bias circuit for the
levelshifter.
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The good thing about the PMOS switch is that atlower Vref
voltage the PMOS M34 allows morevoltage flow through it and drives
the current sourceharder which is needed for faster rise and fall
time forsmaller input voltage while at higher Vref it reducesthe
voltage to the current source since the buffer doesnot need the
extra voltage while shifting betweenrelatively higher voltages and
thus adaptivelymaintaining a steady rise and fall time throughout
thedifferent input spectrum. But in most of the casesusing a NMOS
would serve better purpose becausemost of the levels shifting now a
day are done fromvoltage level above the 0.45v. Figure 2 describes
aboutthe biasing circuit.
The other configuration without the NMOS orPMOS switch and the
current source M4 is directlyconnected to the bias circuit without
the switch. Figure3 illustrates about it.
Figure 3: The schematic for the non-stacked output ofthebuffer
for better rise and fall time.
3. Simulation Setup
The simulation was done with the cadencespectre for the 130nm
process for the level shiftingfrom 0.65v and 0.85v to the 1.2v. The
duty cycle wasset at 37.5 in order to simulate the random data
typethat the buffer may be used in real application. Thesimulation
setup was done for leakage (when total shut
off condition) and when the buffer is having a steadydata
through it. It was simulated both at 250Mhz andIGhz. Figure 4 and
Figure 5 show the level shifteroutput at 250 MHz and IGHz
respectively.
Figure 4: Simulation for at 250 MHz from .065v to I .2v.
Figure 5: The Simulation for the level shifting at I Ghz
from0.65v to 1.2 v.
3.1 Advantages of the Level ShifterGood feature of this Level
shifter is that it is
tunable. Moreover, in this buffer we need only singlepower
supply rail instead of dual. That would saveboth the cost and space
on the chip die. All thetransistors are ofthe same process unlike
other designswhere it uses two different types of transistors,
Highvoltage and Low voltage for the level shifting. Alsothis level
shifter at smaller process, with the transistorshaving a higher
unity gain frequency means it hasmore bandwidth due to smaller gate
capacitances Cgand the Wu (unity gain frequency) = Gm/Cg, hence
itcan be used is the low power clock tree design and canlevelshift
the clock at very high frequency withtolerable amount of signal
integrity.
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There is trade-off between the low powerimplementation and the
performance because the riseand fall time tend to degrade with the
transistorstacking but reduces the power. Another importantfeature
of using this buffer is that by setting thethreshold voltage on the
buffer we can guarantee theswitching of the output only above or
below the Vrefthus giving more control over the buffer
withouthaving to resize the transistors for applications
withdifferent switching thresholds.
Table 1: Non-stacked transistor data at 250 MHz.
kin Rise time (ps) Fall time (ps) Power (W)0.85 53.23 38.31
14.09%0.65 56.88 66.83 8.33u
Table 2: Non-stacked transistor data at 1 GHz.
1rin Rise time (ps) Fall time (ps) Power (W)0.85 88.4 73.46
8.989j0.65 56.88 66.83 9.75uTable 3: Stacked transistor without
PMOS control gate M34
at 250 MHz
Table 4: Stacked transistor without PMOS control gate M34at I
GHz.
rin Rise time (ps) Fall time (ps) Power (W).85 116.6 87.75
7.98u0.65 82.77 81.6 9.3u
Table 5: Stacked transistor with PMOS gate M34 and non-stacking
at 250MHz.
Yin Rise time (ps) Fall time (ps) Power (W)0.85 89.8 87.75
8.22u0.65 57.6 69.5 8.75u
3.2 Leakage AnalysisFor the leakage analysis we turned off the
N/PMOS
switch (M34) that feeds the voltage to the cufrentsource and
provide input clock and then steady voltageto the input of the
buffer. In the other scenario we tumoff all the inputs to buffer as
well and then measure thepower dissipation through the transistors.
The dataobtained from these set up are given in tables below.
Itseems that the using NMOS switch performs better interms of
reducing the power when turned off becausewhen the NMOS is used, we
need to provide a zerovoltage to the Vref and that in tum not only
restrictsthe voltage to the current source but also tums of
thecurrent flowing through the Vref transistor, whileusing PMOS it
only shuts off the current source but theVref transistors remains
turned on thus causing more
power dissipation. Hence it would be a better option touse the
NMOS switch when using the buffer in the lowpower clock tree design
where the specific clock nodeneeds to be tumed of for a significant
amount of timeas opposed to the level shifting of voltage from
onelow to high.
Table 6: Buffer off (Using PMOS switch).
Vinpu' Pwr Dissipation (W)Clk swing 0.85v 1.09uConstant 0.85v
1.05uConstant 0 v 1.049u
Table 7: Buffer off (Using NMOS switch).kinput Pwr Dissipation
(W)Clk swing 0.85v 470nConstant 0.85v 459nConstant 0 v 31 Sn
4. SummaryWe targeted gate level power optimization with
dual-supply voltages. We have shown that dual-voltage approach
can achieve significant power savingwithout degrading timing
performance of the circuit.In this paper, a new architecture of
tunable thresholdlevel shifter has been presented with some
poweranalysis. Thus this analog buffer could be integrated aspart
of the analog I/O ring as oppose to be part of thedigital on chip
thus saving on chip space and die size.
References
[1] Chan P.K., Siek L., Lim T., Han M.K.,"Adaptive-biased buffer
with low inputcapacitance," Electronics Letters, Volume36, Issue 9,
pp. 775 - 776, 27 April 2000.
[2] Doutreloigne J., De Smet H., Van den Steen J.,Van Doorselaer
G, "Low-power high-voltageCMOS level-shifters for liquid crystal
displaydrivers," The Eleventh International Conferenceon
Microelectronics, pp. 213 - 216, 22-24 Nov.1999.
[3] Pan D., Li H.W., Wilamowski B.M., "A lowvoltage to high
voltage level shifter circuit forMEMS application," Proceedings of
the 15thBiennial Microelectronics Symposium, pp. 128 -131, 30th
June-2nd July 2003
[4] Kyoung-Hoi Koo, Jin-Ho Seo, Myeong-LyongKo, Jae-Whui Kim, "A
new level shifter in ultradeep sub-micron for low to wide range
voltageapplications," Proceedings of the IEEEInternational on SOC
Conference, pp. 155 - 156,12-15 Sept. 2004.
314
[in Rise time (ps) Fall time (ps) Power (W)0.85 1j16.6 85.9
6.847u0.65 83.17 79.9 7.96u