1 TM freescale - NXP Semiconductors · 2018. 8. 21. · BK 1 RD 2 BL 3 + 14C8 VCC_HOT_3.3 C32 330uF 25V + VCC_12 C35 330uF 25V + 330uF C33 25V 17 GND_P17 GND_P3 3 GND_P5 5 GND_P7

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2 3

semiconductor

TM

Project:

D

4 5 86

Date Changed:Title:

by

B B

Gary Milliorn

Engineer:

Steve Foster

Revision:

Tiffany Tran-Chandler

7700 W. Parmer Ln

Cass Arnett

Austin, Texas 78729freescale

C

Freescale Semiconductor

C

semiconductor

TM

freescale

87654321

1

Gary Milliorn1.03

01HPCN: Argo Navis

Cover StoryThursday, February 1, 2007

2:05:21 pmPage:

7

A

D

Time Changed:

HPCN: High-Performance Computing platform for Networking

A

42PCIExpress Slot #1

QuadPHY Ports34

loved can be lost. All rights reserved. No warranty is made,

04

VCORE Power Supply

383940

DDR2 DIMM #1

25

DDR2 DIMM #2

V1.02 2006Nov07 PCB Tweaks

Contents

35

DDR1 DIMM #122

10SERDES and 1.8V Power

Global Bypass, Mounting, etc.

USB Ports

07

All information is subject to change without notice.

5.

M1573 PCI, RTC, LPC and Misc

Power Entry, Switches

Contents

20

05Placement and PCB Stackup

DDR1 Termination

Debug, LEDs

52

57

06 Hot Power Supplies

LPC Flash54PIXIS System Logic, Part 114

PIXIS System Logic, Part 215

this product.

13

Revision:

CompactFlash Header

44

Flash and PromJet Headers

MC8641D SERDES #1

Ethernet Port Connectors #1/#2

32

41MC8641D SERDES #2

MC8641D LocalBus Interface

The sheet-to-sheet cross reference format is:

27

MC8641D Control Block

37

Components with the label "No_Stuff" are not to be installed bydefault; they are for test or manufacturing purposes only.

C123

DDR1 DIMM #2

DDR2 Termination and Power

50 AC97 Codec

PEX Alternate Slot #1 and MidBus Probe45M1573 ULI PEX Connection46

23

PCI Isolation Buffer16

VCC_3.3

LocalBus DebugPage

4.

3

08

MC8641D Power part 1MC8641D Power part 2

1.2V power

and ground unless explicitly shown otherwise. Global power

C

11System and PHY Clocks

This schematic is provided for reference purposes only.

1

No warranty, expressed or applied, is made as to theaccuracy of the information contained herein. ContactFreescale Sale/FAEs to obtain the latest information on

4 5 6

51

55

17

COP and Debug Interfaces

SIO53 AC97 Audio Connectors

I2CBus Devices

21

MC8641D DDR Interface #2

24

D

12SERDES (REFCLK) and BCLK Clocks

Engineer:semiconductor

MC8641D Quad Ethernet MAC

28

43

30

VCORE

B

7

29

connections are:

DATE

Sheet VertZoneLetter HorizZoneNumber

of IBM. Other trademarks are the respective property of theirrespective copyright holders. Anyone perfect must be lying,

Initial version

Unless otherwise specified:All resistors are SMD0402, in ohms, 0.08W, +/-5%

47

PCI Slots #1 and #2

Part numbers used are for reference only; compatibleparts may be used; refer to the bill of materials.

49 M1573 SATA + IDE48

Page

Schematic Notes1.

2.

7

VCC_5

3.

4

VCC_1.2

anything easy has it’s cost, anyone plain can be lovely, anyone

33pF

09

Integrated circuits have default connections to power

6.

7.

VCC_2.5

Freescale and the Freescale logo are registered

2

TM

1 2 3

02Block Diagram

01

18Configuration Switches

apply (i.e. PCI). Little-endian numbering is noted at thesource component.

19

M1573 USB + APIC

56

MC8641D DDR Interface #1

8

A

B

D

Date Changed:

Time Changed:


Serial Ports 1 and 2

26

36

QuadPHY MAC

GND

VCORE Power Supply, cont’d

null

null1

All buses follow big-endian bit numbering order (bit 0 is

C

freescale

QuadPHY Power31

CHANGES

V1.0 2005Aug03

Title:Project:

Austin, Texas 78729

33

Cover PageBoard impedance is 55 +/- 5 ohms. General Information

All capacitors are SMD0402, in microfarads (uF), +/-20%.

Page:

A

express or implied.

8

Platform Power

65

No

_Stu

ff

7700 W. Parmer Ln

Ethernet Port Connectors #3/#4

V1.0a 2006Feb27 Initial production

Gary Milliorn1.03

02HPCN: Argo Navis

Information, pleaseThursday, February 1, 2007

2:05:47 pm

the most-significant bit), except where industry standards

trademarks of Freescale Semiconductor. PowerPC is a trademark

All ferrites are Z=50 ohms at 100 MHz.All fuses are self-resetting polyswitch (PTC) devices.

REV

03

All inductances are in microhenries (uH).

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Bus

7700 W. Parmer LnAustin, Texas 78729

C

A

US

B

AU

DIO

PromJET

DDR #1

8

7 8

Serial

RJ45MAG

RJ45MAG

RJ45MAG

Engineer:Revision:

6

Local

VCORE

SA

TA

2 31 5 6

PEX Slot

PEX Slot

PC

I 1

PC

I 2

TM

MC8641D

Title:

7

Group

LPC

PEx

PEx

Flash

SIO

PA

TA

C

54321

M1575

CF+

DDR #2

A

B

Date Changed:

Time Changed:

PIXIS

Clock

Page:Project:

D

VSC8244QuadPHY

RJ45MAG

Gary Milliorn 031.03

HPCN: Argo NavisBlock Diagram

Thursday, February 1, 2007

2:05:55 pm

4

B

D

Flash

freescaleFreescale Semiconductor

semiconductor

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Time Changed:Engineer:

Revision:Page:

LAYER 3

Batt.

CO

P

Su

per

IO

LP

CF

lash

AC97

VCORE

VD

D_P

LA

T

MPC9855

CONFIG SWITCHES

0.5oz0.5oz

LAYER 1

SIGNAL: 7

1.0oz

21

8

VT

T P

LA

NE

+ PO

WE

R #2

USB

RS

T

PW

R

FAN

RST

Title:

SIGNAL: 2

PWR

LE

D

LE

D

STATUS LEDS

PLANE: GND 1

SV

C

QPHY

PS/2

29L

V64

1

Note: Not Definitive -- see

PC

IExp

ress 4X

SATA3

SATA4

432

0.5oz0.5oz

SIGNAL

SIGNAL

PLANE

Project:

ON

A12V

AT

X P

OW

ER

APA150

8

A

B

D

Date Changed:

PLANE

LAYER 2

LAYER 4LAYER 5

LE

D

LE

D

LE

D

LE

D

Pro

mJe

t

IDE

SATA1

APA PROG

SIGNAL

1.5oz

A

B

freescale

Design Workbook.

PLANE: VCC_5, VCC_HOT_xxx

PLANE: GND

DD

R #1 D

IMM

#1

DD

R #1 D

IMM

#2

7

RJ45

SIGNAL: 5PLANE: VCC_3.3, VCORE

SIGNAL: 3SIGNAL: 4

PLANE: GND

244mm (9.6")

SIGNAL: 6

244mm (9.6")

D

1

RJ45SER #1

DD

R #2 D

IMM

#2

5 6 7

RJ45

65

SATA2

Mounting holes, positioned per microATX spec.

M1575

LT1331

PC

I 2

DD

R #2 D

IMM

#1

LE

D

LE

D

Mounting holes for socket.

MC8641D

AUDIO

1.0oz

BURIED CAP LAYER OPTION

USB

USBHDR

MIC2077

LE

D

LE

D

SIGNALSIGNALPLANE

LAYER 6LAYER 7

PC

IExp

ress 8X (in

16X slo

t)

PC

I 3

LAYER 8

semiconductor

TM

4

SIGNAL

1.5oz

SIGNAL: 1

1.0ozPLANE

1.0oz

SIGNAL

C

LE

D

LE

D

LE

D

LE

D

INFO LEDS

158.75mm (6.25")

VT

T P

LA

NE

+ PO

WE

R

RJ45

LAYER 9

LAYER 12

3


C

LE

D

LE

D


HPCN: Argo NavisPlacement Guide and PCB Stackup


2:06:05 pm

LAYER 10LAYER 11

.0930.5oz1.0oz


PLANE

AT

X P

OW

ER

CHASSIS POWER LED

ATX CHASSIS POWERVCC and VCC_3.3 on separate power planes.

LOCAL POWER

OPTION22ms R-C delay, or FPGAcontrol (not both).

22ms

CHASSIS RESET SWITCH

FORCE PSU ALWAYS ON

LOCAL RESET SWITCH

(3V)

LOCAL EVENT SWITCH

semiconductor

TM

321

8


65

A

4321

4 5


HPCN: Argo NavisPower Entry, System Reset


2:06:19 pm

6 7 8

B

D

Date Changed:

7

Engineer:

CUBE FANSINK HEADER

Revision:Page:Title:

Project:7700 W. Parmer LnAustin, Texas 78729

C

A

B

D

C

freescale

CHASSIS POWER

PC FANSINK HEADER

Time Changed:

100

header.1x2J5 1

2

0.1uFC39

14E2

U2

74lvc1g125.sc70

VCC_3.3=VCC_HOT_3.3

2

1

4

R45

VCC_HOT_3.3

VCC_12N

C430.1uF

14D2

VCC_5

14C2

VCC_5

54D1

VCC_3.3

R52

10K

J4header.1x2

1

2

VCC_3.3

25V

C38330uF

+

R46

4.7K

VCC_12

330uFC36

25V

+

VCC_3.3

220

R54

10uF

+

VCC_HOT_3.3

4.7K

R53

VCC_3.3=VCC_HOT_3.3

74lvc1g125.sc70

U12

1

4

C41

R57

sw.1spdtSW7

1

2

3

54D1

0.1uF

sw.1spdtSW9

1

2

3

47K

VCC_12_BULK

R58

10

C40

SW10

sw.1spdt1

2

3

VCC_5

R43

4.7K

VCC_12 VCC_HOT_5

48C7

0.1uFC37

R49

3.3K

J2atxpwr_12v_2x2vert

GND11

2GND2 P12V3

3P12V4

4

VCC_3.3

R48

6.8K

R50

100

header.1x31

2

3

14C8

14D2

3.3K

R47

25V

330uFC34+

14B2

J8

R55

10

14C2

VCC_5

10uFC42

+100

R51

conn.fan.3pos

P2

BK1

RD2

BL3

+

14C8

VCC_HOT_3.3

C32330uF

25V

+

VCC_12

C35330uF

25V

+330uF

C33

25V

17GND_P17

GND_P33

GND_P55

GND_P77

PS_ON14

PWRGOOD8

VCC_P1919

VCC_P2020

VCC_P44

VCC_P66

VSTDBY9

+12V_P1010

+3.3V_P11

+3.3V_P1111

+3.3V_P22

-12V_P1212

-5V_P1818

GND_P1313

GND_P1515

GND_P1616

No_Stuff

header.1x2J7

1

2

atxpwr_2x10vert_nopeg

J6

J3header.1x2

1

2

VCC_HOT_3.3

R1 220

R56

10

R44

220K

FAN_TACH

FAN_PWM

NC

NC

NC

NC

NC

SB_RSMRST

14C8

EVENT*

SHORT_POWERFANPWR

PWRSW*PWRSWS*

PS_ON*

RSMRST*

SB_RSMRST*

PWRGD

Date Changed:

TOP LAYER POUR FOR AGNDSEE LAYOUT RULES FOR VIAS TO GROUND PLANE

ACTEL POWER SEQUENCING

Add 0.5 square inch fill to ground tab.

Add 0.5 square inch fill to ground tab.

43

Revision:Page:Title:7700 W. Parmer Ln

B

D

2

A

Engineer:Project:

RES

1

C

TM

semiconductor

Cass Arnett 061.03

HPCN: Argo NavisHot Power Supplies


2:07:28 pmfreescaleFreescale Semiconductor

C

Austin, Texas 78729

2 43 65 871

5

A

Time Changed:

B

D

6 7 8

SYNC19

17V

BIA

S

VIN114

15VIN2

VIN316

2VSENSE

12PGND2

PGND311

10PH1

PH29

8PH3

PH47

6PH5

POWERPAD21

4PWRGD

20R

T

18SS_ENA

U18tps54310pwp.htssop20

1AGND

BOOT5

COMP3

PGND113

2IN

OUT4

5nRESET_FB

C1461.0uF

750

R68

1%

GND3

GND_TAB6

2IN

OUT4

5nRESET_FB

ddpak5

TPS72525KTT

U7

1ENABLE

GND3

GND_TAB6

1%

1.0uFC147

ddpak5

TPS72518KTT

U8

1ENABLE

1

rc1210

10R4

No_Stuff

VCC_HOT_3.3

R67

3.74K

CR1

MBRS360T3

smc_403

No_Stuff

21

smc_403

MBRS360T3

CR2

No_Stuff

2

R66

18K

1%

71.5K

R65 C1450.1uF

10.0K

R69

1%

100uFC143

VCC_HOT_3.3

C148

0.047uF

C144100uF

R64

10K

No_Stuff

C1381.0uF 1.0uF

C139

3.3UH

L3

1 2

C152470uF

+C140100uF

TP2

100uFC141

C1370.027uF

220K

R63

0.1uFC470

VCC_HOT_2.5

VCC_HOT_3.3

VCC_HOT_1.8

VCC_HOT_3.3 VCC_HOT_5

15B1

47pF

74lvc1g125.sc70

U56

VCC_3.3=VCC_HOT_3.3

2

1

456B1

C151

C1492200pF

C150

HOT_RST*

PS_H33_PG

C142100uF

2200pF

AREA_FILL

NC

NC

SH

OR

T_P

OW

ER

SH

OR

T_P

OW

ER

D

C

semiconductor

TM

5

54 8

2:07:37 pm

7

Place caps close to pins.

All grounds tied together at output caps.

621 3

2 31 7 86

Date Changed:

Time Changed:

A

B

D

Engineer:Revision:

Page:Title:

4

Freescale Semiconductor7700 W. Parmer Ln

Project:freescale

Austin, Texas 78729

C

A

B

VCC_3.3

14B2,56D1

8C8

Cass Arnett 071.03

HPCN: Argo NavisProcessor VDD (Vcore) Supplies


1%

680

R27

MBR0530

CR4

sod_123

cc0805

0.1uF

TP1

sod_123

MBR0530CR5

C18

NPO

cc0805

1uFC21

cc0805 25V

C25

1%

1000pFC27

25V

10nF

cc0805

1000pFC20

6

0

16.2K

R38

20D1

R37

16.2K 1%

C301uF

0.1uF

C24

25V

cc0805

2

VCC_12

8A1

12pFC804

VCC_5

R22

0

rc0603

C23

25V

cc0805

R42

0

rc0603

82.5K

rc0603

0

R41

0.1uF

8B1

30.1K

1%

R26

1%

R30

rc0603

100R36

cc0805

1uF

C17

C311uFcc0805

14C8

8B1

R40

23.7K

1%

No_Stuff

1uF

10nFC28

NPO

25V

cc0805

560pF

R31

10K cc0805

C19

8C8

C261000pF

C22

NPO

25V

cc0805

C2910nF

10K

R28

14C8,17C1

5

4

3

8C1

R34

2.40K

1%

1%

23.7K

R39

No_Stuff

1%

R29

130K

No_Stuff

10

R33

0

130K

R25

1%

0R23 VIN

142 14

VIN

2

43VPN1

VPN213

VREF2

1nPG

12

VCC_5

R32

TG216

37V

5_1

V5_

219

VCCA28

11VID0_LSB

10VID1

9VID2

VID38

7VID4

VID56

5VID6_MSB

36EN

ER

RO

UT

29

22FBn

21FBp

GND45

3HYS

ISH

34

35NC

25S

S

TG140

32CS1n

CS1p33

31CS2n

CS2p30

DA

C26

44DRIFT

39DRN1

DRN217

23DRPn

DRPp24

20DUAL

1

8C8

sc458.mlp44

U38

27A

GN

D

BG138

18BG2

BST141

15BST2

4CLSET

100

R24 0

20D1

BSTRCD1

ER

RO

UT

VREF

VREF

8B8

8D1

8D1

VCC_5

rc0603

R35

VTRC1

DAC

BG1

CFG_VID(6:0)

VPN2

VTRC2

ERC

SC458_AGND

CS1P

CS1N

CS2P

BST1

BSTRCD2

BST2

PG_DEL

PS_VCORE_PG

PS_CORE_EN

BG2

CLSET

CS2N

DRN1

DRN2

DRPNDRPP

HYS

ISH

SS

TG1

TG2

VCCA

VPN1

VCORE_SENSEpVCORE_SENSEn

Engineer:Revision:

Page:Title:Project:

7


C

A

B

D

Distribute caps along plane to processor.

Distribute caps along plane to processor.

DRNx is the "+" end of the inductor.CSxN is the "-" end of the inductor.

Route CS1x, CS2x, DRPx and FBxas differential pairs.

3

C


semiconductor

TM

7651 2 3 4 8

A

B

D

Date Changed:

Time Changed:

4 5 6

0.5..1.5V55A maximum

821

4

1 2 3

081.03

HPCN: Argo NavisProcessor VDD (Vcore) Supply, Part 2


2:07:45 pmCass Arnett

4

1 2 3

so8

Q9

IRF7832

5 6 7 8

C11

2.5V390uF

+

so8

Q6

IRF7832

5 6 7 8

C8070.1uF

VCORE

R18

47K

C4740.1uF 0.1uF

C806

18.2K 1%

C410uF

Q5

so8

5 6 7 8

4

1 2 3

R15

2 3

7B7

7B7

mbrs140lt3.smb403aD1

No_Stuff

2

1

IRF7832

16.2K

so8

IRF7821

Q4

5 6 7 8

4

1

D2mbrs140lt3.smb403a

No_Stuff

2

1

7B7

7B7

R11

1%

6 7 8

4

1 2 3

18.2K

R14

1%

5 6 7 8

4

1 2 3

so8

Q3

IRF7821

5

R21

26.1K

7C7

7C7

7C7

so8

IRF7832

Q1

Q8

so8

5 6 7 8

4

1 2 3

1%

33K

TH2

R16

0

IRF7821

C610uF

390uFC15

2.5V

+C13390uF2.5V

+

C510uF

C4720.1uF 0.1uF

C473

47K

R19

7B7

0.1uFC471

47K

R17

C710uF

7B7

VCORE

C14390uF2.5V

+

2 3

NPO

25V

56nF

C9

cc0805

1%

R12

16.2K

1 2

so8

IRF7832

Q2

5 6 7 8

4

1

IRF7832

5 6 7 8

4

1 2 3

L1

0.50UH

100pFC16

2.5V390uFC12+

so8

Q10

+

VCC_12_BULK

7C7

VCC_12_BULK

TH1

33K

25V

cc0805

L2

0.50UH

1 2

C10390uF2.5V

5 6 7 8

4

1 2 3

NPOC8

56nF

R20

C210uF

so8

Q7

IRF7821

0

R13

C310uF

47K

TG1

BG1

CS1N

DCR_DR1 DRPP

DRPN

DCR_DR2

CS2NTG2

BG2

DRN2

DRN1

Time Changed:

2

1.05 V

Rset = sum of R680 + R156 (switch open)Rset = R680 (switch closed)

56.2K

7700 W. Parmer LnRevision:Austin, Texas 78729

C

1.0-1.2V @ 9A

7654

freescale

1.10 V

VCC_PLAT

B

VCC_PLAT

8


A

B

D

Freescale SemiconductorTM

31

Engineer:

1

4 5 6 7

Date Changed:

32

A

CFG_PLATVDD

0 / OFF1 / ON

Page:semiconductor

Title:Project:

8

5

Cass Arnett 091.03

HPCN: Argo NavisPlatform Power (nominally 1.1V)

Wednesday, February 14, 2007

10:56:47 am

D

C

Rset

VCC_PLAT SETTINGRset

42.2K

VCC_3.3

sop5

74cbtlv1g125dbv.so5

U25

A2

B4

GND3

OE1

VCC

47pF

C800

1%10.0K

R682

2200pF

C799

0.1uFC797

TP170

18K

R679

C791R677

10K

0.047uFC798

1%

14C8

C801

2200pF

1.0uF

1%

42.2K

R680

R678

71.5K

1.0uF

0.033uFC795

1%

R681

750

L13

1UH1 2

C803470uF

4V

+C7906.3V

100uFC796

1.0uFC792 C793

1.0uF

23VIN4

VIN524

VSENSE2

VCC_PLAT

4V

470uFC802+

13PH8

PH914

29POWERPAD

PWRGD4

RT

28

SS_ENA26

27SYNC

VB

IAS

25

20VIN1

VIN221

22VIN3

PGND217

PGND3

PGND418

19PGND5

6PH1

PH27

8PH3

PH49

PH510

11PH6

PH712

6.3V

14B2,56D1

tps54910pwp.htssop28U50

AGND1

5BOOT

3COMP

PGND115

16

14D8,17C1

1%

R156

14.0K

VCC_3.3

C794100uF

AREA_FILL

PS_PLATFORM_PG

PS_PLATFORM_EN

CFG_PLATVDD

VCC_3.3

7

Austin, Texas 78729

C

A

B

D

semiconductor

TM Page:Title:


8

C


765432

VCC_1.21.2v @ 3.3A

1

1 2 3 4

Cass Arnett 101.03

HPCN: Argo NavisGeneral 1.2V Power

Wednesday, February 14, 2007

5 6 8

Project:

Revision:7700 W. Parmer Ln

A

B

D

Date Changed:


VCC_5

4.7UH

L12

1 2

VCC_1.2

10:47:45 am

R516

18K

R518

750 1%

1.0uFC738

VCC_3.3

C744

47pF

14B2,56D1

+C740100uF

C7371.0uFR514

10K

C746470uF

R517

28.7K

1%

14C8

1%

71.5K

R515

C743

0.047uF

TP151

15VIN2

16VIN3

2VSENSEC7390.027uF

C7410.1uF

9

8PH3

PH47

PH56

POWERPAD21

4PWRGD

20R

T

18SS_ENA

SYNC19

17V

BIA

S

VIN114


1AGND

BOOT5

COMP3

PGND113

12PGND2

PGND311

10PH1

PH2

2200pF

C745

1%

R519

10.0K

AREA_FILL

PS_1.2V_PG

PS_1.2V_EN

C742

2200pF




C

A

B

D

C

8


semiconductor

TM

4

7

1 52

VCC_SERDESTypically 1.1V @ 3.3A

VCC_1.81.8V @ 3.3A

3

Cass Arnett 111.03

HPCN: Argo NavisSERDES 1.2V and PHY 1.8V Power


2:08:11 pm

1

6

8

A

2 3 4

Engineer:Revision:

Page:

5 6

B

D

Date Changed:

Time Changed:Title:

Project:

7

14C8

1%

71.5K

R505

R504

71.5K

1%

C732

47pF

VCC_SERDES

2200pF

C734

C728

2200pF

1%

14C8

R507

18K

C7220.027uF

18K

R506

R509

9.76K

C730

0.047uF

C7260.1uF

1.0uFC721

4.7UH

L11

1 2

C724100uF

C7181.0uF

VCC_1.8

47pF

C731

VCC_3.3

14C2,56C1

10K

R503

C733

2200pF

2200pF

C727

C736470uF

+

TP150

C7191.0uF

L10

3.3UH1 2

0.047uF

C729

+100uFC723

1.0uFC717

RT

20

SS_ENA18

19SYNC

VB

IAS

17

14VIN1

VIN215

16VIN3

VSENSE2

470uFC735

COMP

13PGND1

PGND212

11PGND3

PH110

9PH2

PH38

7PH4

PH56

21POWERPAD

PWRGD4

SYNC19

17V

BIA

S

VIN114

15VIN2

VIN316

2VSENSE

tps54310pwp.htssop20

U11

AGND1

5BOOT

3

PGND2

PGND311

10PH1

PH29

8PH3

PH47

6PH5

POWERPAD21

4PWRGD

20R

T

18SS_ENA

0.1uFC725


1AGND

BOOT5

COMP3

PGND113

12

1%

0.027uFC720

TP149

42.2K

R508

1%

R513

10.0K

VCC_3.3

14C2,56C1

R502

10K

VCC_5

VCC_5

1%

R511

750

750

R510

1%

10.0K

R512

1%

PS_SERDES_PG

PS_SERDES_EN

PS_ULI_1.8V_PG

PS_ULI_1.8V_EN

5 6 7 8

A


Project:

Very Short

C

A

No special match requirements.

Variable 1-200 MHz reference.SYSCLK Clock

No special match requirements.

Austin, Texas 78729semiconductor

TM

B

D

C

7700 W. Parmer Ln

876

Any Length

Fixed 125.0 MHz reference.


PHY Clocks

3 54

Very ShortVery Short

4


HPCN: Argo NavisSystem Clock Generator


2:08:21 pm

21

1 2 3

B

D

Date Changed:


0

R75

10

R79

6.3V22uFC156

OSCON

+ C1570.1uF 0.1uF

C158

33

6

19D1

23

7X1_ICLK

X28

R72 0

100

R74

V2

13V3

14V4

15V5

16V6

17V7

18V8

6

VDD1 VDD2

1R5

R62

22REF

3S0

S14

S25 10

V0

11V1

12

21

9

GND1 GND2

20

19PDTS

24R0

R125

26R2

27R3

R428

R81 33

U14ics525_02.ssop28

CLK

No_Stuff

0.1uF

C155

U9

EH2645TS-125.000M

125.000MHz

GND2 1

OE

OUT 34 V3.3V

VCC_3.3

51

R5

1

15B8

15A1

3

15B8

R78 33 1

33R73

2

R70

7

100

R80

0.1uF

0.1uF

C154

5

15B1

R76

100

C159

6

1ICLK

8OE

2Q1

3Q2

4Q3

5Q4

VDD7

0

R71

5

MPC94551EFso8

U10

GND

5

15B1

0R82

VCC_3.3

30D1,32B1

No_Stuff

conn.sma

P7

0.1uF

P1

conn.sma

No_Stuff

4

4

2

VCC_3.3

C153

1

2

1

33R77

SYSCLK_V(7:0)

SRCCLK SYSCLK

SYSCLK_R(4:0)

SYSCLK_S(2:0) 0

0

2

3

NC

NC NC

SYS_REFCLK

POWER_TRACEICSCLKPWR

PHYCLKPWR SHORT_POWER PHYCLK(0:2)PCLK1CM_MAXUTPCLK

SHORT_POWERMBUF1_PWR

UTLSYSCLK2CM_MAX

NC

SYSCLK_EN

1CM_MAXUTPHYCLK0

UTPHYCLK1 1CM_MAX

1CM_MAXUTPHYCLK2

NC

8

1 4

2

63

4

A

B

52 7 8

Time Changed:

D

REFCLK TERMINATIONBoth series and parallel are near the clock source.

TEST: Connect pin 1 to U53 pin 16

Date Changed:

2:08:30 pmTitle:

Project:Engineer:

to disable ULI REFCLK. Required to

Revision:Page:

C

BCLK Clock14.318 MHz reference.No special match requirements.

REFCLK (SerDes) Clock100.0, 125.0 or 156.25 MHz (common)Clocks routed as differential pairs.No special match requirements.

test Serial RapidIO modes.

A

6

7700 W. Parmer Ln

Very Short

Austin, Texas 78729


semiconductor

B

D

73

C

freescale51

TM

46A1

Gary Milliorn1.03

13HPCN: Argo Navis

RefClk (SERDES) and base clock.Thursday, February 1, 2007

R539 33

33R540

5

46A1

R538 33

0.1uF

C781

R534

33R563

R564 33

VCC_3.3

R530

5

1%

475

R532

0.1uF

C783

R536 33

51

R558

19C8,23D1,24D1,27D1,28D1,#6

54A1

C784

0.1uF

1

47C8Q1

3Q2

4Q3

5Q4

VDD7

R552

51

C777MPC94551EFso8

U54

GND

6

1ICLK

8OE

2

R546 33

VCC_3.3

VCC_3.3

50A1

0.1uF

R535

0

42C7

VCC_3.3

17D8

45A1

22uF6.3V

+

44C8

OSCON

C77522uF6.3V

+ C7790.1uF

OSCON

C782

R557

51

19C8,23D1,24D1,27D1,28D1,#6

14B2,17C8

42C7

VCC_3.3

R556

51

R560

51

R553

51 51

R554

51

R551

33R548

51

R550

R545

43B1

R547 33

C776

OSCON

+

33R544

33

R541

R542 33

6.3V22uF

14.318MHzU52

2GND OE

1

3OUTV3.3V4

VCC_3.3

33

C778

43A1

33R537

33R529

44C8

0.1uF

3 10

VD

D2

14

VD

D3

VD

D4

19 31

VD

D5

VD

D6

36

VD

D7

40

VD

DA

48

X22

1XIN_CLKIN

45A1

34

28OE_3

OE_422

16OE_5

OE_613

7OE_7

5REFOUT

SCLK24

23SDATA

SEL14M_25M27

26SPREAD

VD

D1

FS045

44FS1

FS26

4

GN

D1

GN

D2

15 35

GN

D3

GN

DA

47

46IREF

OE_043

37OE_1

OE_2

29

30DIF3_P

21DIF4_N

DIF4_P20

DIF5_N18

17DIF5_P

12DIF6_N

DIF6_P11

DIF7_N9

8DIF7_P

DIF_STOP25

ICS9FG108BG-LFT

tssop48

U53

41DIF0_N

DIF0_P42

DIF1_N38

39DIF1_P

32DIF2_N

DIF2_P33

DIF3_N

R533

51

45C1

C780

0.1uF

P9conn.sma

19D1

No_Stuff

VCC_3.3

2

51

R555

No_Stuff

0

51

R559

5

R531

C774

R549

51

45C1

R528

50.1uF

33R561

R562 33

1CM_MAX

RCLK1 REFCLK_SD1pDIFF_CLK

RCLK

NC

NC

R543 33

UTREFSD2P 1CM_MAX

UTREFSD2N 1CM_MAX

1CM_MAXUTREFSL1P

1CM_MAXUTREFSL1N

UTREFSL2P 1CM_MAX

UTREFSL2N 1CM_MAX

1CM_MAXUTREFTAPP

1CM_MAXUTREFTAPN

UTREFULIP 1CM_MAX

UTREFULIN

DIFF_CLK REFCLK_SLOT1n

RCLK4DIFF_CLK REFCLK_SLOT2pRCLK4 REFCLK_SLOT2nDIFF_CLK

RCLK5 REFCLK_TAPpDIFF_CLKRCLK5DIFF_CLK REFCLK_TAPn

RCLK6DIFF_CLK REFCLK_M1575pRCLK6 REFCLK_M1575nDIFF_CLK

POWER_TRACEREFCLKPWR2

POWER_TRACEREFCLKPWR1

RCLK1DIFF_CLK REFCLK_SD1n

RCLK2DIFF_CLK REFCLK_SD2pRCLK2 REFCLK_SD2nDIFF_CLK

RCLK3 REFCLK_SLOT1pDIFF_CLKRCLK3

1CM_MAX

M1575_BCLK

SIO_BCLK

RTC_CLK

AUD_CLK

POWER_TRACE REFCLKPWR3

REFCLKPWR0

1CM_MAX

UTRCLK

1CM_MAXUTREFSD1N

CFG_REFCLKSEL(2:0)

I2C2_SDAI2C2_SCL

1CM_MAX

1CM_MAX

UTBCLK 1CM_MAX BCLK

1CM_MAX

1CM_MAX

NC

1CM_MAXUTREFSD1P

NC

NC

NC

NC

CFG_REFSPREAD

NC

See MapFile

GND

B

D


C

semiconductor

TM

7

freescale832 6

Stephen Foster1.03

14HPCN: Argo Navis

PIXIS System Controller, Page 1Thursday, February 1, 2007

2:08:40 pm

541

1 2 3 4 5 6 7 8

A

B

D

Date Changed:




C

A

1

5C8

0

5

6

7

0.1uFC759

16V

2

0

0.1uFC757

16V

VDD_5G6

VDD_6G11

VDD_7H6

VDD_8H11

J6VDD_9

R15VPN

VPPP14

0

1

F7

VDD_10K6

K11VDD_11

L7VDD_12

VDD_13L8

VDD_14L9

VDD_15L10

VDD_16J11

VDD_2F8

F9VDD_3

VDD_4F10

VDDP_14M10

VDDP_15M11

VDDP_16

E7VDDP_2

VDDP_3E10

E11VDDP_4

F5VDDP_5

VDDP_6F12

VDDP_7G5

G12VDDP_8

K5VDDP_9

VDD_1

TCKP13

TDIR14

TDOR16

TMST15

P15TRST

VDDP_1E6

VDDP_10K12

L5VDDP_11

VDDP_12L12

M6VDDP_13

M7

E8

E9IO_E9

F1IO_F1

F13IO_F13

IO_F14F14

IO_F15F15

F16IO_F16

IO_F2F2

F3IO_F3

IO_F4F4

N14RCK

D9

E1IO_E1

IO_E12E12

E13IO_E13

IO_E14E14

E15IO_E15

IO_E16E16

E2IO_E2

E3IO_E3

IO_E4E4

E5IO_E5

IO_E8

D14IO_D14

D15IO_D15

IO_D16D16

D2IO_D2

IO_D3D3

D4IO_D4

IO_D5D5

D6IO_D6

IO_D7D7

D8IO_D8

IO_D9

C4

C5IO_C5

IO_C6C6

C7IO_C7

IO_C8C8

C9IO_C9

IO_D1D1

D10IO_D10

IO_D11D11

D12IO_D12

IO_D13D13

B9

C1IO_C1

IO_C10C10

C11IO_C11

IO_C12C12

C13IO_C13

C14IO_C14

C15IO_C15

IO_C16C16

IO_C2C2

C3IO_C3

IO_C4

B14IO_B14

IO_B15B15

B16IO_B16

IO_B2B2

IO_B3B3

B4IO_B4

IO_B5B5

B6IO_B6

IO_B7B7

B8IO_B8

IO_B9

A4

A5IO_A5

A6IO_A6

IO_A7A7

A8IO_A8

IO_A9A9

IO_B1B1

B10IO_B10

IO_B11B11

B12IO_B12

IO_B13B13

AGND_2

J3AVDD_1

J15AVDD_2

A10IO_A10

IO_A11A11

A12IO_A12

IO_A13A13

A14IO_A14

IO_A15A15

IO_A2A2

A3IO_A3

IO_A4

0.1uFC758

apa150.1of2.fbga256

U49

AGND_1H4

H15

16V

C756 0.1uF

10B1

VCC_HOT_2.5

32B1

12

7B1,56D1

4

TP166

11C1

C762

R525

10K

0

1

11A1

3

0.1uF 0.1uFC767

2

48C7

1

13

10K

R5240.1uF

19C1

19C1

19B1

18C1

7B1,17C1

9C1,17C1

C7510.1uF

2

C761

0

1

4

5

3

32B1

0.1uF

19B1,46C8,54B1

1

15C1,16B8

17B8,38B1

43B1,45A1

15C1,16B8

19C1

19C1

C753 C7550.1uF

10A1,56D1

TP164

0.1uFC763

VCC_HOT_3.3

15

11C1,56C1

11A1,56C1

14

18D1

16V

C760 0.1uF

24

25 26

3 4

5 6

7 8

9

14

15 16

17 18

19

2

20

21 22

23

0

11

13C1,17C8

conn.2x13J34

1

10

11 12

13

48D7

5D1

16B8

17B8,18B1

29B8,56C1

5B8

38C1,39C1,41C1

19D8,56B1

23D1,24D1,27D1,28D1

18D1

54B1

C7640.22uF

0.1uF

17B1,18A1

VCC_1.8

10K

R527

0.1uF

3

VCC_HOT_2.5

5D8

C765

48C7

0.1uFC771 C772

6

17A8,18B1

17B8

0.1uFC752

5B1

46C8

9B1,56D1

74lvc1g125.sc70

U512

1

4

0.1uFC769 C770

0.1uF

8

48C7

C7680.1uF

18D1

TP167

0.22uFC766

9B1

46C8

19C1

0.1uFC754

2

VCC_HOT_2.5

0.1uFC773

7B1

PEX_RST*

25B8,56C1

10

5

R526

9

CFG_PLATVDD

GEN_RST*

MEM_RST*

CFG_FLASHBANKCFG_FLASHMAP

CFG_PORTDIVLB_RST*

ASLEEP

PWRSW*PS_ON*

PS_CORE_ENPS_PLATFORM_EN

PS_1.2V_ENPS_SERDES_ENPS_ULI_1.8V_EN

SB_OFFPWR_S4_S5*

CFG_BOOTLOC(0:3)

CFG_VID(6:0)

CFG_BOOTSEQ(0:1)

CFG_REFCLKSEL(2:0)PWRSWX*

COP_HRST*

COP_TRST*HRESET_REQ*

CPU_TRST*CPU_HRST*EVENT*

SRESET_1*SRESET_0*

SPARE01*CFGDRV*

M1_DDR_IOPWRGDM2_DDR_IOPWRGD

SB_CPURST*

SB_INIT*SB_OFFPWR_S3*

SB_PWGRSMRST*

SMI*

PWRGD

10CM_MAX

10CM_MAX

PS_VCORE_PGPS_PLATFORM_PGPS_1.2V_PGPS_SERDES_PGPS_ULI_1.8V_PG

NC

NC

NC

10CM_MAX

COP_SRST*

PME*

PHYRST*

10CM_MAX

10CM_MAX

V3_CBE*(3:0)

V3_PAR

V3_AD(31:0)

APA150_VDDPWR 2CM_MAX

10CM_MAX

10CM_MAX

10CM_MAX

NC

NC

NC

NC

NC

7700 W. Parmer Ln

C

A

B

D

C


semiconductor

TM

1.03

HPCN: Argo NavisPIXIS System Controller, Page 2


2:09:03 pm

876321 54

1 2 3 4 5 6 7

A

B

D

Date Changed:

8


Revision:Austin, Texas 78729Page:Title:

Project:

2

12B1

3

Stephen Foster 15

0

0

14B8,16B8

16B8

6

5

4

19B1,32A1,46C8

51A8

3

1

3

TP155

33R523

1

41C1

2

4

16B8

47A8,51B1,54A1,55B1

17

38B1

26

19

16A8

7

38B1

28

31

1

39B1

VCC_HOT_3.3

J13

1

56A1

56A1

3

16A8

17B1,18A10

1

IO_T3T3

T4IO_T4

T5IO_T5

IO_T6T6

IO_T7T7

T8IO_T8

IO_T9T9

NPECL1H2

NPECL2H14

J2PPECL1

PPECL2

R5

R6IO_R6

R7IO_R7

IO_R8R8

R9IO_R9

T10IO_T10

IO_T11T11

T12IO_T12

IO_T13T13

T14IO_T14

T2IO_T2

P7

P8IO_P8

IO_P9P9

R1IO_R1

IO_R10R10

R11IO_R11

IO_R12R12

R13IO_R13

IO_R2R2

R3IO_R3

IO_R4R4

IO_R5

P1IO_P1

P10IO_P10

IO_P11P11

IO_P12P12

IO_P16P16

IO_P2P2

P3IO_P3

P4IO_P4

IO_P5P5

P6IO_P6

IO_P7

N13

IO_N15N15

N16IO_N16

N2IO_N2

IO_N3N3

N4IO_N4

N5IO_N5

IO_N6N6

IO_N7N7

N8IO_N8

IO_N9N9

IO_M16

M2IO_M2

M3IO_M3

M4IO_M4

M5IO_M5

M8IO_M8

M9IO_M9

IO_N1N1

N10IO_N10

IO_N11N11

N12IO_N12

IO_N13

L15IO_L15

IO_L16L16

L2IO_L2

L3IO_L3

IO_L4L4

M1IO_M1

M12IO_M12

M13IO_M13

M14IO_M14

M15IO_M15

M16

IO_K1

K13IO_K13

IO_K14K14

K15IO_K15

IO_K16K16

IO_K2K2

K3IO_K3

IO_K4K4

IO_L1L1

L13IO_L13

IO_L14L14

IO_G2

IO_G3G3

G4IO_G4

IO_H12H12

H13IO_H13_GLMX2

IO_H3_GLMX1H3

IO_H5H5

J12IO_J12

IO_J14J14

J4IO_J4

IO_J5J5

K1

U49

GL1H1

GL2J1

GL3J16

H16GL4

IO_G1G1

IO_G13G13

IO_G14G14

IO_G15G15

IO_G16G16

G2

1

TP159

0

2

0

apa150.2of2.fbga256

29

25

24

26

1

0

33R522

0

4

17A1

16A8

4

22

4

5

12C1

0

6.3V22uFC749

OSCON

+5R520

TP158

C7500.1uF

018B8,37D8,38B1,41B1

27

8

37D8,38A1,39A1,41A1

0

1

17B8

19

2

30

31

0

27

16A8

16A8

R691 3347A8

22

2

12D1

1

2

23

16A8

U48

2GND OE

1

3OUTV3.3V4

39B1

3

3

33

16

12C1

2

18

33.000MHz

28

29

1

2

1

1

R521

3037D8,38A1,39A1,41B1

0

16B8

17A1,18A1

17A8,18B1

37D8,41A1

6B1

18B8,37D8,38B1,39A1,41C1

7

21

20

14C2,16B8

3

1

SYSCLK_V(7:0)

12C1

6

2

37D8,39A1,41C10

16A8

1CM_MAX

PIXIS_DEBUG(0:1)

LB_A(0:31)

IRQ*(0:11)

FAIL_LED*PASS_LED*

LB_WE*(0:3)

HOT_RST*

PCICLK_SB

SYSCLK_S(2:0)

SYSCLK_R(4:0)

LB_GPL(0:5)

CFG_PIXISOPT(0:1)

CFG_CCBPLL(0:3)

CFG_COREPLL(0:4)

CFG_SYSCLK(0:2)

CFG_HOSTMODE(0:1)

LB_D(0:31)

SYSCLK_EN

LB_CLK(0:1)

V3_AD(31:0)

SYS_REFCLK

HOTCLK

FCS*PJCS*

V3_INT*(0:1)

CF_RDYBSY*CF_CD*

PCI_CLK(0:4)

LB_CS*(0:3)

DATABLIZZARD_INTD*

V3_DEVSEL*

V3_FRAME*

V3_TRDY*V3_IRDY*

V3_STOP*

NC

NC

NC

1CM_MAX

UTHOTCLK

NC

V3_CBE*(3:0)

V3_SERR*V3_PERR*

V3_REQ*V3_GNT*

17

GROUND

8

19

38

49

NC

1

VCC

17

GROUND

8

19

38

49

NC

1

VCC

D

C

8

freescale764


5321


HPCN: Argo NavisPCI 5V-to-3V Level Translators


2:09:15 pmsemiconductorTM

31 2 4 5 6 7 8

A

B

D

Date Changed:




C

A

B

C748

12

13

20

1

15A1

15A147C1,51B1

0.1uF

47C1,51B1

18

19

22

47D1,51B1

19

18

28

0

14B8,15C1

9

8

0

15B1

14D8

1

2

3

23

15C8

51B1

29

20

21

31

30

4

5

11

10

C747

0.1uF

10

2B634

2B733

2B832

2B9

552OE

1NC

VCC17

27

15A1

15C8

242A8

252A9

412B1

312B10

302B11

292B12

402B2

392B3

372B4

362B5

35

1OE

152A1

262A10

272A11

282A12

162A2

2A318

202A4

212A5

222A6

232A7

1B1043

1B1142

1B12

531B2

521B3

511B4

1B550

481B6

471B7

461B8

451B9

56

141A12

31A2

41A3

51A4

61A5

71A6

91A7

101A8

111A9

541B1

44

7

0

1

tssop56

SN74CBTD16211DGGR

U47

21A1

121A10

131A11

47C1,51B1

14

15

22

23

6

26

2

1

26

27

47C1,51B1

47C1,51B1

47C1,51B1

9

47B1,51C1

47C1,51C1

30

3147A1,51D1 14C2,15C1

25

2

15C8

28

29

2

2

8

15B1

11

4

15A1

3

24

25

14

15

VCC_5

1

5

6

15B1

3

21

7

0

16

17

47C1,51B1

12

13

0

1

17

16

2B436

2B535

2B634

2B733

2B832

2B9

552OE

1NC

17VCC

24

2A522

2A623

2A724

2A825

2A9

412B1

312B10

302B11

292B12

402B2

392B3

37

461B8

451B9

561OE

152A1

262A10

272A11

282A12

162A2

182A3

202A4

21

1A9

541B1

441B10

431B11

421B12

531B2

521B3

511B4

501B5

481B6

471B7

1A1

121A10

131A11

141A12

31A2

41A3

51A4

61A5

71A6

91A7

101A8

11PCI_GNT*(0:2)

47C1,51C1

0

2

3

tssop56

SN74CBTD16211DGGR

U46

2PCI_FRAME*PCI_DEVSEL*PCI_IRDY*PCI_TRDY*PCI_STOP*

V3_FRAME*NC

V3_DEVSEL*V3_IRDY*

V3_TRDY*V3_STOP*V3_PERR*V3_SERR*

V3_INT*(0:1)

V3_REQ*V3_GNT*

PCI_PERR*PCI_SERR*PCI_REQ*(0:2)

PCI_PAR V3_PAR

PCI_CBE*(3:0) V3_CBE*(3:0)

PCI_INT*(0:3)

V3_AD(31:0)PCI_AD(31:0)

NC

semiconductor

TM

8765321 4

2 31 5 6 74 8

B

D


HPCN: Argo NavisGeneral Configuration


2:09:24 pm

Date Changed:

A

Engineer:Revision:

Page:Time Changed:

Title:Project:


C

A

B

D

C


4.7K

R65

4

4.7K

R58

7

7B1,14C8

R59

11K

18C1

R58

84.

7K VCC_HOT_3.3

4.7K

R66

7

R60

51K

4.7K

R65

9

R66

34.

7K

1

1

0

2

1KR

610

14B2,38B1

1KR

613

0

18B1

30A8

1KR

634

1KR

594

4.7K

R58

3

VCC_3.3

0

1

4.7K

R57

7

4.7K

R64

6

R60

11K

R66

94.

7K

4.7K

R67

3

R64

31K

R66

04.

7K

R63

51K 1K

R63

9

0

1

2

R65

84.

7K

38C1,55B1

48D7

4.7K

R56

7

0

R61

91K 1K

R62

3

4.7K

R58

5

2

3

VCC_3.3

1KR

598

R58

24.

7K

1KR

592

R59

51K

2

1

R67

14.

7K

R60

31K

R66

64.

7K

R65

04.

7K

1KR

600

R62

71K 1K

R63

1

R66

4

1KR

644

13

5 12

6 11

7 10

8 9

4.7K

sw.8spst.cts

SW3

1 16

2 15

3 14

4

R62

51K

4.7K

R58

1

47B8

47B8,50B1

47B8

VCC_3.3

1KR

621

7 10

8 9

15C1,18B11

1KR

604

2 15

3 14

4 13

5 12

6 11

6 11

7 10

8 9

SW6

sw.8spst.cts

1 16

1 16

2 15

3 14

4 13

5 12

5 12

6 11

7 10

8 9

sw.8spst.cts

SW5

SW4

sw.8spst.cts

1 16

2 15

3 14

4 13

1KR

590

R57

04.

7K

R64

54.

7K

4.7K

R64

9

R57

44.

7K

2

18B1

4.7K

R65

1

18B1

4.7K

R57

1

1K 1KR

637

4.7K

1KR

608

R63

3

4.7K

R57

3

R67

6R

674

4.7K

R64

74.

7K

R60

71K

4.7K

R66

2

3

R65

34.

7K

4.7K

R65

7

15C1,18A1

R58

91K

18B1

2

1KR

618

3

R66

84.

7K

3

R61

41K

0

4

3

R66

14.

7K

VCC_3.3

1KR

628

15D1

1KR

620

R62

41K

15C1

13C1,14B21

0

R61

61K

5 12

6 11

7 10

8 9

R56

64.

7K

SW2

sw.8spst.cts

1 16

2 15

3 14

4 13

1

4.7K

R67

5

0

0

1

R58

44.

7K

R61

11K

VCC_3.3

14B2

R58

64.

7K

VCC_3.3

1KR

596

R59

31K

40C8

18C1

R63

21K

VCC_3.3

14D8,18A1

4.7K

R56

5 1K

R62

6

R63

01K

4

6

1

2

R56

84.

7K

R61

71K

1KR

642

R65

54.

7K

4.7K

R56

9

4.7K

R65

6

014C8,18B1

13

5 12

6 11

7 10

8 9

R65

24.

7K

47B8,50B1

sw.8spst.ctsSW8

1 16

2 15

3 14

4

0

1KR

615

1KR

629

48C7,56B1

15C1,18A1

R59

71K

4.7K

R64

8

4.7K

R67

2

1KR

636

R64

01K

14B2,18B1

9C1,14D8

R63

81K

R57

64.

7K

4.7K

R57

9

1

R59

91K 1K

R60

2

1KR

612

13C1

4.7K

R67

0

R60

6

R60

91K

R62

21K

40A1

5

1K

14

4 13

5 12

6 11

7 10

8 9

sw.8spst.cts

SW1

1 16

2 15

3

R64

11K

R58

04.

7K

R57

84.

7K

4.7K

R66

5

CFG_ASMP

R57

24.

7K

4.7K

R57

5

CFG_DDRDEBUG

CFG_HOSTMODE(0:1)

CFG_BOOTSEQ(0:1)

CFG_IOPORTS(0:3)

CFG_REFCLKSEL(2:0)

CFG_FLASHBANKCFG_FLASHMAP

CFG_PIXISOPT(0:1)

CFG_FLASHWP*

CFG_CPUBOOTCFG_BOOTADDR

CFG_SERROM_ADDR

ACZ_SDOUT

ACZ_SYNC

SUSLEDACB_SDOUT

ACB_SYNC

ACPWRCFG_IDWP

CFG_REFSPREAD

CFG_LADOPT(0:1)

CFG_PORTDIV

CFG_COREPLL(0:4)

CFG_CCBPLL(0:3)

CFG_BOOTLOC(0:3)

CFG_SYSCLK(0:2)

CFG_PLATVDD

CFG_VID(6:0)

CFG_MEMDEBUG

4

VCC_3.3

31

42

10

15

21

28

34

39

45

GND

18

7

(MSB)

B2, B5, B8, B11

GROUND

A2, A5, A8, A11, A14

(LSB)

4

VCC_3.3

31

42

10

15

21

28

34

39

45

GND

18

7

semiconductor

TM

43

Route TSECxxx lines through pin 2 of these330-ohm resistors (no stubs in path).

1 2 3 4

21

7 8

A

B

5 6


Revision:Page:

D

Date Changed:Project:7700 W. Parmer LnAustin, Texas 78729

C

Title:

Place near CPU.

D

C



HPCN: Argo NavisConfiguration Buffer; COP and Debug


2:09:33 pm

A

B

87

KEY

CPU JTAG Header

65

0

14C8,17A8

R31

310

.0K

29

1OE1

48OE2

25OE3

OE424

17C8

2

1

2

14C2

14

16

17

30

29

27

26

19

20

22

23

37

8

9

11

12

36

35

33

32

13

47

46

44

43

2

3

5

6

41

40

38

3

1

2

3

tssop48

A4

A3

A2

A1

U2374lvc16244adgg.tssop48

Y1

Y2

Y3

Y4

VCC_3.31K

R32

0

1

2

6

7 8

9

19B8

330R329

11 12

13 14

15 16

2

3 4

5

19C1

0

219C1

J26header_riscwatch

1

10

3

3

17A8

0

1

0

19C1

R330 330

1

TP109

37A8

1

10.0

KR

312

31

3

15C1,17A1

330R331

R326 330

330R692

2

3

27

30B8,31B8

0

330R325

3

17C8

0

0

1

0

1

0

TP111

0

5

3

TP112

1

1

4

TP110

1

10.0

KR

314

37A8,41C1

14C2

30

R332 330

3

15A8,37D8,38B1,41B1

37A8,41B1

R324 330

28

29

0

14C2

2

2

30B1,31B1330R323

1

0

4

19B8

19B8

2

3

10.0

KR

318

14D8,17B1

1

4

R31

710

.0K

R31

910

.0K

30

15A8,37D8,38B1,39A1,41C1

10.0

KR

315

330

2

17C8

17B8

10.0

KR

316

R328

17C8

15C1,17A8

1

R327

OE248

OE325

24OE4

15C1,17B10

3

19B8

19B8

330

17

30

29

27

26

19

20

22

23

OE11

37

8

9

11

12

36

35

33

32

13

14

16

46

44

43

2

3

5

6

41

40

38

D6nA10

D6p

D7nB10

D7pB12

30A1,31A1

Y4

Y3

Y2

Y1

74lvc16244adgg.tssop48U22

A1

A2

A3

A4

tssop48

47

D1nB1

D1pB3

A6D2n

A4D2p

D3nB4

D3pB6

A9D4n

A7D4p

D5nB7

D5pB9

A12

14C2

P8conn.banjo_alt

A15CLK_QUALn

CLK_QUALpA13

A3D0n

A1D0p

0

14B2,17B8

19C1

19B8

0

R157 330

R32

110

.0K

19C1

19C1

NC

D1_MSRCID(4:0)

CFG_MEMDEBUGCFG_DDRDEBUG

CFG_BOOTSEQ(0:1) LB_GPL(0:5)

CFG_IOPORTS(0:3) TSEC4_TXD(3:0)

CFG_CPUBOOT

NC NC

LB_LAD(0:31)

LB_DP(0:3)

LB_WE*(0:3)

CFG_BOOTADDR TSEC1_TXD(3:0)CFG_PORTDIV

10.0

KR

322

NCMDVAL1

D2_MSRCID(4:0)MDVAL2

TRIG_OUTTRIG_IN

CFG_CCBPLL(0:3)

CFG_COREPLL(0:4)

LB_LA(27:31)

CFG_BOOTLOC(0:3) TSEC2_TXD(3:0)

CFG_HOSTMODE(0:1)

NC

NC

NC

NC

NC

CFGDRV*

CFG_LADOPT(0:1)

COP_TRST*

CKSTP_IN*

CKSTP_OUT*

COP_SRST*CPU_TMS

CPU_TDOCPU_TDI

NC

CPU_TCK

COP_HRST*


Revision:Page:

and external clock term.

Project:Freescale Semiconductor

Austin, Texas 78729

C

A

Option: EMI Suppression

TMfreescale

B

D

C

semiconductor

2 87654

5

1 3

2 31 4

Date Changed:

6


HPCN: Argo NavisMC8641D System Interfaces


2:09:43 pm

7 8

A

Title:

CLKOUT: Place outsidethe socket outline on thetop layer.

IRQ[0:7] Pullup/PulldownsMPC8641 V1.0("PD4") - PulldownsMPC8641 V2.0("PD6") - Pullups

B

D

7700 W. Parmer Ln

VCC_3.3

3

4

36B1

11

4.7K

R10

4

4.7K

R86

4.7K

R84

10

6

4.7K

R87

54C1

18C8

14C2,56B1

18C8

TP8

0

0

1

3

4

18D8

14D2,46C8,54B1

2

3

4

15C8,32A1,46C8

R11

54.

7K

No_Stuff

R8

1K

4.7K

R96

R11

34.

7K1KR

111

4.7K

R10

2

R95

4.7K

2

7

TP12

4.7K

R11

6

VCC_3.3

5

1

9

18D1

14C2

18D8

13A8

TP10

R99

4.7K

4.7K

R98

40A8

14C2

4.7K

R10

0

TP14

R10

34.

7K

18D8

R11

44.

7K

TP11

36A1

13C1,23D1,24D1,27D1,28D1,#6

8

14C2

18D8

54C1

18D1

TP13

14C2

0

R699

No_Stuff

R97

4.7K

R118

14C2

VCC_3.3 VCC_3.3

R698

0

R11

21K

0

No_Stuff

100pF

C1

1KR

109

0

R10

14.

7K

R89

4.7K

49.9

R7

36B1

TP15

4.7K

R94

R93

4.7K

No_Stuff

12B8

TP4

TP5

D31

A32UART_SOUT2

J17

18D1

40A8

18C1

R11

01K

TMSF18

TRIG_INJ14

J13TRIG_OUT_READY_QUIESCE

A17TRST

UART_CTS1A31

B31UART_CTS2

UART_RTS1C31

E30UART_RTS2

B32UART_SIN1

C32UART_SIN2

UART_SOUT1C21SRESET_1

G16SYSCLK

TCKH18

TDIJ18

TDOG18

C16TEST_MODE0

TEST_MODE1E17

D18TEST_MODE2

TEST_MODE3D16

AA11

Y11

AD24

LSSD_MODEC18

MCP_0F17

H17MCP_1

J16

D19

RTCK17

SMI_0L15

SMI_1L16

SRESET_0C20

C30

IRQ11_DMA_DDONE3D30

IRQ2H27

IRQ3J23

IRQ4M23

IRQ5J27

IRQ6F28

IRQ7J24

IRQ8_AUX_CLKOUTL23

B30IRQ9_DMA_DREQ3

IRQ_OUTJ26

AG26

DMA_DREQ0E31

DMA_DREQ1E32

HRESETB18

HRESET_REQK18

IIC1_SCLB17

A16IIC1_SDA

IIC2_SCLB21

A21IIC2_SDA

G28IRQ0

IRQ1G29

IRQ10_DMA_DACK3

H15D1_MSRCID3

G15D1_MSRCID4

D2_MSRCID0E16

D2_MSRCID1C17

D2_MSRCID2F16

D2_MSRCID3H16

D2_MSRCID4K16

D32DMA_DACK0

DMA_DACK1F30

DMA_DDONE0F31

DMA_DDONE1F32

18D1

SYSTEM

mc8641d.1of9.system.cbga1023U32

ASLEEPC19

L18CKSTP_IN

CKSTP_OUTL17

CLK_OUTB16

F15D1_MSRCID0

D1_MSRCID1K15

K14D1_MSRCID2

R88

4.7K

36B1

36B1

36A1

R117 0

1

TP9

TP7

TP6

R91

4.7K

4.7K

R90

2

13D1,23D1,24D1,27D1,28D1,#6

TP3

4.7K

R92

R10

84.

7K

14C2

0

R83

4.7K

4.7K

R10

7

No_Stuff

0R6

18D1

R85

4.7K

4.7K

R10

6

TP16

D2_MDVALMDVAL2

TEMP_ANODETEMP_CATHODE

SMI*

RSVD10

ASLEEP

R10

54.

7K

I2C1_SCL

CPU_TDICPU_TDOCPU_TCKCPU_TMSCPU_TRST*

RTC_CLK

HRESET_REQ*

D1_MSRCID(4:0)

UART2_RXD

SRESET_0*SRESET_1*

D2_MSRCID(4:0)

MDVAL1D1_MDVAL

I2C2_SCL

UART2_TXD

I2C2_SDA

UART1_RXDUART1_TXD

UART1_RTS*UART1_CTS*

RSVD9

TRIG_OUTTRIG_IN

CPU_HRST*

I2C1_SDA

SYSCLK

CKSTP_IN*CKSTP_OUT*

TEMP_ANODE

IRQ*(0:11)

SPARE1SPARE01*

TEMP_CATHODE

Engineer:Project:

B

Austin, Texas 78729

B

D

Date Changed:

placement.

TM

8

D

C

Bypass Capacitor PlacementRefer to design workbook for detailed

semiconductor

2

2

7

C


3

FOR MC8641D: V1.0

1

3

654

7

Page:

VCORE_0 and VCORE_1 are connected

1 4 5 6

Revision:7700 W. Parmer Ln

A

internally.

8

Time Changed:Gary Milliorn

1.0320

HPCN: Argo NavisMC8641D Power


2:09:52 pmTitle:

A

C1140.1uF 0.1uF

C120

0.1uFC65

0.1uFC107

C690.1uF

VDD_ENET_IO

C95

C870.1uF

7C1

0.1uFC100

0.1uF

C104

C1150.1uF

0.1uFC83

R62

10

0

1 TM freescale - NXP Semiconductors · 2018. 8. 21. · BK 1 RD 2 BL 3 + 14C8 VCC_HOT_3.3 C32 330uF 25V + VCC_12 C35 330uF 25V + 330uF C33 25V 17 GND_P17 GND_P3 3 GND_P5 5 GND_P7

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