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1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

Dec 22, 2015

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Page 1: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Synchronous Sequential Circuit Analysis

Page 2: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Synchronous Sequential Circuit

• State Memory – A set of n edge-triggered flip-flops that store the current state of the machine

– All flip-flops are triggered from the same master clock signal

– All change state together

• Combinational circuit

– Next state logic

– Output logic – Mealy and Moore

Combinational

circuit

Inputs

State Memory

Outputs

Clock

CurrentState

NextState

Page 3: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Mealy Model

next state = F (current state, inputs)

outputs = G (current state, inputs)

Page 4: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Moore Model

next state = F (current state, inputs)

outputs = G (current state)

Page 5: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Analysis - Goals

• Characterize as Mealy or Moore machine

• Determine next state equations, i.e., find the function F

– next state = F (current state, inputs)

• Determine output equations

– Meally: outputs = F (current state, inputs), or

– Moore: outputs = F (current state)

• Express as machine behavior

– State table, or

– State diagram

• Formulate English description of machine behavior

Page 6: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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An example sequential circuit

• A sequential circuit with two JK flip-flops

• State or memory: Q1Q0

• One input: X; One output: Z

Page 7: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State table of example circuit

Present State I nputs Next State OutputsQ1 Q0 X Q1 Q0 Z

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Page 8: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Output Equations

• From the diagram, you can see that

Z = Q1Q0X

Mealy model circuit !!!

Present State I nputs Next State OutputsQ1 Q0 X Q1 Q0 Z

0 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

Page 9: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Next State Equations – Q(t+1)

• Find the flip-flop input equations/excitation equations

• Substitute excitation equations in the flip-flop’s characteristic equation

J1 = X’ Q0

K1 = X + Q0

J0 = X + Q1

K0 = X’

Page 10: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Next State Equations – Q(t+1)

• Next state equations:

– Q1(t+1) = K1’Q1(t) + J1Q1’(t)

= (X + Q0(t))’ Q1(t) + X’ Q0 (t) Q1’(t)

= X’ (Q0(t)’ Q1(t) + Q0(t) Q1(t)’)

= X’ (Q0(t) Q1(t))

– Q0(t+1) = K0’Q0(t) + J0Q0’(t)

= X Q0(t) + (X + Q1(t)) Q0’(t)

= X + Q0(t)’ Q1(t)

• Excitation equations:

– J1 = X’ Q0 and K1 = X + Q0

– J0 = X + Q1 and K0 = X’

• Characteristic equation of the JK flip-flop:

– Q(t+1) = K’Q(t) + JQ’(t)

Page 11: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Table & Next State Equations

• Q1(t+1) = X’ (Q0(t) Q1(t))

– Q1=0, Q0=0, X= 0 => Q1(t+1)= 0

• Q0(t+1) = X + Q0(t)’ Q1(t)

– Q1=0, Q0=0, X= 0 => Q0(t+1)= 0

Present State I nputs Next State OutputsQ1 Q0 X Q1 Q0 Z

0 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

0 0

Page 12: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Table & Next State Equations

• Q1(t+1) = X’ (Q0(t) Q1(t))

– Q1=0, Q0=1, X= 1 => Q1(t+1)= 0

• Q0(t+1) = X + Q0(t)’ Q1(t)

– Q1=0, Q0=1, X= 1 => Q0(t+1)= 1

Present State I nputs Next State OutputsQ1 Q0 X Q1 Q0 Z

0 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1

0 0

0 1

Page 13: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Table & Next State Equations

• Q1(t+1) = X’ (Q0(t) Q1(t))

• Q0(t+1) = X + Q0(t)’ Q1(t)

Present State I nputs Next State OutputsQ1 Q0 X Q1 Q0 Z

0 0 0 0 0 00 0 1 0 1 00 1 0 1 0 00 1 1 0 1 01 0 0 1 1 01 0 1 0 1 01 1 0 0 0 01 1 1 0 1 1

Page 14: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Table & Characteristic Table

• The general JK flip-flop characteristic equation is:

Q(t+1) = K’Q(t) + JQ’(t)

• We can also determine the next state for each input/current state combination directly from the characteristic table

J K Q(t+1) Operation

0 0 Q(t) No change0 1 0 Reset1 0 1 Set1 1 Q’(t) Complement

Page 15: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Table & Characteristic Table

• With these equations, we can make a table showing J1, K1, J0 and K0

for the different combinations of present state Q1Q0 and input X

J1 = X’ Q0 J0 = X + Q1

K1 = X + Q0 K0 = X’

Present State I nputs Flip-flop I nputsQ1 Q0 X J 1 K1 J 0 K0

0 0 0 0 0 0 10 0 1 0 1 1 00 1 0 1 1 0 10 1 1 0 1 1 01 0 0 0 0 1 11 0 1 0 1 1 01 1 0 1 1 1 11 1 1 0 1 1 0

Page 16: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Table & Characteristic Table

Present State I nputs FF I nputs Next State Q1 Q0 X J 1 K1 J 0 K0 Q1 Q0

0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 0

J K Q(t+1)

0 0 Q(t) 0 1 0 1 0 1 1 1 Q’(t)

Page 17: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Table & Characteristic Table

Present State I nputs FF I nputs Next State Q1 Q0 X J 1 K1 J 0 K0 Q1 Q0

0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 0

J K Q(t+1)

0 0 Q(t) 0 1 0 1 0 1 1 1 Q’(t)

0

Page 18: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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A different look

Present State I nputs Next State OutputsQ1 Q0 X Q1 Q0 Z

0 0 0 0 0 00 0 1 0 1 00 1 0 1 0 00 1 1 0 1 01 0 0 1 1 01 0 1 0 1 01 1 0 0 0 01 1 1 0 1 1

Present State Q1 Q0

Next StateOutput Z

Input X= 0

Input X= 1

X= 0 X= 1

0 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0

1 0 1 1 0 1 0 0

1 1 0 0 0 1 0 1

Page 19: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State diagrams (Mealy model)

Present State I nputs Next State OutputsQ1 Q0 X Q1 Q0 Z

0 0 0 0 0 00 0 1 0 1 00 1 0 1 0 00 1 1 0 1 01 0 0 1 1 01 0 1 0 1 01 1 0 0 0 01 1 1 0 1 1

• We can also represent the state table graphically with a state diagram

• A diagram corresponding to our example state table is shown below

00 01

1011

1/0

0/00/0

0/0

0/0 1/0

1/01/1

input output

state

Page 20: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Sizes of state diagrams

00 01

1011

1/0

0/00/0

0/0

0/0 1/0

1/01/1

• Always check the size of your state diagrams

– If there are n flip-flops, there should be 2n nodes in the diagram

– If there are m inputs, then each node will have 2m outgoing arrows

• In our example,

– We have two flip-flops, and thus four states or nodes.

– There is one input, so each node has two outgoing arrows.

Page 21: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Another Mealy Circuit

Page 22: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Excitation Equations

• DD00 = EN’ = EN’ QQ00 + EN + EN QQ00’’

• DD11 = EN’ = EN’ QQ11 + EN + EN QQ11’ ’ QQ00 + EN + EN QQ11 QQ00’’

Page 23: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Next State/Output Equations

• QQ00(t+1) = D(t+1) = D00 = EN’ = EN’ QQ00 + EN + EN QQ00’’

• QQ11(t+1) = D(t+1) = D11 = EN’ = EN’ QQ11 + EN + EN QQ11’ ’ QQ00 + EN + EN QQ11 QQ00’’

• MAX= EN MAX= EN QQ11 QQ00

Page 24: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Mealy State Table

Present State Q1 Q0

Next StateOutput MAX

Input EN= 0

Input EN= 1

X= 0 X= 1

0 0 0 0 0 1 0 0

0 1 0 1 1 0 0 0

1 0 1 0 1 1 0 0

1 1 1 1 0 0 0 1

• QQ00(t+1) = D(t+1) = D00 = EN’ = EN’ QQ00 + EN + EN QQ00’’

• QQ11(t+1) = D(t+1) = D11 = EN’ = EN’ QQ11 + EN + EN QQ11’ ’ QQ00 + EN + EN QQ11 QQ00’’

• MAX= EN MAX= EN QQ11 QQ00

Page 25: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Mealy State Diagram

Present State Q1 Q0

Next StateOutput MAX

Input EN= 0

Input EN= 1

X= 0 X= 1

0 0 0 0 0 1 0 0

0 1 0 1 1 0 0 0

1 0 1 0 1 1 0 0

1 1 1 1 0 0 0 1

Page 26: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Moore Circuit

X

Remove input connection to output logic => Moore machine

Page 27: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Next State/Output Equations

• QQ00(t+1) = D(t+1) = D00 = EN’ = EN’ QQ00 + EN + EN QQ00’’

• QQ11(t+1) = D(t+1) = D11 = EN’ = EN’ QQ11 + EN + EN QQ11’ ’ QQ00 + EN + EN QQ11 QQ00’’

• MAX= MAX= QQ11 QQ00

X

Page 28: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Moore State Table

Present State Q1 Q0

Next State

Output MAX

Input EN= 0

Input EN= 1

0 0 0 0 0 1 0

0 1 0 1 1 0 0

1 0 1 0 1 1 0

1 1 1 1 0 0 1

• QQ00(t+1) = D(t+1) = D00 = EN’ = EN’ QQ00 + EN + EN QQ00’’

• QQ11(t+1) = D(t+1) = D11 = EN’ = EN’ QQ11 + EN + EN QQ11’ ’ QQ00 + EN + EN QQ11 QQ00’’

• MAX= MAX= QQ11 QQ00

Page 29: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Moore State Diagram

Present State Q1 Q0

Next StateOutput MAX

Input EN= 0

Input EN= 1

X= 0 X= 1

0 0 0 0 0 1 0 0

0 1 0 1 1 0 0 0

1 0 1 0 1 1 0 0

1 1 1 1 0 0 0 1

Page 30: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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State Transitions

• MAX : Output of the Mealy circuit

• MAXS : Output of the Moore circuit

Page 31: 1 Synchronous Sequential Circuit Analysis. 2 Synchronous Sequential Circuit State Memory – A set of n edge-triggered flip-flops that store the current.

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Sequential circuit analysis summary

• To analyze sequential circuits, you have to:

– Find Boolean expressions for the outputs of the circuit and the

flip-flop inputs

– Use these expressions to fill in the output and flip-flop input columns

in the state table

– Finally, use the characteristic equation or characteristic table of theflip-flop to fill in the next state columns.

• The result of sequential circuit analysis is a state table or a state

diagram describing the circuit