1 Registers Memories Basic Up

8/12/2019 1 Registers Memories Basic Up

1/28

Registers and memories

Ismail MAJDOUB

[email protected]


2/28

Digital Signal Processor 2

A register lives within the microrocessor and stores small

!uantities o" data "or immediate use. A register is just a collection o" "li#"los. A "li#"lo can onl$

store one bit so to handle %& bits at a time we would need%& "li#"los and would re"er to this as a %bit register.

'he register has two distinct grous o" connections( thedata bits and the control signals.

Register


3/28


)hi"t registers

*+emle ( )ending data seriall$


4/28


'he bene"it o" using a rotate rather than a shi"t register isthat the data is not destro$ed.

Rotate register


5/28


It is an -#bit register but it is unusual in that each bit storedis !uite indeendent o" all the others.

A status register or "lag register is lie a window to see into

the worings o" the microrocessor. 'imer "lag

)ign "lag ( A negative number has a / in bit 0 and aositive number has a 1 in bit 0

2ero "lag ( sends all its time watching "or a result o"3ero.

4lag register


6/28


'he memor$ comes in an integrated circuit looing lie asmall microrocessor and is usuall$ called a memor$ chi.

Inside5 there are a large number o" registers5 hundreds5thousands5 millions deending on the si3e o" the memor$.

Incidentall$5 when we are re"erring to memories5 we use

the word 6cell7 instead o" register even though the$ are thesame thing.

Memories


7/28


Memories

Read 8rite Memor$

9olatile Memor$ :on#volatile memor$


8/28


'he letters RAM stands "or Random Access Memor$

In rehistoric comuting da$s5 the memor$ would beloaded in order rather lie a shi"t register. ;se!uentialaccess memor$ 'o overcome this roblem5 we develoed a wa$ to access

an$ memor$ location ?? Random Access Memor$

RAM


9/28


)tatic RAM ( constructed o" "li#"los

D$namic RAM ( store the in"ormation in caacitors

:eed 6re"reshing7 at intervals o" about & ms b$ a DRAMcontrol circuit.

'wo t$es o" RAM


10/28


ROMs are used to store in"ormation on ermanent basis.

In the most cases5 ROM are used to store "irmware


11/28


Mased ROM ( is manu"actured to our seci"ication andcannot be changed.

rogrammable ROM


12/28


*ach location in a memor$ is given a number5 called an address.

'he / locations o" memor$ would be numbered "rom 1 to /C5 or inbinar$ 1111////

Accessing Memor$

generall$ &En ? number o" locations where n is the number o" bits in the address.


13/28


'he memor$ organi3ation is alwa$s !uoted as


14/28


'he rocessor5 along with the so"tware5 treats memor$ asone large one#dimensional arra$5 called a memor$ ma

'he s$stem designer decide in what wa$ the availablememor$ is to be used.

Memor$ mas


15/28


'he rocessor5 along with the so"tware5 treats memor$ asone large one#dimensional arra$5 called a memor$ ma

'he s$stem designer decide in what wa$ the availablememor$ is to be used.

Memor$ mas


16/28


Huestions (

ow man$ ilob$tes o" User RAM


17/28


18/28


'he most basic microrocessor based s$stem

Instructions

Internal or e+ternal

B


19/28


Buses connect the microrocessor inernall$ and to the rest

o" the s$stem.

A bus is there"ore a collection o" conductors roviding asimilar "unction.

*+amle (

an -#bit microrocessor normall$ uses - connectorsto carr$ the data between the microrocessor andthe memor$.

Buses

B


20/28


In a microrocessor#based s$stem we have three mainbuses(

Data bus ( is a two#wa$ bus5 In"ormation going into themicrorocessor and results coming out.

Address bus ( carries addresses and is a one#wa$ bus"rom the microrocessor to the memor$ or otherdevices

Kontrol bus ( carries commands "rom the KU andreturn status signals "rom the devices

*+amle ( chi select5 readGwrite ...

Buses

I tG t t i it


21/28


An IGO subs$stem can be as simle as a basic electroniccircuit that connects the rocessor directl$ to an IGO device


22/28


InutGoutut circuits

A ti l i t


23/28


8e need to modi"$ some data in"ormation into the memor$?? some RAM must be added.

'he microrocessor is now controlling the oeration o"three chis( ROM5 RAM and IGO ?? it needs to send chiselect and readGwrite in"ormation along the control bus.

A ractical microrocessor s$stem



24/28





25/28


*+amle ( )end the number &C which is in the ROM andstore it in the RAM at address &C11.

/# 'he microrocessor has to collect the instruction"rom an address in ROM. It does this b$ utting theaddress onto the address bus.

'he address is alied to the ROM and the RAM aswell as the address decoder. 'his will not cause an$roblems because all the chi selects will be switchedo"" at the moment. 8hen the logic gates within the

address decoder resonds to the inut "rom theaddress bus the result will be that the ROM is switchedon and the other two are et o"".




26/28



%# )witching on the ROM will mean that it taes in theaddress "rom the address bus. Inside the ROM chi5 therow and column decoders activate one o" the memor$locations and the binar$ number stored at that location

is laced on the data bus b$ switching on the tri#statebu""ers. As soon as the in"ormation is read5the chiselect will switch the ROM chi o"".

# 'he in"ormation which is now on the data bus is readb$ the microrocessor. It is an instruction which can beinterreted as 6go to address 411 and read thenumber that is stored in that address7.




27/28



C# In resonse to this instruction5 the microrocessoruts the address 411 onto the address bus.

# 'he address decoder alies this number to its logicgates and this results in the chi select o" the ROM chibeing switched on again. 'he ROM chi accets theaddress 411 into its row and column decoders andthen uts the number &C onto the data bus.




28/28



0# 'his number is stored temoraril$ in themicrorocessor.

-# 'he microrocessor then uts the number &C11onto the address bus and the address decoder uts asignal on the chi select o" the RAM chi to switch it on.It then sends a logic / on the readGwrite line. 'he RAMis switched on and it is told to read the data on the data

bus. 'he readGwrite line goes to the IGO chi as well butagain5this causes no roblem because its chi selectline is eeing it switched o"".


1 Registers Memories Basic Up

Documents